arch/arm/plat-mxc/time.c

   1 /*
   2  *  linux/arch/arm/plat-mxc/time.c
   3  *
   4  *  Copyright (C) 2000-2001 Deep Blue Solutions
   5  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   7  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA 02110-1301, USA.
  22  */
  23
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk.h>
  28
  29 #include <mach/hardware.h>
  30 #include <asm/sched_clock.h>
  31 #include <asm/mach/time.h>
  32 #include <mach/common.h>
  33
  34 /*
  35  * There are 2 versions of the timer hardware on Freescale MXC hardware.
  36  * Version 1: MX1/MXL, MX21, MX27.
  37  * Version 2: MX25, MX31, MX35, MX37, MX51
  38  */
  39
  40 /* defines common for all i.MX */
  41 #define MXC_TCTL                0x00
  42 #define MXC_TCTL_TEN            (1 << 0) /* Enable module */
  43 #define MXC_TPRER               0x04
  44
  45 /* MX1, MX21, MX27 */
  46 #define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
  47 #define MX1_2_TCTL_IRQEN        (1 << 4)
  48 #define MX1_2_TCTL_FRR          (1 << 8)
  49 #define MX1_2_TCMP              0x08
  50 #define MX1_2_TCN               0x10
  51 #define MX1_2_TSTAT             0x14
  52
  53 /* MX21, MX27 */
  54 #define MX2_TSTAT_CAPT          (1 << 1)
  55 #define MX2_TSTAT_COMP          (1 << 0)
  56
  57 /* MX31, MX35, MX25, MX5 */
  58 #define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
  59 #define V2_TCTL_CLK_IPG         (1 << 6)
  60 #define V2_TCTL_FRR             (1 << 9)
  61 #define V2_IR                   0x0c
  62 #define V2_TSTAT                0x08
  63 #define V2_TSTAT_OF1            (1 << 0)
  64 #define V2_TCN                  0x24
  65 #define V2_TCMP                 0x10
  66
  67 #define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
  68 #define timer_is_v2()   (!timer_is_v1())
  69
  70 static struct clock_event_device clockevent_mxc;
  71 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  72
  73 static void __iomem *timer_base;
  74
  75 static inline void gpt_irq_disable(void)
  76 {
  77         unsigned int tmp;
  78
  79         if (timer_is_v2())
  80                 __raw_writel(0, timer_base + V2_IR);
  81         else {
  82                 tmp = __raw_readl(timer_base + MXC_TCTL);
  83                 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
  84         }
  85 }
  86
  87 static inline void gpt_irq_enable(void)
  88 {
  89         if (timer_is_v2())
  90                 __raw_writel(1<<0, timer_base + V2_IR);
  91         else {
  92                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
  93                         timer_base + MXC_TCTL);
  94         }
  95 }
  96
  97 static void gpt_irq_acknowledge(void)
  98 {
  99         if (timer_is_v1()) {
 100                 if (cpu_is_mx1())
 101                         __raw_writel(0, timer_base + MX1_2_TSTAT);
 102                 else
 103                         __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
 104                                 timer_base + MX1_2_TSTAT);
 105         } else if (timer_is_v2())
 106                 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 107 }
 108
 109 static void __iomem *sched_clock_reg;
 110
 111 static u32 notrace mxc_read_sched_clock(void)
 112 {
 113         return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 114 }
 115
 116 static int __init mxc_clocksource_init(struct clk *timer_clk)
 117 {
 118         unsigned int c = clk_get_rate(timer_clk);
 119         void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
 120
 121         sched_clock_reg = reg;
 122
 123         setup_sched_clock(mxc_read_sched_clock, 32, c);
 124         return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
 125                         clocksource_mmio_readl_up);
 126 }
 127
 128 /* clock event */
 129
 130 static int mx1_2_set_next_event(unsigned long evt,
 131                               struct clock_event_device *unused)
 132 {
 133         unsigned long tcmp;
 134
 135         tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
 136
 137         __raw_writel(tcmp, timer_base + MX1_2_TCMP);
 138
 139         return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
 140                                 -ETIME : 0;
 141 }
 142
 143 static int v2_set_next_event(unsigned long evt,
 144                               struct clock_event_device *unused)
 145 {
 146         unsigned long tcmp;
 147
 148         tcmp = __raw_readl(timer_base + V2_TCN) + evt;
 149
 150         __raw_writel(tcmp, timer_base + V2_TCMP);
 151
 152         return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
 153                                 -ETIME : 0;
 154 }
 155
 156 #ifdef DEBUG
 157 static const char *clock_event_mode_label[] = {
 158         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 159         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 160         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 161         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 162 };
 163 #endif /* DEBUG */
 164
 165 static void mxc_set_mode(enum clock_event_mode mode,
 166                                 struct clock_event_device *evt)
 167 {
 168         unsigned long flags;
 169
 170         /*
 171          * The timer interrupt generation is disabled at least
 172          * for enough time to call mxc_set_next_event()
 173          */
 174         local_irq_save(flags);
 175
 176         /* Disable interrupt in GPT module */
 177         gpt_irq_disable();
 178
 179         if (mode != clockevent_mode) {
 180                 /* Set event time into far-far future */
 181                 if (timer_is_v2())
 182                         __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
 183                                         timer_base + V2_TCMP);
 184                 else
 185                         __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
 186                                         timer_base + MX1_2_TCMP);
 187
 188                 /* Clear pending interrupt */
 189                 gpt_irq_acknowledge();
 190         }
 191
 192 #ifdef DEBUG
 193         printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
 194                 clock_event_mode_label[clockevent_mode],
 195                 clock_event_mode_label[mode]);
 196 #endif /* DEBUG */
 197
 198         /* Remember timer mode */
 199         clockevent_mode = mode;
 200         local_irq_restore(flags);
 201
 202         switch (mode) {
 203         case CLOCK_EVT_MODE_PERIODIC:
 204                 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
 205                                 "supported for i.MX\n");
 206                 break;
 207         case CLOCK_EVT_MODE_ONESHOT:
 208         /*
 209          * Do not put overhead of interrupt enable/disable into
 210          * mxc_set_next_event(), the core has about 4 minutes
 211          * to call mxc_set_next_event() or shutdown clock after
 212          * mode switching
 213          */
 214                 local_irq_save(flags);
 215                 gpt_irq_enable();
 216                 local_irq_restore(flags);
 217                 break;
 218         case CLOCK_EVT_MODE_SHUTDOWN:
 219         case CLOCK_EVT_MODE_UNUSED:
 220         case CLOCK_EVT_MODE_RESUME:
 221                 /* Left event sources disabled, no more interrupts appear */
 222                 break;
 223         }
 224 }
 225
 226 /*
 227  * IRQ handler for the timer
 228  */
 229 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
 230 {
 231         struct clock_event_device *evt = &clockevent_mxc;
 232         uint32_t tstat;
 233
 234         if (timer_is_v2())
 235                 tstat = __raw_readl(timer_base + V2_TSTAT);
 236         else
 237                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
 238
 239         gpt_irq_acknowledge();
 240
 241         evt->event_handler(evt);
 242
 243         return IRQ_HANDLED;
 244 }
 245
 246 static struct irqaction mxc_timer_irq = {
 247         .name           = "i.MX Timer Tick",
 248         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 249         .handler        = mxc_timer_interrupt,
 250 };
 251
 252 static struct clock_event_device clockevent_mxc = {
 253         .name           = "mxc_timer1",
 254         .features       = CLOCK_EVT_FEAT_ONESHOT,
 255         .shift          = 32,
 256         .set_mode       = mxc_set_mode,
 257         .set_next_event = mx1_2_set_next_event,
 258         .rating         = 200,
 259 };
 260
 261 static int __init mxc_clockevent_init(struct clk *timer_clk)
 262 {
 263         unsigned int c = clk_get_rate(timer_clk);
 264
 265         if (timer_is_v2())
 266                 clockevent_mxc.set_next_event = v2_set_next_event;
 267
 268         clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
 269                                         clockevent_mxc.shift);
 270         clockevent_mxc.max_delta_ns =
 271                         clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
 272         clockevent_mxc.min_delta_ns =
 273                         clockevent_delta2ns(0xff, &clockevent_mxc);
 274
 275         clockevent_mxc.cpumask = cpumask_of(0);
 276
 277         clockevents_register_device(&clockevent_mxc);
 278
 279         return 0;
 280 }
 281
 282 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 283 {
 284         uint32_t tctl_val;
 285
 286         clk_enable(timer_clk);
 287
 288         timer_base = base;
 289
 290         /*
 291          * Initialise to a known state (all timers off, and timing reset)
 292          */
 293
 294         __raw_writel(0, timer_base + MXC_TCTL);
 295         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 296
 297         if (timer_is_v2())
 298                 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
 299         else
 300                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 301
 302         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 303
 304         /* init and register the timer to the framework */
 305         mxc_clocksource_init(timer_clk);
 306         mxc_clockevent_init(timer_clk);
 307
 308         /* Make irqs happen */
 309         setup_irq(irq, &mxc_timer_irq);
 310 }