arch/arm/plat-mxc/time.c

   1 /*
   2  *  linux/arch/arm/plat-mxc/time.c
   3  *
   4  *  Copyright (C) 2000-2001 Deep Blue Solutions
   5  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   7  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA 02110-1301, USA.
  22  */
  23
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29
  30 #include <mach/hardware.h>
  31 #include <asm/sched_clock.h>
  32 #include <asm/mach/time.h>
  33 #include <mach/common.h>
  34
  35 /*
  36  * There are 2 versions of the timer hardware on Freescale MXC hardware.
  37  * Version 1: MX1/MXL, MX21, MX27.
  38  * Version 2: MX25, MX31, MX35, MX37, MX51
  39  */
  40
  41 /* defines common for all i.MX */
  42 #define MXC_TCTL                0x00
  43 #define MXC_TCTL_TEN            (1 << 0) /* Enable module */
  44 #define MXC_TPRER               0x04
  45
  46 /* MX1, MX21, MX27 */
  47 #define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
  48 #define MX1_2_TCTL_IRQEN        (1 << 4)
  49 #define MX1_2_TCTL_FRR          (1 << 8)
  50 #define MX1_2_TCMP              0x08
  51 #define MX1_2_TCN               0x10
  52 #define MX1_2_TSTAT             0x14
  53
  54 /* MX21, MX27 */
  55 #define MX2_TSTAT_CAPT          (1 << 1)
  56 #define MX2_TSTAT_COMP          (1 << 0)
  57
  58 /* MX31, MX35, MX25, MX5 */
  59 #define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
  60 #define V2_TCTL_CLK_IPG         (1 << 6)
  61 #define V2_TCTL_CLK_PER         (2 << 6)
  62 #define V2_TCTL_FRR             (1 << 9)
  63 #define V2_IR                   0x0c
  64 #define V2_TSTAT                0x08
  65 #define V2_TSTAT_OF1            (1 << 0)
  66 #define V2_TCN                  0x24
  67 #define V2_TCMP                 0x10
  68
  69 #define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
  70 #define timer_is_v2()   (!timer_is_v1())
  71
  72 static struct clock_event_device clockevent_mxc;
  73 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  74
  75 static void __iomem *timer_base;
  76
  77 static inline void gpt_irq_disable(void)
  78 {
  79         unsigned int tmp;
  80
  81         if (timer_is_v2())
  82                 __raw_writel(0, timer_base + V2_IR);
  83         else {
  84                 tmp = __raw_readl(timer_base + MXC_TCTL);
  85                 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
  86         }
  87 }
  88
  89 static inline void gpt_irq_enable(void)
  90 {
  91         if (timer_is_v2())
  92                 __raw_writel(1<<0, timer_base + V2_IR);
  93         else {
  94                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
  95                         timer_base + MXC_TCTL);
  96         }
  97 }
  98
  99 static void gpt_irq_acknowledge(void)
 100 {
 101         if (timer_is_v1()) {
 102                 if (cpu_is_mx1())
 103                         __raw_writel(0, timer_base + MX1_2_TSTAT);
 104                 else
 105                         __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
 106                                 timer_base + MX1_2_TSTAT);
 107         } else if (timer_is_v2())
 108                 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 109 }
 110
 111 static void __iomem *sched_clock_reg;
 112
 113 static u32 notrace mxc_read_sched_clock(void)
 114 {
 115         return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 116 }
 117
 118 static int __init mxc_clocksource_init(struct clk *timer_clk)
 119 {
 120         unsigned int c = clk_get_rate(timer_clk);
 121         void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
 122
 123         sched_clock_reg = reg;
 124
 125         setup_sched_clock(mxc_read_sched_clock, 32, c);
 126         return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
 127                         clocksource_mmio_readl_up);
 128 }
 129
 130 /* clock event */
 131
 132 static int mx1_2_set_next_event(unsigned long evt,
 133                               struct clock_event_device *unused)
 134 {
 135         unsigned long tcmp;
 136
 137         tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
 138
 139         __raw_writel(tcmp, timer_base + MX1_2_TCMP);
 140
 141         return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
 142                                 -ETIME : 0;
 143 }
 144
 145 static int v2_set_next_event(unsigned long evt,
 146                               struct clock_event_device *unused)
 147 {
 148         unsigned long tcmp;
 149
 150         tcmp = __raw_readl(timer_base + V2_TCN) + evt;
 151
 152         __raw_writel(tcmp, timer_base + V2_TCMP);
 153
 154         return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
 155                                 -ETIME : 0;
 156 }
 157
 158 #ifdef DEBUG
 159 static const char *clock_event_mode_label[] = {
 160         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 161         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 162         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 163         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
 164         [CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
 165 };
 166 #endif /* DEBUG */
 167
 168 static void mxc_set_mode(enum clock_event_mode mode,
 169                                 struct clock_event_device *evt)
 170 {
 171         unsigned long flags;
 172
 173         /*
 174          * The timer interrupt generation is disabled at least
 175          * for enough time to call mxc_set_next_event()
 176          */
 177         local_irq_save(flags);
 178
 179         /* Disable interrupt in GPT module */
 180         gpt_irq_disable();
 181
 182         if (mode != clockevent_mode) {
 183                 /* Set event time into far-far future */
 184                 if (timer_is_v2())
 185                         __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
 186                                         timer_base + V2_TCMP);
 187                 else
 188                         __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
 189                                         timer_base + MX1_2_TCMP);
 190
 191                 /* Clear pending interrupt */
 192                 gpt_irq_acknowledge();
 193         }
 194
 195 #ifdef DEBUG
 196         printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
 197                 clock_event_mode_label[clockevent_mode],
 198                 clock_event_mode_label[mode]);
 199 #endif /* DEBUG */
 200
 201         /* Remember timer mode */
 202         clockevent_mode = mode;
 203         local_irq_restore(flags);
 204
 205         switch (mode) {
 206         case CLOCK_EVT_MODE_PERIODIC:
 207                 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
 208                                 "supported for i.MX\n");
 209                 break;
 210         case CLOCK_EVT_MODE_ONESHOT:
 211         /*
 212          * Do not put overhead of interrupt enable/disable into
 213          * mxc_set_next_event(), the core has about 4 minutes
 214          * to call mxc_set_next_event() or shutdown clock after
 215          * mode switching
 216          */
 217                 local_irq_save(flags);
 218                 gpt_irq_enable();
 219                 local_irq_restore(flags);
 220                 break;
 221         case CLOCK_EVT_MODE_SHUTDOWN:
 222         case CLOCK_EVT_MODE_UNUSED:
 223         case CLOCK_EVT_MODE_RESUME:
 224                 /* Left event sources disabled, no more interrupts appear */
 225                 break;
 226         }
 227 }
 228
 229 /*
 230  * IRQ handler for the timer
 231  */
 232 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
 233 {
 234         struct clock_event_device *evt = &clockevent_mxc;
 235         uint32_t tstat;
 236
 237         if (timer_is_v2())
 238                 tstat = __raw_readl(timer_base + V2_TSTAT);
 239         else
 240                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
 241
 242         gpt_irq_acknowledge();
 243
 244         evt->event_handler(evt);
 245
 246         return IRQ_HANDLED;
 247 }
 248
 249 static struct irqaction mxc_timer_irq = {
 250         .name           = "i.MX Timer Tick",
 251         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 252         .handler        = mxc_timer_interrupt,
 253 };
 254
 255 static struct clock_event_device clockevent_mxc = {
 256         .name           = "mxc_timer1",
 257         .features       = CLOCK_EVT_FEAT_ONESHOT,
 258         .shift          = 32,
 259         .set_mode       = mxc_set_mode,
 260         .set_next_event = mx1_2_set_next_event,
 261         .rating         = 200,
 262 };
 263
 264 static int __init mxc_clockevent_init(struct clk *timer_clk)
 265 {
 266         unsigned int c = clk_get_rate(timer_clk);
 267
 268         if (timer_is_v2())
 269                 clockevent_mxc.set_next_event = v2_set_next_event;
 270
 271         clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
 272                                         clockevent_mxc.shift);
 273         clockevent_mxc.max_delta_ns =
 274                         clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
 275         clockevent_mxc.min_delta_ns =
 276                         clockevent_delta2ns(0xff, &clockevent_mxc);
 277
 278         clockevent_mxc.cpumask = cpumask_of(0);
 279
 280         clockevents_register_device(&clockevent_mxc);
 281
 282         return 0;
 283 }
 284
 285 void __init mxc_timer_init(void __iomem *base, int irq)
 286 {
 287         uint32_t tctl_val;
 288         struct clk *timer_clk;
 289         struct clk *timer_ipg_clk;
 290
 291         timer_clk = clk_get_sys("imx-gpt.0", "per");
 292         if (IS_ERR(timer_clk)) {
 293                 pr_err("i.MX timer: unable to get clk\n");
 294                 return;
 295         }
 296
 297         timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
 298         if (!IS_ERR(timer_ipg_clk))
 299                 clk_prepare_enable(timer_ipg_clk);
 300
 301         clk_prepare_enable(timer_clk);
 302
 303         timer_base = base;
 304
 305         /*
 306          * Initialise to a known state (all timers off, and timing reset)
 307          */
 308
 309         __raw_writel(0, timer_base + MXC_TCTL);
 310         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 311
 312         if (timer_is_v2())
 313                 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
 314         else
 315                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 316
 317         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 318
 319         /* init and register the timer to the framework */
 320         mxc_clocksource_init(timer_clk);
 321         mxc_clockevent_init(timer_clk);
 322
 323         /* Make irqs happen */
 324         setup_irq(irq, &mxc_timer_irq);
 325 }