2 * linux/arch/arm/plat-mxc/time.c
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
28 #include <linux/err.h>
30 #include <mach/hardware.h>
31 #include <asm/sched_clock.h>
32 #include <asm/mach/time.h>
33 #include <mach/common.h>
36 * There are 2 versions of the timer hardware on Freescale MXC hardware.
37 * Version 1: MX1/MXL, MX21, MX27.
38 * Version 2: MX25, MX31, MX35, MX37, MX51
41 /* defines common for all i.MX */
43 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
44 #define MXC_TPRER 0x04
47 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
48 #define MX1_2_TCTL_IRQEN (1 << 4)
49 #define MX1_2_TCTL_FRR (1 << 8)
50 #define MX1_2_TCMP 0x08
51 #define MX1_2_TCN 0x10
52 #define MX1_2_TSTAT 0x14
55 #define MX2_TSTAT_CAPT (1 << 1)
56 #define MX2_TSTAT_COMP (1 << 0)
58 /* MX31, MX35, MX25, MX5 */
59 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
60 #define V2_TCTL_CLK_IPG (1 << 6)
61 #define V2_TCTL_CLK_PER (2 << 6)
62 #define V2_TCTL_FRR (1 << 9)
65 #define V2_TSTAT_OF1 (1 << 0)
69 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
70 #define timer_is_v2() (!timer_is_v1())
72 static struct clock_event_device clockevent_mxc
;
73 static enum clock_event_mode clockevent_mode
= CLOCK_EVT_MODE_UNUSED
;
75 static void __iomem
*timer_base
;
77 static inline void gpt_irq_disable(void)
82 __raw_writel(0, timer_base
+ V2_IR
);
84 tmp
= __raw_readl(timer_base
+ MXC_TCTL
);
85 __raw_writel(tmp
& ~MX1_2_TCTL_IRQEN
, timer_base
+ MXC_TCTL
);
89 static inline void gpt_irq_enable(void)
92 __raw_writel(1<<0, timer_base
+ V2_IR
);
94 __raw_writel(__raw_readl(timer_base
+ MXC_TCTL
) | MX1_2_TCTL_IRQEN
,
95 timer_base
+ MXC_TCTL
);
99 static void gpt_irq_acknowledge(void)
103 __raw_writel(0, timer_base
+ MX1_2_TSTAT
);
105 __raw_writel(MX2_TSTAT_CAPT
| MX2_TSTAT_COMP
,
106 timer_base
+ MX1_2_TSTAT
);
107 } else if (timer_is_v2())
108 __raw_writel(V2_TSTAT_OF1
, timer_base
+ V2_TSTAT
);
111 static void __iomem
*sched_clock_reg
;
113 static u32 notrace
mxc_read_sched_clock(void)
115 return sched_clock_reg
? __raw_readl(sched_clock_reg
) : 0;
118 static int __init
mxc_clocksource_init(struct clk
*timer_clk
)
120 unsigned int c
= clk_get_rate(timer_clk
);
121 void __iomem
*reg
= timer_base
+ (timer_is_v2() ? V2_TCN
: MX1_2_TCN
);
123 sched_clock_reg
= reg
;
125 setup_sched_clock(mxc_read_sched_clock
, 32, c
);
126 return clocksource_mmio_init(reg
, "mxc_timer1", c
, 200, 32,
127 clocksource_mmio_readl_up
);
132 static int mx1_2_set_next_event(unsigned long evt
,
133 struct clock_event_device
*unused
)
137 tcmp
= __raw_readl(timer_base
+ MX1_2_TCN
) + evt
;
139 __raw_writel(tcmp
, timer_base
+ MX1_2_TCMP
);
141 return (int)(tcmp
- __raw_readl(timer_base
+ MX1_2_TCN
)) < 0 ?
145 static int v2_set_next_event(unsigned long evt
,
146 struct clock_event_device
*unused
)
150 tcmp
= __raw_readl(timer_base
+ V2_TCN
) + evt
;
152 __raw_writel(tcmp
, timer_base
+ V2_TCMP
);
154 return (int)(tcmp
- __raw_readl(timer_base
+ V2_TCN
)) < 0 ?
159 static const char *clock_event_mode_label
[] = {
160 [CLOCK_EVT_MODE_PERIODIC
] = "CLOCK_EVT_MODE_PERIODIC",
161 [CLOCK_EVT_MODE_ONESHOT
] = "CLOCK_EVT_MODE_ONESHOT",
162 [CLOCK_EVT_MODE_SHUTDOWN
] = "CLOCK_EVT_MODE_SHUTDOWN",
163 [CLOCK_EVT_MODE_UNUSED
] = "CLOCK_EVT_MODE_UNUSED"
167 static void mxc_set_mode(enum clock_event_mode mode
,
168 struct clock_event_device
*evt
)
173 * The timer interrupt generation is disabled at least
174 * for enough time to call mxc_set_next_event()
176 local_irq_save(flags
);
178 /* Disable interrupt in GPT module */
181 if (mode
!= clockevent_mode
) {
182 /* Set event time into far-far future */
184 __raw_writel(__raw_readl(timer_base
+ V2_TCN
) - 3,
185 timer_base
+ V2_TCMP
);
187 __raw_writel(__raw_readl(timer_base
+ MX1_2_TCN
) - 3,
188 timer_base
+ MX1_2_TCMP
);
190 /* Clear pending interrupt */
191 gpt_irq_acknowledge();
195 printk(KERN_INFO
"mxc_set_mode: changing mode from %s to %s\n",
196 clock_event_mode_label
[clockevent_mode
],
197 clock_event_mode_label
[mode
]);
200 /* Remember timer mode */
201 clockevent_mode
= mode
;
202 local_irq_restore(flags
);
205 case CLOCK_EVT_MODE_PERIODIC
:
206 printk(KERN_ERR
"mxc_set_mode: Periodic mode is not "
207 "supported for i.MX\n");
209 case CLOCK_EVT_MODE_ONESHOT
:
211 * Do not put overhead of interrupt enable/disable into
212 * mxc_set_next_event(), the core has about 4 minutes
213 * to call mxc_set_next_event() or shutdown clock after
216 local_irq_save(flags
);
218 local_irq_restore(flags
);
220 case CLOCK_EVT_MODE_SHUTDOWN
:
221 case CLOCK_EVT_MODE_UNUSED
:
222 case CLOCK_EVT_MODE_RESUME
:
223 /* Left event sources disabled, no more interrupts appear */
229 * IRQ handler for the timer
231 static irqreturn_t
mxc_timer_interrupt(int irq
, void *dev_id
)
233 struct clock_event_device
*evt
= &clockevent_mxc
;
237 tstat
= __raw_readl(timer_base
+ V2_TSTAT
);
239 tstat
= __raw_readl(timer_base
+ MX1_2_TSTAT
);
241 gpt_irq_acknowledge();
243 evt
->event_handler(evt
);
248 static struct irqaction mxc_timer_irq
= {
249 .name
= "i.MX Timer Tick",
250 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
251 .handler
= mxc_timer_interrupt
,
254 static struct clock_event_device clockevent_mxc
= {
255 .name
= "mxc_timer1",
256 .features
= CLOCK_EVT_FEAT_ONESHOT
,
258 .set_mode
= mxc_set_mode
,
259 .set_next_event
= mx1_2_set_next_event
,
263 static int __init
mxc_clockevent_init(struct clk
*timer_clk
)
265 unsigned int c
= clk_get_rate(timer_clk
);
268 clockevent_mxc
.set_next_event
= v2_set_next_event
;
270 clockevent_mxc
.mult
= div_sc(c
, NSEC_PER_SEC
,
271 clockevent_mxc
.shift
);
272 clockevent_mxc
.max_delta_ns
=
273 clockevent_delta2ns(0xfffffffe, &clockevent_mxc
);
274 clockevent_mxc
.min_delta_ns
=
275 clockevent_delta2ns(0xff, &clockevent_mxc
);
277 clockevent_mxc
.cpumask
= cpumask_of(0);
279 clockevents_register_device(&clockevent_mxc
);
284 void __init
mxc_timer_init(void __iomem
*base
, int irq
)
287 struct clk
*timer_clk
;
288 struct clk
*timer_ipg_clk
;
290 timer_clk
= clk_get_sys("imx-gpt.0", "per");
291 if (IS_ERR(timer_clk
)) {
292 pr_err("i.MX timer: unable to get clk\n");
296 timer_ipg_clk
= clk_get_sys("imx-gpt.0", "ipg");
297 if (!IS_ERR(timer_ipg_clk
))
298 clk_prepare_enable(timer_ipg_clk
);
300 clk_prepare_enable(timer_clk
);
305 * Initialise to a known state (all timers off, and timing reset)
308 __raw_writel(0, timer_base
+ MXC_TCTL
);
309 __raw_writel(0, timer_base
+ MXC_TPRER
); /* see datasheet note */
312 tctl_val
= V2_TCTL_CLK_PER
| V2_TCTL_FRR
| V2_TCTL_WAITEN
| MXC_TCTL_TEN
;
314 tctl_val
= MX1_2_TCTL_FRR
| MX1_2_TCTL_CLK_PCLK1
| MXC_TCTL_TEN
;
316 __raw_writel(tctl_val
, timer_base
+ MXC_TCTL
);
318 /* init and register the timer to the framework */
319 mxc_clocksource_init(timer_clk
);
320 mxc_clockevent_init(timer_clk
);
322 /* Make irqs happen */
323 setup_irq(irq
, &mxc_timer_irq
);