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[PATCH] fix missing includes
[deliverable/linux.git] / arch / arm / plat-omap / clock.c
1 /*
2 * linux/arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16 #include <linux/string.h>
17
18 #include <asm/io.h>
19 #include <asm/semaphore.h>
20 #include <asm/hardware/clock.h>
21 #include <asm/arch/board.h>
22 #include <asm/arch/usb.h>
23
24 #include "clock.h"
25 #include "sram.h"
26
27 static LIST_HEAD(clocks);
28 static DECLARE_MUTEX(clocks_sem);
29 static DEFINE_SPINLOCK(clockfw_lock);
30 static void propagate_rate(struct clk * clk);
31 /* UART clock function */
32 static int set_uart_rate(struct clk * clk, unsigned long rate);
33 /* External clock (MCLK & BCLK) functions */
34 static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
35 static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
36 static void init_ext_clk(struct clk * clk);
37 /* MPU virtual clock functions */
38 static int select_table_rate(struct clk * clk, unsigned long rate);
39 static long round_to_table_rate(struct clk * clk, unsigned long rate);
40 void clk_setdpll(__u16, __u16);
41
42 static struct mpu_rate rate_table[] = {
43 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
44 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
45 */
46 #if defined(CONFIG_OMAP_ARM_216MHZ)
47 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
48 #endif
49 #if defined(CONFIG_OMAP_ARM_195MHZ)
50 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
51 #endif
52 #if defined(CONFIG_OMAP_ARM_192MHZ)
53 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
54 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
55 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
56 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
57 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
58 #endif
59 #if defined(CONFIG_OMAP_ARM_182MHZ)
60 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
61 #endif
62 #if defined(CONFIG_OMAP_ARM_168MHZ)
63 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
64 #endif
65 #if defined(CONFIG_OMAP_ARM_150MHZ)
66 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
67 #endif
68 #if defined(CONFIG_OMAP_ARM_120MHZ)
69 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
70 #endif
71 #if defined(CONFIG_OMAP_ARM_96MHZ)
72 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
73 #endif
74 #if defined(CONFIG_OMAP_ARM_60MHZ)
75 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
76 #endif
77 #if defined(CONFIG_OMAP_ARM_30MHZ)
78 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
79 #endif
80 { 0, 0, 0, 0, 0 },
81 };
82
83
84 static void ckctl_recalc(struct clk * clk);
85 int __clk_enable(struct clk *clk);
86 void __clk_disable(struct clk *clk);
87 void __clk_unuse(struct clk *clk);
88 int __clk_use(struct clk *clk);
89
90
91 static void followparent_recalc(struct clk * clk)
92 {
93 clk->rate = clk->parent->rate;
94 }
95
96
97 static void watchdog_recalc(struct clk * clk)
98 {
99 clk->rate = clk->parent->rate / 14;
100 }
101
102 static void uart_recalc(struct clk * clk)
103 {
104 unsigned int val = omap_readl(clk->enable_reg);
105 if (val & clk->enable_bit)
106 clk->rate = 48000000;
107 else
108 clk->rate = 12000000;
109 }
110
111 static struct clk ck_ref = {
112 .name = "ck_ref",
113 .rate = 12000000,
114 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
115 ALWAYS_ENABLED,
116 };
117
118 static struct clk ck_dpll1 = {
119 .name = "ck_dpll1",
120 .parent = &ck_ref,
121 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
122 RATE_PROPAGATES | ALWAYS_ENABLED,
123 };
124
125 static struct clk ck_dpll1out = {
126 .name = "ck_dpll1out",
127 .parent = &ck_dpll1,
128 .flags = CLOCK_IN_OMAP16XX,
129 .enable_reg = ARM_IDLECT2,
130 .enable_bit = EN_CKOUT_ARM,
131 .recalc = &followparent_recalc,
132 };
133
134 static struct clk arm_ck = {
135 .name = "arm_ck",
136 .parent = &ck_dpll1,
137 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
138 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
139 .rate_offset = CKCTL_ARMDIV_OFFSET,
140 .recalc = &ckctl_recalc,
141 };
142
143 static struct clk armper_ck = {
144 .name = "armper_ck",
145 .parent = &ck_dpll1,
146 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
147 RATE_CKCTL,
148 .enable_reg = ARM_IDLECT2,
149 .enable_bit = EN_PERCK,
150 .rate_offset = CKCTL_PERDIV_OFFSET,
151 .recalc = &ckctl_recalc,
152 };
153
154 static struct clk arm_gpio_ck = {
155 .name = "arm_gpio_ck",
156 .parent = &ck_dpll1,
157 .flags = CLOCK_IN_OMAP1510,
158 .enable_reg = ARM_IDLECT2,
159 .enable_bit = EN_GPIOCK,
160 .recalc = &followparent_recalc,
161 };
162
163 static struct clk armxor_ck = {
164 .name = "armxor_ck",
165 .parent = &ck_ref,
166 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
167 .enable_reg = ARM_IDLECT2,
168 .enable_bit = EN_XORPCK,
169 .recalc = &followparent_recalc,
170 };
171
172 static struct clk armtim_ck = {
173 .name = "armtim_ck",
174 .parent = &ck_ref,
175 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
176 .enable_reg = ARM_IDLECT2,
177 .enable_bit = EN_TIMCK,
178 .recalc = &followparent_recalc,
179 };
180
181 static struct clk armwdt_ck = {
182 .name = "armwdt_ck",
183 .parent = &ck_ref,
184 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
185 .enable_reg = ARM_IDLECT2,
186 .enable_bit = EN_WDTCK,
187 .recalc = &watchdog_recalc,
188 };
189
190 static struct clk arminth_ck16xx = {
191 .name = "arminth_ck",
192 .parent = &arm_ck,
193 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
194 .recalc = &followparent_recalc,
195 /* Note: On 16xx the frequency can be divided by 2 by programming
196 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
197 *
198 * 1510 version is in TC clocks.
199 */
200 };
201
202 static struct clk dsp_ck = {
203 .name = "dsp_ck",
204 .parent = &ck_dpll1,
205 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
206 RATE_CKCTL,
207 .enable_reg = ARM_CKCTL,
208 .enable_bit = EN_DSPCK,
209 .rate_offset = CKCTL_DSPDIV_OFFSET,
210 .recalc = &ckctl_recalc,
211 };
212
213 static struct clk dspmmu_ck = {
214 .name = "dspmmu_ck",
215 .parent = &ck_dpll1,
216 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
217 RATE_CKCTL | ALWAYS_ENABLED,
218 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
219 .recalc = &ckctl_recalc,
220 };
221
222 static struct clk dspper_ck = {
223 .name = "dspper_ck",
224 .parent = &ck_dpll1,
225 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
226 RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
227 .enable_reg = DSP_IDLECT2,
228 .enable_bit = EN_PERCK,
229 .rate_offset = CKCTL_PERDIV_OFFSET,
230 .recalc = &followparent_recalc,
231 //.recalc = &ckctl_recalc,
232 };
233
234 static struct clk dspxor_ck = {
235 .name = "dspxor_ck",
236 .parent = &ck_ref,
237 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
238 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
239 .enable_reg = DSP_IDLECT2,
240 .enable_bit = EN_XORPCK,
241 .recalc = &followparent_recalc,
242 };
243
244 static struct clk dsptim_ck = {
245 .name = "dsptim_ck",
246 .parent = &ck_ref,
247 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
248 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_DSPTIMCK,
251 .recalc = &followparent_recalc,
252 };
253
254 static struct clk tc_ck = {
255 .name = "tc_ck",
256 .parent = &ck_dpll1,
257 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
258 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .rate_offset = CKCTL_TCDIV_OFFSET,
260 .recalc = &ckctl_recalc,
261 };
262
263 static struct clk arminth_ck1510 = {
264 .name = "arminth_ck",
265 .parent = &tc_ck,
266 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
267 .recalc = &followparent_recalc,
268 /* Note: On 1510 the frequency follows TC_CK
269 *
270 * 16xx version is in MPU clocks.
271 */
272 };
273
274 static struct clk tipb_ck = {
275 .name = "tibp_ck",
276 .parent = &tc_ck,
277 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
278 .recalc = &followparent_recalc,
279 };
280
281 static struct clk l3_ocpi_ck = {
282 .name = "l3_ocpi_ck",
283 .parent = &tc_ck,
284 .flags = CLOCK_IN_OMAP16XX,
285 .enable_reg = ARM_IDLECT3,
286 .enable_bit = EN_OCPI_CK,
287 .recalc = &followparent_recalc,
288 };
289
290 static struct clk tc1_ck = {
291 .name = "tc1_ck",
292 .parent = &tc_ck,
293 .flags = CLOCK_IN_OMAP16XX,
294 .enable_reg = ARM_IDLECT3,
295 .enable_bit = EN_TC1_CK,
296 .recalc = &followparent_recalc,
297 };
298
299 static struct clk tc2_ck = {
300 .name = "tc2_ck",
301 .parent = &tc_ck,
302 .flags = CLOCK_IN_OMAP16XX,
303 .enable_reg = ARM_IDLECT3,
304 .enable_bit = EN_TC2_CK,
305 .recalc = &followparent_recalc,
306 };
307
308 static struct clk dma_ck = {
309 .name = "dma_ck",
310 .parent = &tc_ck,
311 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
312 ALWAYS_ENABLED,
313 .recalc = &followparent_recalc,
314 };
315
316 static struct clk dma_lcdfree_ck = {
317 .name = "dma_lcdfree_ck",
318 .parent = &tc_ck,
319 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
320 .recalc = &followparent_recalc,
321 };
322
323 static struct clk api_ck = {
324 .name = "api_ck",
325 .parent = &tc_ck,
326 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
327 .enable_reg = ARM_IDLECT2,
328 .enable_bit = EN_APICK,
329 .recalc = &followparent_recalc,
330 };
331
332 static struct clk lb_ck = {
333 .name = "lb_ck",
334 .parent = &tc_ck,
335 .flags = CLOCK_IN_OMAP1510,
336 .enable_reg = ARM_IDLECT2,
337 .enable_bit = EN_LBCK,
338 .recalc = &followparent_recalc,
339 };
340
341 static struct clk rhea1_ck = {
342 .name = "rhea1_ck",
343 .parent = &tc_ck,
344 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
345 .recalc = &followparent_recalc,
346 };
347
348 static struct clk rhea2_ck = {
349 .name = "rhea2_ck",
350 .parent = &tc_ck,
351 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
352 .recalc = &followparent_recalc,
353 };
354
355 static struct clk lcd_ck = {
356 .name = "lcd_ck",
357 .parent = &ck_dpll1,
358 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
359 RATE_CKCTL,
360 .enable_reg = ARM_IDLECT2,
361 .enable_bit = EN_LCDCK,
362 .rate_offset = CKCTL_LCDDIV_OFFSET,
363 .recalc = &ckctl_recalc,
364 };
365
366 static struct clk uart1_1510 = {
367 .name = "uart1_ck",
368 /* Direct from ULPD, no parent */
369 .rate = 12000000,
370 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
371 .enable_reg = MOD_CONF_CTRL_0,
372 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
373 .set_rate = &set_uart_rate,
374 .recalc = &uart_recalc,
375 };
376
377 static struct clk uart1_16xx = {
378 .name = "uart1_ck",
379 /* Direct from ULPD, no parent */
380 .rate = 48000000,
381 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
382 .enable_reg = MOD_CONF_CTRL_0,
383 .enable_bit = 29,
384 };
385
386 static struct clk uart2_ck = {
387 .name = "uart2_ck",
388 /* Direct from ULPD, no parent */
389 .rate = 12000000,
390 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
391 ALWAYS_ENABLED,
392 .enable_reg = MOD_CONF_CTRL_0,
393 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
394 .set_rate = &set_uart_rate,
395 .recalc = &uart_recalc,
396 };
397
398 static struct clk uart3_1510 = {
399 .name = "uart3_ck",
400 /* Direct from ULPD, no parent */
401 .rate = 12000000,
402 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
403 .enable_reg = MOD_CONF_CTRL_0,
404 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
405 .set_rate = &set_uart_rate,
406 .recalc = &uart_recalc,
407 };
408
409 static struct clk uart3_16xx = {
410 .name = "uart3_ck",
411 /* Direct from ULPD, no parent */
412 .rate = 48000000,
413 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
414 .enable_reg = MOD_CONF_CTRL_0,
415 .enable_bit = 31,
416 };
417
418 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
419 .name = "usb_clko",
420 /* Direct from ULPD, no parent */
421 .rate = 6000000,
422 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
423 RATE_FIXED | ENABLE_REG_32BIT,
424 .enable_reg = ULPD_CLOCK_CTRL,
425 .enable_bit = USB_MCLK_EN_BIT,
426 };
427
428 static struct clk usb_hhc_ck1510 = {
429 .name = "usb_hhc_ck",
430 /* Direct from ULPD, no parent */
431 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
432 .flags = CLOCK_IN_OMAP1510 |
433 RATE_FIXED | ENABLE_REG_32BIT,
434 .enable_reg = MOD_CONF_CTRL_0,
435 .enable_bit = USB_HOST_HHC_UHOST_EN,
436 };
437
438 static struct clk usb_hhc_ck16xx = {
439 .name = "usb_hhc_ck",
440 /* Direct from ULPD, no parent */
441 .rate = 48000000,
442 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
443 .flags = CLOCK_IN_OMAP16XX |
444 RATE_FIXED | ENABLE_REG_32BIT,
445 .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
446 .enable_bit = 8 /* UHOST_EN */,
447 };
448
449 static struct clk usb_dc_ck = {
450 .name = "usb_dc_ck",
451 /* Direct from ULPD, no parent */
452 .rate = 48000000,
453 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
454 .enable_reg = SOFT_REQ_REG,
455 .enable_bit = 4,
456 };
457
458 static struct clk mclk_1510 = {
459 .name = "mclk",
460 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
461 .rate = 12000000,
462 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
463 };
464
465 static struct clk mclk_16xx = {
466 .name = "mclk",
467 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
468 .flags = CLOCK_IN_OMAP16XX,
469 .enable_reg = COM_CLK_DIV_CTRL_SEL,
470 .enable_bit = COM_ULPD_PLL_CLK_REQ,
471 .set_rate = &set_ext_clk_rate,
472 .round_rate = &round_ext_clk_rate,
473 .init = &init_ext_clk,
474 };
475
476 static struct clk bclk_1510 = {
477 .name = "bclk",
478 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
479 .rate = 12000000,
480 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
481 };
482
483 static struct clk bclk_16xx = {
484 .name = "bclk",
485 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
486 .flags = CLOCK_IN_OMAP16XX,
487 .enable_reg = SWD_CLK_DIV_CTRL_SEL,
488 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
489 .set_rate = &set_ext_clk_rate,
490 .round_rate = &round_ext_clk_rate,
491 .init = &init_ext_clk,
492 };
493
494 static struct clk mmc1_ck = {
495 .name = "mmc1_ck",
496 /* Functional clock is direct from ULPD, interface clock is ARMPER */
497 .parent = &armper_ck,
498 .rate = 48000000,
499 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
500 RATE_FIXED | ENABLE_REG_32BIT,
501 .enable_reg = MOD_CONF_CTRL_0,
502 .enable_bit = 23,
503 };
504
505 static struct clk mmc2_ck = {
506 .name = "mmc2_ck",
507 /* Functional clock is direct from ULPD, interface clock is ARMPER */
508 .parent = &armper_ck,
509 .rate = 48000000,
510 .flags = CLOCK_IN_OMAP16XX |
511 RATE_FIXED | ENABLE_REG_32BIT,
512 .enable_reg = MOD_CONF_CTRL_0,
513 .enable_bit = 20,
514 };
515
516 static struct clk virtual_ck_mpu = {
517 .name = "mpu",
518 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
519 VIRTUAL_CLOCK | ALWAYS_ENABLED,
520 .parent = &arm_ck, /* Is smarter alias for */
521 .recalc = &followparent_recalc,
522 .set_rate = &select_table_rate,
523 .round_rate = &round_to_table_rate,
524 };
525
526
527 static struct clk * onchip_clks[] = {
528 /* non-ULPD clocks */
529 &ck_ref,
530 &ck_dpll1,
531 /* CK_GEN1 clocks */
532 &ck_dpll1out,
533 &arm_ck,
534 &armper_ck,
535 &arm_gpio_ck,
536 &armxor_ck,
537 &armtim_ck,
538 &armwdt_ck,
539 &arminth_ck1510, &arminth_ck16xx,
540 /* CK_GEN2 clocks */
541 &dsp_ck,
542 &dspmmu_ck,
543 &dspper_ck,
544 &dspxor_ck,
545 &dsptim_ck,
546 /* CK_GEN3 clocks */
547 &tc_ck,
548 &tipb_ck,
549 &l3_ocpi_ck,
550 &tc1_ck,
551 &tc2_ck,
552 &dma_ck,
553 &dma_lcdfree_ck,
554 &api_ck,
555 &lb_ck,
556 &rhea1_ck,
557 &rhea2_ck,
558 &lcd_ck,
559 /* ULPD clocks */
560 &uart1_1510,
561 &uart1_16xx,
562 &uart2_ck,
563 &uart3_1510,
564 &uart3_16xx,
565 &usb_clko,
566 &usb_hhc_ck1510, &usb_hhc_ck16xx,
567 &usb_dc_ck,
568 &mclk_1510, &mclk_16xx,
569 &bclk_1510, &bclk_16xx,
570 &mmc1_ck,
571 &mmc2_ck,
572 /* Virtual clocks */
573 &virtual_ck_mpu,
574 };
575
576 struct clk *clk_get(struct device *dev, const char *id)
577 {
578 struct clk *p, *clk = ERR_PTR(-ENOENT);
579
580 down(&clocks_sem);
581 list_for_each_entry(p, &clocks, node) {
582 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
583 clk = p;
584 break;
585 }
586 }
587 up(&clocks_sem);
588
589 return clk;
590 }
591 EXPORT_SYMBOL(clk_get);
592
593
594 void clk_put(struct clk *clk)
595 {
596 if (clk && !IS_ERR(clk))
597 module_put(clk->owner);
598 }
599 EXPORT_SYMBOL(clk_put);
600
601
602 int __clk_enable(struct clk *clk)
603 {
604 __u16 regval16;
605 __u32 regval32;
606
607 if (clk->flags & ALWAYS_ENABLED)
608 return 0;
609
610 if (unlikely(clk->enable_reg == 0)) {
611 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
612 clk->name);
613 return 0;
614 }
615
616 if (clk->flags & DSP_DOMAIN_CLOCK) {
617 __clk_use(&api_ck);
618 }
619
620 if (clk->flags & ENABLE_REG_32BIT) {
621 if (clk->flags & VIRTUAL_IO_ADDRESS) {
622 regval32 = __raw_readl(clk->enable_reg);
623 regval32 |= (1 << clk->enable_bit);
624 __raw_writel(regval32, clk->enable_reg);
625 } else {
626 regval32 = omap_readl(clk->enable_reg);
627 regval32 |= (1 << clk->enable_bit);
628 omap_writel(regval32, clk->enable_reg);
629 }
630 } else {
631 if (clk->flags & VIRTUAL_IO_ADDRESS) {
632 regval16 = __raw_readw(clk->enable_reg);
633 regval16 |= (1 << clk->enable_bit);
634 __raw_writew(regval16, clk->enable_reg);
635 } else {
636 regval16 = omap_readw(clk->enable_reg);
637 regval16 |= (1 << clk->enable_bit);
638 omap_writew(regval16, clk->enable_reg);
639 }
640 }
641
642 if (clk->flags & DSP_DOMAIN_CLOCK) {
643 __clk_unuse(&api_ck);
644 }
645
646 return 0;
647 }
648
649
650 void __clk_disable(struct clk *clk)
651 {
652 __u16 regval16;
653 __u32 regval32;
654
655 if (clk->enable_reg == 0)
656 return;
657
658 if (clk->flags & DSP_DOMAIN_CLOCK) {
659 __clk_use(&api_ck);
660 }
661
662 if (clk->flags & ENABLE_REG_32BIT) {
663 if (clk->flags & VIRTUAL_IO_ADDRESS) {
664 regval32 = __raw_readl(clk->enable_reg);
665 regval32 &= ~(1 << clk->enable_bit);
666 __raw_writel(regval32, clk->enable_reg);
667 } else {
668 regval32 = omap_readl(clk->enable_reg);
669 regval32 &= ~(1 << clk->enable_bit);
670 omap_writel(regval32, clk->enable_reg);
671 }
672 } else {
673 if (clk->flags & VIRTUAL_IO_ADDRESS) {
674 regval16 = __raw_readw(clk->enable_reg);
675 regval16 &= ~(1 << clk->enable_bit);
676 __raw_writew(regval16, clk->enable_reg);
677 } else {
678 regval16 = omap_readw(clk->enable_reg);
679 regval16 &= ~(1 << clk->enable_bit);
680 omap_writew(regval16, clk->enable_reg);
681 }
682 }
683
684 if (clk->flags & DSP_DOMAIN_CLOCK) {
685 __clk_unuse(&api_ck);
686 }
687 }
688
689
690 void __clk_unuse(struct clk *clk)
691 {
692 if (clk->usecount > 0 && !(--clk->usecount)) {
693 __clk_disable(clk);
694 if (likely(clk->parent))
695 __clk_unuse(clk->parent);
696 }
697 }
698
699
700 int __clk_use(struct clk *clk)
701 {
702 int ret = 0;
703 if (clk->usecount++ == 0) {
704 if (likely(clk->parent))
705 ret = __clk_use(clk->parent);
706
707 if (unlikely(ret != 0)) {
708 clk->usecount--;
709 return ret;
710 }
711
712 ret = __clk_enable(clk);
713
714 if (unlikely(ret != 0) && clk->parent) {
715 __clk_unuse(clk->parent);
716 clk->usecount--;
717 }
718 }
719
720 return ret;
721 }
722
723
724 int clk_enable(struct clk *clk)
725 {
726 unsigned long flags;
727 int ret;
728
729 spin_lock_irqsave(&clockfw_lock, flags);
730 ret = __clk_enable(clk);
731 spin_unlock_irqrestore(&clockfw_lock, flags);
732 return ret;
733 }
734 EXPORT_SYMBOL(clk_enable);
735
736
737 void clk_disable(struct clk *clk)
738 {
739 unsigned long flags;
740
741 spin_lock_irqsave(&clockfw_lock, flags);
742 __clk_disable(clk);
743 spin_unlock_irqrestore(&clockfw_lock, flags);
744 }
745 EXPORT_SYMBOL(clk_disable);
746
747
748 int clk_use(struct clk *clk)
749 {
750 unsigned long flags;
751 int ret = 0;
752
753 spin_lock_irqsave(&clockfw_lock, flags);
754 ret = __clk_use(clk);
755 spin_unlock_irqrestore(&clockfw_lock, flags);
756 return ret;
757 }
758 EXPORT_SYMBOL(clk_use);
759
760
761 void clk_unuse(struct clk *clk)
762 {
763 unsigned long flags;
764
765 spin_lock_irqsave(&clockfw_lock, flags);
766 __clk_unuse(clk);
767 spin_unlock_irqrestore(&clockfw_lock, flags);
768 }
769 EXPORT_SYMBOL(clk_unuse);
770
771
772 int clk_get_usecount(struct clk *clk)
773 {
774 return clk->usecount;
775 }
776 EXPORT_SYMBOL(clk_get_usecount);
777
778
779 unsigned long clk_get_rate(struct clk *clk)
780 {
781 return clk->rate;
782 }
783 EXPORT_SYMBOL(clk_get_rate);
784
785
786 static __u16 verify_ckctl_value(__u16 newval)
787 {
788 /* This function checks for following limitations set
789 * by the hardware (all conditions must be true):
790 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
791 * ARM_CK >= TC_CK
792 * DSP_CK >= TC_CK
793 * DSPMMU_CK >= TC_CK
794 *
795 * In addition following rules are enforced:
796 * LCD_CK <= TC_CK
797 * ARMPER_CK <= TC_CK
798 *
799 * However, maximum frequencies are not checked for!
800 */
801 __u8 per_exp;
802 __u8 lcd_exp;
803 __u8 arm_exp;
804 __u8 dsp_exp;
805 __u8 tc_exp;
806 __u8 dspmmu_exp;
807
808 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
809 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
810 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
811 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
812 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
813 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
814
815 if (dspmmu_exp < dsp_exp)
816 dspmmu_exp = dsp_exp;
817 if (dspmmu_exp > dsp_exp+1)
818 dspmmu_exp = dsp_exp+1;
819 if (tc_exp < arm_exp)
820 tc_exp = arm_exp;
821 if (tc_exp < dspmmu_exp)
822 tc_exp = dspmmu_exp;
823 if (tc_exp > lcd_exp)
824 lcd_exp = tc_exp;
825 if (tc_exp > per_exp)
826 per_exp = tc_exp;
827
828 newval &= 0xf000;
829 newval |= per_exp << CKCTL_PERDIV_OFFSET;
830 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
831 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
832 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
833 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
834 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
835
836 return newval;
837 }
838
839
840 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
841 {
842 /* Note: If target frequency is too low, this function will return 4,
843 * which is invalid value. Caller must check for this value and act
844 * accordingly.
845 *
846 * Note: This function does not check for following limitations set
847 * by the hardware (all conditions must be true):
848 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
849 * ARM_CK >= TC_CK
850 * DSP_CK >= TC_CK
851 * DSPMMU_CK >= TC_CK
852 */
853 unsigned long realrate;
854 struct clk * parent;
855 unsigned dsor_exp;
856
857 if (unlikely(!(clk->flags & RATE_CKCTL)))
858 return -EINVAL;
859
860 parent = clk->parent;
861 if (unlikely(parent == 0))
862 return -EIO;
863
864 realrate = parent->rate;
865 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
866 if (realrate <= rate)
867 break;
868
869 realrate /= 2;
870 }
871
872 return dsor_exp;
873 }
874
875
876 static void ckctl_recalc(struct clk * clk)
877 {
878 int dsor;
879
880 /* Calculate divisor encoded as 2-bit exponent */
881 if (clk->flags & DSP_DOMAIN_CLOCK) {
882 /* The clock control bits are in DSP domain,
883 * so api_ck is needed for access.
884 * Note that DSP_CKCTL virt addr = phys addr, so
885 * we must use __raw_readw() instead of omap_readw().
886 */
887 __clk_use(&api_ck);
888 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
889 __clk_unuse(&api_ck);
890 } else {
891 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
892 }
893 if (unlikely(clk->rate == clk->parent->rate / dsor))
894 return; /* No change, quick exit */
895 clk->rate = clk->parent->rate / dsor;
896
897 if (unlikely(clk->flags & RATE_PROPAGATES))
898 propagate_rate(clk);
899 }
900
901
902 long clk_round_rate(struct clk *clk, unsigned long rate)
903 {
904 int dsor_exp;
905
906 if (clk->flags & RATE_FIXED)
907 return clk->rate;
908
909 if (clk->flags & RATE_CKCTL) {
910 dsor_exp = calc_dsor_exp(clk, rate);
911 if (dsor_exp < 0)
912 return dsor_exp;
913 if (dsor_exp > 3)
914 dsor_exp = 3;
915 return clk->parent->rate / (1 << dsor_exp);
916 }
917
918 if(clk->round_rate != 0)
919 return clk->round_rate(clk, rate);
920
921 return clk->rate;
922 }
923 EXPORT_SYMBOL(clk_round_rate);
924
925
926 static void propagate_rate(struct clk * clk)
927 {
928 struct clk ** clkp;
929
930 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
931 if (likely((*clkp)->parent != clk)) continue;
932 if (likely((*clkp)->recalc))
933 (*clkp)->recalc(*clkp);
934 }
935 }
936
937
938 static int select_table_rate(struct clk * clk, unsigned long rate)
939 {
940 /* Find the highest supported frequency <= rate and switch to it */
941 struct mpu_rate * ptr;
942
943 if (clk != &virtual_ck_mpu)
944 return -EINVAL;
945
946 for (ptr = rate_table; ptr->rate; ptr++) {
947 if (ptr->xtal != ck_ref.rate)
948 continue;
949
950 /* DPLL1 cannot be reprogrammed without risking system crash */
951 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
952 continue;
953
954 /* Can check only after xtal frequency check */
955 if (ptr->rate <= rate)
956 break;
957 }
958
959 if (!ptr->rate)
960 return -EINVAL;
961
962 /*
963 * In most cases we should not need to reprogram DPLL.
964 * Reprogramming the DPLL is tricky, it must be done from SRAM.
965 */
966 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
967
968 ck_dpll1.rate = ptr->pll_rate;
969 propagate_rate(&ck_dpll1);
970 return 0;
971 }
972
973
974 static long round_to_table_rate(struct clk * clk, unsigned long rate)
975 {
976 /* Find the highest supported frequency <= rate */
977 struct mpu_rate * ptr;
978 long highest_rate;
979
980 if (clk != &virtual_ck_mpu)
981 return -EINVAL;
982
983 highest_rate = -EINVAL;
984
985 for (ptr = rate_table; ptr->rate; ptr++) {
986 if (ptr->xtal != ck_ref.rate)
987 continue;
988
989 highest_rate = ptr->rate;
990
991 /* Can check only after xtal frequency check */
992 if (ptr->rate <= rate)
993 break;
994 }
995
996 return highest_rate;
997 }
998
999
1000 int clk_set_rate(struct clk *clk, unsigned long rate)
1001 {
1002 int ret = -EINVAL;
1003 int dsor_exp;
1004 __u16 regval;
1005 unsigned long flags;
1006
1007 if (clk->flags & RATE_CKCTL) {
1008 dsor_exp = calc_dsor_exp(clk, rate);
1009 if (dsor_exp > 3)
1010 dsor_exp = -EINVAL;
1011 if (dsor_exp < 0)
1012 return dsor_exp;
1013
1014 spin_lock_irqsave(&clockfw_lock, flags);
1015 regval = omap_readw(ARM_CKCTL);
1016 regval &= ~(3 << clk->rate_offset);
1017 regval |= dsor_exp << clk->rate_offset;
1018 regval = verify_ckctl_value(regval);
1019 omap_writew(regval, ARM_CKCTL);
1020 clk->rate = clk->parent->rate / (1 << dsor_exp);
1021 spin_unlock_irqrestore(&clockfw_lock, flags);
1022 ret = 0;
1023 } else if(clk->set_rate != 0) {
1024 spin_lock_irqsave(&clockfw_lock, flags);
1025 ret = clk->set_rate(clk, rate);
1026 spin_unlock_irqrestore(&clockfw_lock, flags);
1027 }
1028
1029 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
1030 propagate_rate(clk);
1031
1032 return ret;
1033 }
1034 EXPORT_SYMBOL(clk_set_rate);
1035
1036
1037 static unsigned calc_ext_dsor(unsigned long rate)
1038 {
1039 unsigned dsor;
1040
1041 /* MCLK and BCLK divisor selection is not linear:
1042 * freq = 96MHz / dsor
1043 *
1044 * RATIO_SEL range: dsor <-> RATIO_SEL
1045 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
1046 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
1047 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
1048 * can not be used.
1049 */
1050 for (dsor = 2; dsor < 96; ++dsor) {
1051 if ((dsor & 1) && dsor > 8)
1052 continue;
1053 if (rate >= 96000000 / dsor)
1054 break;
1055 }
1056 return dsor;
1057 }
1058
1059 /* Only needed on 1510 */
1060 static int set_uart_rate(struct clk * clk, unsigned long rate)
1061 {
1062 unsigned int val;
1063
1064 val = omap_readl(clk->enable_reg);
1065 if (rate == 12000000)
1066 val &= ~(1 << clk->enable_bit);
1067 else if (rate == 48000000)
1068 val |= (1 << clk->enable_bit);
1069 else
1070 return -EINVAL;
1071 omap_writel(val, clk->enable_reg);
1072 clk->rate = rate;
1073
1074 return 0;
1075 }
1076
1077 static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
1078 {
1079 unsigned dsor;
1080 __u16 ratio_bits;
1081
1082 dsor = calc_ext_dsor(rate);
1083 clk->rate = 96000000 / dsor;
1084 if (dsor > 8)
1085 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
1086 else
1087 ratio_bits = (dsor - 2) << 2;
1088
1089 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
1090 omap_writew(ratio_bits, clk->enable_reg);
1091
1092 return 0;
1093 }
1094
1095
1096 static long round_ext_clk_rate(struct clk * clk, unsigned long rate)
1097 {
1098 return 96000000 / calc_ext_dsor(rate);
1099 }
1100
1101
1102 static void init_ext_clk(struct clk * clk)
1103 {
1104 unsigned dsor;
1105 __u16 ratio_bits;
1106
1107 /* Determine current rate and ensure clock is based on 96MHz APLL */
1108 ratio_bits = omap_readw(clk->enable_reg) & ~1;
1109 omap_writew(ratio_bits, clk->enable_reg);
1110
1111 ratio_bits = (ratio_bits & 0xfc) >> 2;
1112 if (ratio_bits > 6)
1113 dsor = (ratio_bits - 6) * 2 + 8;
1114 else
1115 dsor = ratio_bits + 2;
1116
1117 clk-> rate = 96000000 / dsor;
1118 }
1119
1120
1121 int clk_register(struct clk *clk)
1122 {
1123 down(&clocks_sem);
1124 list_add(&clk->node, &clocks);
1125 if (clk->init)
1126 clk->init(clk);
1127 up(&clocks_sem);
1128 return 0;
1129 }
1130 EXPORT_SYMBOL(clk_register);
1131
1132 void clk_unregister(struct clk *clk)
1133 {
1134 down(&clocks_sem);
1135 list_del(&clk->node);
1136 up(&clocks_sem);
1137 }
1138 EXPORT_SYMBOL(clk_unregister);
1139
1140 #ifdef CONFIG_OMAP_RESET_CLOCKS
1141 /*
1142 * Resets some clocks that may be left on from bootloader,
1143 * but leaves serial clocks on. See also omap_late_clk_reset().
1144 */
1145 static inline void omap_early_clk_reset(void)
1146 {
1147 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
1148 }
1149 #else
1150 #define omap_early_clk_reset() {}
1151 #endif
1152
1153 int __init clk_init(void)
1154 {
1155 struct clk ** clkp;
1156 const struct omap_clock_config *info;
1157 int crystal_type = 0; /* Default 12 MHz */
1158
1159 omap_early_clk_reset();
1160
1161 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
1162 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1163 clk_register(*clkp);
1164 continue;
1165 }
1166
1167 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1168 clk_register(*clkp);
1169 continue;
1170 }
1171
1172 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1173 clk_register(*clkp);
1174 continue;
1175 }
1176 }
1177
1178 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1179 if (info != NULL) {
1180 if (!cpu_is_omap1510())
1181 crystal_type = info->system_clock_type;
1182 }
1183
1184 #if defined(CONFIG_ARCH_OMAP730)
1185 ck_ref.rate = 13000000;
1186 #elif defined(CONFIG_ARCH_OMAP16XX)
1187 if (crystal_type == 2)
1188 ck_ref.rate = 19200000;
1189 #endif
1190
1191 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1192 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1193 omap_readw(ARM_CKCTL));
1194
1195 /* We want to be in syncronous scalable mode */
1196 omap_writew(0x1000, ARM_SYSST);
1197
1198 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1199 /* Use values set by bootloader. Determine PLL rate and recalculate
1200 * dependent clocks as if kernel had changed PLL or divisors.
1201 */
1202 {
1203 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1204
1205 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1206 if (pll_ctl_val & 0x10) {
1207 /* PLL enabled, apply multiplier and divisor */
1208 if (pll_ctl_val & 0xf80)
1209 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1210 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1211 } else {
1212 /* PLL disabled, apply bypass divisor */
1213 switch (pll_ctl_val & 0xc) {
1214 case 0:
1215 break;
1216 case 0x4:
1217 ck_dpll1.rate /= 2;
1218 break;
1219 default:
1220 ck_dpll1.rate /= 4;
1221 break;
1222 }
1223 }
1224 }
1225 propagate_rate(&ck_dpll1);
1226 #else
1227 /* Find the highest supported frequency and enable it */
1228 if (select_table_rate(&virtual_ck_mpu, ~0)) {
1229 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1230 /* Guess sane values (60MHz) */
1231 omap_writew(0x2290, DPLL_CTL);
1232 omap_writew(0x1005, ARM_CKCTL);
1233 ck_dpll1.rate = 60000000;
1234 propagate_rate(&ck_dpll1);
1235 }
1236 #endif
1237 /* Cache rates for clocks connected to ck_ref (not dpll1) */
1238 propagate_rate(&ck_ref);
1239 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
1240 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
1241 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1242 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
1243 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
1244
1245 #ifdef CONFIG_MACH_OMAP_PERSEUS2
1246 /* Select slicer output as OMAP input clock */
1247 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1248 #endif
1249
1250 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1251 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1252
1253 /* Put DSP/MPUI into reset until needed */
1254 omap_writew(0, ARM_RSTCT1);
1255 omap_writew(1, ARM_RSTCT2);
1256 omap_writew(0x400, ARM_IDLECT1);
1257
1258 /*
1259 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1260 * of the ARM_IDLECT2 register must be set to zero. The power-on
1261 * default value of this bit is one.
1262 */
1263 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
1264
1265 /*
1266 * Only enable those clocks we will need, let the drivers
1267 * enable other clocks as necessary
1268 */
1269 clk_use(&armper_ck);
1270 clk_use(&armxor_ck);
1271 clk_use(&armtim_ck);
1272
1273 if (cpu_is_omap1510())
1274 clk_enable(&arm_gpio_ck);
1275
1276 return 0;
1277 }
1278
1279
1280 #ifdef CONFIG_OMAP_RESET_CLOCKS
1281
1282 static int __init omap_late_clk_reset(void)
1283 {
1284 /* Turn off all unused clocks */
1285 struct clk *p;
1286 __u32 regval32;
1287
1288 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
1289 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
1290 omap_writew(regval32, SOFT_REQ_REG);
1291 omap_writew(0, SOFT_REQ_REG2);
1292
1293 list_for_each_entry(p, &clocks, node) {
1294 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1295 p->enable_reg == 0)
1296 continue;
1297
1298 /* Assume no DSP clocks have been activated by bootloader */
1299 if (p->flags & DSP_DOMAIN_CLOCK)
1300 continue;
1301
1302 /* Is the clock already disabled? */
1303 if (p->flags & ENABLE_REG_32BIT) {
1304 if (p->flags & VIRTUAL_IO_ADDRESS)
1305 regval32 = __raw_readl(p->enable_reg);
1306 else
1307 regval32 = omap_readl(p->enable_reg);
1308 } else {
1309 if (p->flags & VIRTUAL_IO_ADDRESS)
1310 regval32 = __raw_readw(p->enable_reg);
1311 else
1312 regval32 = omap_readw(p->enable_reg);
1313 }
1314
1315 if ((regval32 & (1 << p->enable_bit)) == 0)
1316 continue;
1317
1318 /* FIXME: This clock seems to be necessary but no-one
1319 * has asked for its activation. */
1320 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
1321 || p == &ck_dpll1out // FIX: SoSSI, SSR
1322 || p == &arm_gpio_ck // FIX: GPIO code for 1510
1323 ) {
1324 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1325 p->name);
1326 continue;
1327 }
1328
1329 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1330 __clk_disable(p);
1331 printk(" done\n");
1332 }
1333
1334 return 0;
1335 }
1336
1337 late_initcall(omap_late_clk_reset);
1338
1339 #endif
Linux kernel - Deliverables
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