2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <plat-omap/dma-omap.h>
41 #include "../mach-omap1/soc.h"
42 #include "../mach-omap2/soc.h"
45 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
46 * channels that an instance of the SDMA IP block can support. Used
47 * to size arrays. (The actual maximum on a particular SoC may be less
48 * than this -- for example, OMAP1 SDMA instances only support 17 logical
51 #define MAX_LOGICAL_DMA_CH_COUNT 32
55 #ifndef CONFIG_ARCH_OMAP1
56 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
57 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
60 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
63 #define OMAP_DMA_ACTIVE 0x01
64 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
66 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
68 static struct omap_system_dma_plat_info
*p
;
69 static struct omap_dma_dev_attr
*d
;
71 static int enable_1510_mode
;
74 static struct omap_dma_global_context_registers
{
76 u32 dma_ocp_sysconfig
;
78 } omap_dma_global_context
;
80 struct dma_link_info
{
82 int no_of_lchs_linked
;
93 static struct dma_link_info
*dma_linked_lch
;
95 #ifndef CONFIG_ARCH_OMAP1
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
129 static int dma_lch_count
;
130 static int dma_chan_count
;
131 static int omap_dma_reserve_channels
;
133 static spinlock_t dma_chan_lock
;
134 static struct omap_dma_lch
*dma_chan
;
136 static inline void disable_lnk(int lch
);
137 static void omap_disable_channel_irq(int lch
);
138 static inline void omap_enable_channel_irq(int lch
);
140 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
143 #ifdef CONFIG_ARCH_OMAP15XX
144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
145 static int omap_dma_in_1510_mode(void)
147 return enable_1510_mode
;
150 #define omap_dma_in_1510_mode() 0
153 #ifdef CONFIG_ARCH_OMAP1
154 static inline int get_gdma_dev(int req
)
156 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
157 int shift
= ((req
- 1) % 5) * 6;
159 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
162 static inline void set_gdma_dev(int req
, int dev
)
164 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
165 int shift
= ((req
- 1) % 5) * 6;
169 l
&= ~(0x3f << shift
);
170 l
|= (dev
- 1) << shift
;
174 #define set_gdma_dev(req, dev) do {} while (0)
175 #define omap_readl(reg) 0
176 #define omap_writel(val, reg) do {} while (0)
179 #ifdef CONFIG_ARCH_OMAP1
180 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
185 if (cpu_class_is_omap1()) {
187 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
188 reg
= OMAP_TC_OCPT1_PRIOR
;
190 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
191 reg
= OMAP_TC_OCPT2_PRIOR
;
193 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
194 reg
= OMAP_TC_EMIFF_PRIOR
;
196 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
197 reg
= OMAP_TC_EMIFS_PRIOR
;
205 l
|= (priority
& 0xf) << 8;
211 #ifdef CONFIG_ARCH_OMAP2PLUS
212 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
216 ccr
= p
->dma_read(CCR
, lch
);
221 p
->dma_write(ccr
, CCR
, lch
);
224 EXPORT_SYMBOL(omap_set_dma_priority
);
226 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
227 int frame_count
, int sync_mode
,
228 int dma_trigger
, int src_or_dst_synch
)
232 l
= p
->dma_read(CSDP
, lch
);
235 p
->dma_write(l
, CSDP
, lch
);
237 if (cpu_class_is_omap1()) {
240 ccr
= p
->dma_read(CCR
, lch
);
242 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
244 p
->dma_write(ccr
, CCR
, lch
);
246 ccr
= p
->dma_read(CCR2
, lch
);
248 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
250 p
->dma_write(ccr
, CCR2
, lch
);
253 if (cpu_class_is_omap2() && dma_trigger
) {
256 val
= p
->dma_read(CCR
, lch
);
258 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
259 val
&= ~((1 << 23) | (3 << 19) | 0x1f);
260 val
|= (dma_trigger
& ~0x1f) << 14;
261 val
|= dma_trigger
& 0x1f;
263 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
268 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
273 if (src_or_dst_synch
== OMAP_DMA_DST_SYNC_PREFETCH
) {
274 val
&= ~(1 << 24); /* dest synch */
275 val
|= (1 << 23); /* Prefetch */
276 } else if (src_or_dst_synch
) {
277 val
|= 1 << 24; /* source synch */
279 val
&= ~(1 << 24); /* dest synch */
281 p
->dma_write(val
, CCR
, lch
);
284 p
->dma_write(elem_count
, CEN
, lch
);
285 p
->dma_write(frame_count
, CFN
, lch
);
287 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
289 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
291 BUG_ON(omap_dma_in_1510_mode());
293 if (cpu_class_is_omap1()) {
296 w
= p
->dma_read(CCR2
, lch
);
300 case OMAP_DMA_CONSTANT_FILL
:
303 case OMAP_DMA_TRANSPARENT_COPY
:
306 case OMAP_DMA_COLOR_DIS
:
311 p
->dma_write(w
, CCR2
, lch
);
313 w
= p
->dma_read(LCH_CTRL
, lch
);
315 /* Default is channel type 2D */
317 p
->dma_write(color
, COLOR
, lch
);
318 w
|= 1; /* Channel type G */
320 p
->dma_write(w
, LCH_CTRL
, lch
);
323 if (cpu_class_is_omap2()) {
326 val
= p
->dma_read(CCR
, lch
);
327 val
&= ~((1 << 17) | (1 << 16));
330 case OMAP_DMA_CONSTANT_FILL
:
333 case OMAP_DMA_TRANSPARENT_COPY
:
336 case OMAP_DMA_COLOR_DIS
:
341 p
->dma_write(val
, CCR
, lch
);
344 p
->dma_write(color
, COLOR
, lch
);
347 EXPORT_SYMBOL(omap_set_dma_color_mode
);
349 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
351 if (cpu_class_is_omap2()) {
354 csdp
= p
->dma_read(CSDP
, lch
);
355 csdp
&= ~(0x3 << 16);
356 csdp
|= (mode
<< 16);
357 p
->dma_write(csdp
, CSDP
, lch
);
360 EXPORT_SYMBOL(omap_set_dma_write_mode
);
362 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
364 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
367 l
= p
->dma_read(LCH_CTRL
, lch
);
370 p
->dma_write(l
, LCH_CTRL
, lch
);
373 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
375 /* Note that src_port is only for omap1 */
376 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
377 unsigned long src_start
,
378 int src_ei
, int src_fi
)
382 if (cpu_class_is_omap1()) {
385 w
= p
->dma_read(CSDP
, lch
);
388 p
->dma_write(w
, CSDP
, lch
);
391 l
= p
->dma_read(CCR
, lch
);
393 l
|= src_amode
<< 12;
394 p
->dma_write(l
, CCR
, lch
);
396 p
->dma_write(src_start
, CSSA
, lch
);
398 p
->dma_write(src_ei
, CSEI
, lch
);
399 p
->dma_write(src_fi
, CSFI
, lch
);
401 EXPORT_SYMBOL(omap_set_dma_src_params
);
403 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
405 omap_set_dma_transfer_params(lch
, params
->data_type
,
406 params
->elem_count
, params
->frame_count
,
407 params
->sync_mode
, params
->trigger
,
408 params
->src_or_dst_synch
);
409 omap_set_dma_src_params(lch
, params
->src_port
,
410 params
->src_amode
, params
->src_start
,
411 params
->src_ei
, params
->src_fi
);
413 omap_set_dma_dest_params(lch
, params
->dst_port
,
414 params
->dst_amode
, params
->dst_start
,
415 params
->dst_ei
, params
->dst_fi
);
416 if (params
->read_prio
|| params
->write_prio
)
417 omap_dma_set_prio_lch(lch
, params
->read_prio
,
420 EXPORT_SYMBOL(omap_set_dma_params
);
422 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
424 if (cpu_class_is_omap2())
427 p
->dma_write(eidx
, CSEI
, lch
);
428 p
->dma_write(fidx
, CSFI
, lch
);
430 EXPORT_SYMBOL(omap_set_dma_src_index
);
432 void omap_set_dma_src_data_pack(int lch
, int enable
)
436 l
= p
->dma_read(CSDP
, lch
);
440 p
->dma_write(l
, CSDP
, lch
);
442 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
444 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
446 unsigned int burst
= 0;
449 l
= p
->dma_read(CSDP
, lch
);
452 switch (burst_mode
) {
453 case OMAP_DMA_DATA_BURST_DIS
:
455 case OMAP_DMA_DATA_BURST_4
:
456 if (cpu_class_is_omap2())
461 case OMAP_DMA_DATA_BURST_8
:
462 if (cpu_class_is_omap2()) {
467 * not supported by current hardware on OMAP1
471 case OMAP_DMA_DATA_BURST_16
:
472 if (cpu_class_is_omap2()) {
477 * OMAP1 don't support burst 16
485 p
->dma_write(l
, CSDP
, lch
);
487 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
489 /* Note that dest_port is only for OMAP1 */
490 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
491 unsigned long dest_start
,
492 int dst_ei
, int dst_fi
)
496 if (cpu_class_is_omap1()) {
497 l
= p
->dma_read(CSDP
, lch
);
500 p
->dma_write(l
, CSDP
, lch
);
503 l
= p
->dma_read(CCR
, lch
);
505 l
|= dest_amode
<< 14;
506 p
->dma_write(l
, CCR
, lch
);
508 p
->dma_write(dest_start
, CDSA
, lch
);
510 p
->dma_write(dst_ei
, CDEI
, lch
);
511 p
->dma_write(dst_fi
, CDFI
, lch
);
513 EXPORT_SYMBOL(omap_set_dma_dest_params
);
515 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
517 if (cpu_class_is_omap2())
520 p
->dma_write(eidx
, CDEI
, lch
);
521 p
->dma_write(fidx
, CDFI
, lch
);
523 EXPORT_SYMBOL(omap_set_dma_dest_index
);
525 void omap_set_dma_dest_data_pack(int lch
, int enable
)
529 l
= p
->dma_read(CSDP
, lch
);
533 p
->dma_write(l
, CSDP
, lch
);
535 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
537 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
539 unsigned int burst
= 0;
542 l
= p
->dma_read(CSDP
, lch
);
545 switch (burst_mode
) {
546 case OMAP_DMA_DATA_BURST_DIS
:
548 case OMAP_DMA_DATA_BURST_4
:
549 if (cpu_class_is_omap2())
554 case OMAP_DMA_DATA_BURST_8
:
555 if (cpu_class_is_omap2())
560 case OMAP_DMA_DATA_BURST_16
:
561 if (cpu_class_is_omap2()) {
566 * OMAP1 don't support burst 16
570 printk(KERN_ERR
"Invalid DMA burst mode\n");
575 p
->dma_write(l
, CSDP
, lch
);
577 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
579 static inline void omap_enable_channel_irq(int lch
)
582 if (cpu_class_is_omap1())
583 p
->dma_read(CSR
, lch
);
585 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
587 /* Enable some nice interrupts. */
588 p
->dma_write(dma_chan
[lch
].enabled_irqs
, CICR
, lch
);
591 static inline void omap_disable_channel_irq(int lch
)
593 /* disable channel interrupts */
594 p
->dma_write(0, CICR
, lch
);
596 if (cpu_class_is_omap1())
597 p
->dma_read(CSR
, lch
);
599 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
602 void omap_enable_dma_irq(int lch
, u16 bits
)
604 dma_chan
[lch
].enabled_irqs
|= bits
;
606 EXPORT_SYMBOL(omap_enable_dma_irq
);
608 void omap_disable_dma_irq(int lch
, u16 bits
)
610 dma_chan
[lch
].enabled_irqs
&= ~bits
;
612 EXPORT_SYMBOL(omap_disable_dma_irq
);
614 static inline void enable_lnk(int lch
)
618 l
= p
->dma_read(CLNK_CTRL
, lch
);
620 if (cpu_class_is_omap1())
623 /* Set the ENABLE_LNK bits */
624 if (dma_chan
[lch
].next_lch
!= -1)
625 l
= dma_chan
[lch
].next_lch
| (1 << 15);
627 #ifndef CONFIG_ARCH_OMAP1
628 if (cpu_class_is_omap2())
629 if (dma_chan
[lch
].next_linked_ch
!= -1)
630 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
633 p
->dma_write(l
, CLNK_CTRL
, lch
);
636 static inline void disable_lnk(int lch
)
640 l
= p
->dma_read(CLNK_CTRL
, lch
);
642 /* Disable interrupts */
643 omap_disable_channel_irq(lch
);
645 if (cpu_class_is_omap1()) {
646 /* Set the STOP_LNK bit */
650 if (cpu_class_is_omap2()) {
651 /* Clear the ENABLE_LNK bit */
655 p
->dma_write(l
, CLNK_CTRL
, lch
);
656 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
659 static inline void omap2_enable_irq_lch(int lch
)
664 if (!cpu_class_is_omap2())
667 spin_lock_irqsave(&dma_chan_lock
, flags
);
668 /* clear IRQ STATUS */
669 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
670 /* Enable interrupt */
671 val
= p
->dma_read(IRQENABLE_L0
, lch
);
673 p
->dma_write(val
, IRQENABLE_L0
, lch
);
674 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
677 static inline void omap2_disable_irq_lch(int lch
)
682 if (!cpu_class_is_omap2())
685 spin_lock_irqsave(&dma_chan_lock
, flags
);
686 /* Disable interrupt */
687 val
= p
->dma_read(IRQENABLE_L0
, lch
);
689 p
->dma_write(val
, IRQENABLE_L0
, lch
);
690 /* clear IRQ STATUS */
691 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
692 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
695 int omap_request_dma(int dev_id
, const char *dev_name
,
696 void (*callback
)(int lch
, u16 ch_status
, void *data
),
697 void *data
, int *dma_ch_out
)
699 int ch
, free_ch
= -1;
701 struct omap_dma_lch
*chan
;
703 spin_lock_irqsave(&dma_chan_lock
, flags
);
704 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
705 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
712 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
715 chan
= dma_chan
+ free_ch
;
716 chan
->dev_id
= dev_id
;
718 if (p
->clear_lch_regs
)
719 p
->clear_lch_regs(free_ch
);
721 if (cpu_class_is_omap2())
722 omap_clear_dma(free_ch
);
724 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
726 chan
->dev_name
= dev_name
;
727 chan
->callback
= callback
;
731 #ifndef CONFIG_ARCH_OMAP1
732 if (cpu_class_is_omap2()) {
734 chan
->next_linked_ch
= -1;
738 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
740 if (cpu_class_is_omap1())
741 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
742 else if (cpu_class_is_omap2())
743 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
744 OMAP2_DMA_TRANS_ERR_IRQ
;
746 if (cpu_is_omap16xx()) {
747 /* If the sync device is set, configure it dynamically. */
749 set_gdma_dev(free_ch
+ 1, dev_id
);
750 dev_id
= free_ch
+ 1;
753 * Disable the 1510 compatibility mode and set the sync device
756 p
->dma_write(dev_id
| (1 << 10), CCR
, free_ch
);
757 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
758 p
->dma_write(dev_id
, CCR
, free_ch
);
761 if (cpu_class_is_omap2()) {
762 omap_enable_channel_irq(free_ch
);
763 omap2_enable_irq_lch(free_ch
);
766 *dma_ch_out
= free_ch
;
770 EXPORT_SYMBOL(omap_request_dma
);
772 void omap_free_dma(int lch
)
776 if (dma_chan
[lch
].dev_id
== -1) {
777 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
782 /* Disable interrupt for logical channel */
783 if (cpu_class_is_omap2())
784 omap2_disable_irq_lch(lch
);
786 /* Disable all DMA interrupts for the channel. */
787 omap_disable_channel_irq(lch
);
789 /* Make sure the DMA transfer is stopped. */
790 p
->dma_write(0, CCR
, lch
);
792 /* Clear registers */
793 if (cpu_class_is_omap2())
796 spin_lock_irqsave(&dma_chan_lock
, flags
);
797 dma_chan
[lch
].dev_id
= -1;
798 dma_chan
[lch
].next_lch
= -1;
799 dma_chan
[lch
].callback
= NULL
;
800 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
802 EXPORT_SYMBOL(omap_free_dma
);
805 * @brief omap_dma_set_global_params : Set global priority settings for dma
808 * @param max_fifo_depth
809 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
810 * DMA_THREAD_RESERVE_ONET
811 * DMA_THREAD_RESERVE_TWOT
812 * DMA_THREAD_RESERVE_THREET
815 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
819 if (!cpu_class_is_omap2()) {
820 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
824 if (max_fifo_depth
== 0)
829 reg
= 0xff & max_fifo_depth
;
830 reg
|= (0x3 & tparams
) << 12;
831 reg
|= (arb_rate
& 0xff) << 16;
833 p
->dma_write(reg
, GCR
, 0);
835 EXPORT_SYMBOL(omap_dma_set_global_params
);
838 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
841 * @param read_prio - Read priority
842 * @param write_prio - Write priority
843 * Both of the above can be set with one of the following values :
844 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
847 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
848 unsigned char write_prio
)
852 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
853 printk(KERN_ERR
"Invalid channel id\n");
856 l
= p
->dma_read(CCR
, lch
);
857 l
&= ~((1 << 6) | (1 << 26));
858 if (cpu_class_is_omap2() && !cpu_is_omap242x())
859 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
861 l
|= ((read_prio
& 0x1) << 6);
863 p
->dma_write(l
, CCR
, lch
);
867 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
870 * Clears any DMA state so the DMA engine is ready to restart with new buffers
871 * through omap_start_dma(). Any buffers in flight are discarded.
873 void omap_clear_dma(int lch
)
877 local_irq_save(flags
);
879 local_irq_restore(flags
);
881 EXPORT_SYMBOL(omap_clear_dma
);
883 void omap_start_dma(int lch
)
888 * The CPC/CDAC register needs to be initialized to zero
889 * before starting dma transfer.
891 if (cpu_is_omap15xx())
892 p
->dma_write(0, CPC
, lch
);
894 p
->dma_write(0, CDAC
, lch
);
896 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
897 int next_lch
, cur_lch
;
898 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
900 dma_chan_link_map
[lch
] = 1;
901 /* Set the link register of the first channel */
904 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
905 cur_lch
= dma_chan
[lch
].next_lch
;
907 next_lch
= dma_chan
[cur_lch
].next_lch
;
909 /* The loop case: we've been here already */
910 if (dma_chan_link_map
[cur_lch
])
912 /* Mark the current channel */
913 dma_chan_link_map
[cur_lch
] = 1;
916 omap_enable_channel_irq(cur_lch
);
919 } while (next_lch
!= -1);
920 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS
))
921 p
->dma_write(lch
, CLNK_CTRL
, lch
);
923 omap_enable_channel_irq(lch
);
925 l
= p
->dma_read(CCR
, lch
);
927 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING
))
928 l
|= OMAP_DMA_CCR_BUFFERING_DISABLE
;
929 l
|= OMAP_DMA_CCR_EN
;
932 * As dma_write() uses IO accessors which are weakly ordered, there
933 * is no guarantee that data in coherent DMA memory will be visible
934 * to the DMA device. Add a memory barrier here to ensure that any
935 * such data is visible prior to enabling DMA.
938 p
->dma_write(l
, CCR
, lch
);
940 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
942 EXPORT_SYMBOL(omap_start_dma
);
944 void omap_stop_dma(int lch
)
948 /* Disable all interrupts on the channel */
949 omap_disable_channel_irq(lch
);
951 l
= p
->dma_read(CCR
, lch
);
952 if (IS_DMA_ERRATA(DMA_ERRATA_i541
) &&
953 (l
& OMAP_DMA_CCR_SEL_SRC_DST_SYNC
)) {
957 /* Configure No-Standby */
958 l
= p
->dma_read(OCP_SYSCONFIG
, lch
);
960 l
&= ~DMA_SYSCONFIG_MIDLEMODE_MASK
;
961 l
|= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE
);
962 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
964 l
= p
->dma_read(CCR
, lch
);
965 l
&= ~OMAP_DMA_CCR_EN
;
966 p
->dma_write(l
, CCR
, lch
);
968 /* Wait for sDMA FIFO drain */
969 l
= p
->dma_read(CCR
, lch
);
970 while (i
< 100 && (l
& (OMAP_DMA_CCR_RD_ACTIVE
|
971 OMAP_DMA_CCR_WR_ACTIVE
))) {
974 l
= p
->dma_read(CCR
, lch
);
977 pr_err("DMA drain did not complete on lch %d\n", lch
);
978 /* Restore OCP_SYSCONFIG */
979 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, lch
);
981 l
&= ~OMAP_DMA_CCR_EN
;
982 p
->dma_write(l
, CCR
, lch
);
986 * Ensure that data transferred by DMA is visible to any access
987 * after DMA has been disabled. This is important for coherent
992 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
993 int next_lch
, cur_lch
= lch
;
994 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
996 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
998 /* The loop case: we've been here already */
999 if (dma_chan_link_map
[cur_lch
])
1001 /* Mark the current channel */
1002 dma_chan_link_map
[cur_lch
] = 1;
1004 disable_lnk(cur_lch
);
1006 next_lch
= dma_chan
[cur_lch
].next_lch
;
1008 } while (next_lch
!= -1);
1011 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
1013 EXPORT_SYMBOL(omap_stop_dma
);
1016 * Allows changing the DMA callback function or data. This may be needed if
1017 * the driver shares a single DMA channel for multiple dma triggers.
1019 int omap_set_dma_callback(int lch
,
1020 void (*callback
)(int lch
, u16 ch_status
, void *data
),
1023 unsigned long flags
;
1028 spin_lock_irqsave(&dma_chan_lock
, flags
);
1029 if (dma_chan
[lch
].dev_id
== -1) {
1030 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1031 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1034 dma_chan
[lch
].callback
= callback
;
1035 dma_chan
[lch
].data
= data
;
1036 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1040 EXPORT_SYMBOL(omap_set_dma_callback
);
1043 * Returns current physical source address for the given DMA channel.
1044 * If the channel is running the caller must disable interrupts prior calling
1045 * this function and process the returned value before re-enabling interrupt to
1046 * prevent races with the interrupt handler. Note that in continuous mode there
1047 * is a chance for CSSA_L register overflow between the two reads resulting
1048 * in incorrect return value.
1050 dma_addr_t
omap_get_dma_src_pos(int lch
)
1052 dma_addr_t offset
= 0;
1054 if (cpu_is_omap15xx())
1055 offset
= p
->dma_read(CPC
, lch
);
1057 offset
= p
->dma_read(CSAC
, lch
);
1059 if (IS_DMA_ERRATA(DMA_ERRATA_3_3
) && offset
== 0)
1060 offset
= p
->dma_read(CSAC
, lch
);
1062 if (!cpu_is_omap15xx()) {
1064 * CDAC == 0 indicates that the DMA transfer on the channel has
1065 * not been started (no data has been transferred so far).
1066 * Return the programmed source start address in this case.
1068 if (likely(p
->dma_read(CDAC
, lch
)))
1069 offset
= p
->dma_read(CSAC
, lch
);
1071 offset
= p
->dma_read(CSSA
, lch
);
1074 if (cpu_class_is_omap1())
1075 offset
|= (p
->dma_read(CSSA
, lch
) & 0xFFFF0000);
1079 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1082 * Returns current physical destination address for the given DMA channel.
1083 * If the channel is running the caller must disable interrupts prior calling
1084 * this function and process the returned value before re-enabling interrupt to
1085 * prevent races with the interrupt handler. Note that in continuous mode there
1086 * is a chance for CDSA_L register overflow between the two reads resulting
1087 * in incorrect return value.
1089 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1091 dma_addr_t offset
= 0;
1093 if (cpu_is_omap15xx())
1094 offset
= p
->dma_read(CPC
, lch
);
1096 offset
= p
->dma_read(CDAC
, lch
);
1099 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1100 * read before the DMA controller finished disabling the channel.
1102 if (!cpu_is_omap15xx() && offset
== 0) {
1103 offset
= p
->dma_read(CDAC
, lch
);
1105 * CDAC == 0 indicates that the DMA transfer on the channel has
1106 * not been started (no data has been transferred so far).
1107 * Return the programmed destination start address in this case.
1109 if (unlikely(!offset
))
1110 offset
= p
->dma_read(CDSA
, lch
);
1113 if (cpu_class_is_omap1())
1114 offset
|= (p
->dma_read(CDSA
, lch
) & 0xFFFF0000);
1118 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1120 int omap_get_dma_active_status(int lch
)
1122 return (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
) != 0;
1124 EXPORT_SYMBOL(omap_get_dma_active_status
);
1126 int omap_dma_running(void)
1130 if (cpu_class_is_omap1())
1131 if (omap_lcd_dma_running())
1134 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1135 if (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
)
1142 * lch_queue DMA will start right after lch_head one is finished.
1143 * For this DMA link to start, you still need to start (see omap_start_dma)
1144 * the first one. That will fire up the entire queue.
1146 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1148 if (omap_dma_in_1510_mode()) {
1149 if (lch_head
== lch_queue
) {
1150 p
->dma_write(p
->dma_read(CCR
, lch_head
) | (3 << 8),
1154 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1159 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1160 (dma_chan
[lch_queue
].dev_id
== -1)) {
1161 pr_err("omap_dma: trying to link non requested channels\n");
1165 dma_chan
[lch_head
].next_lch
= lch_queue
;
1167 EXPORT_SYMBOL(omap_dma_link_lch
);
1170 * Once the DMA queue is stopped, we can destroy it.
1172 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1174 if (omap_dma_in_1510_mode()) {
1175 if (lch_head
== lch_queue
) {
1176 p
->dma_write(p
->dma_read(CCR
, lch_head
) & ~(3 << 8),
1180 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1185 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1186 dma_chan
[lch_head
].next_lch
== -1) {
1187 pr_err("omap_dma: trying to unlink non linked channels\n");
1191 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1192 (dma_chan
[lch_queue
].flags
& OMAP_DMA_ACTIVE
)) {
1193 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1197 dma_chan
[lch_head
].next_lch
= -1;
1199 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1201 #ifndef CONFIG_ARCH_OMAP1
1202 /* Create chain of DMA channesls */
1203 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1207 /* Check if this is the first link in chain */
1208 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1209 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1210 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1211 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1212 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1215 /* a link exists, link the new channel in circular chain */
1217 dma_chan
[lch_queue
].next_linked_ch
=
1218 dma_chan
[lch_head
].next_linked_ch
;
1219 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1220 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1221 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1225 l
= p
->dma_read(CLNK_CTRL
, lch_head
);
1228 p
->dma_write(l
, CLNK_CTRL
, lch_head
);
1230 l
= p
->dma_read(CLNK_CTRL
, lch_queue
);
1232 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1233 p
->dma_write(l
, CLNK_CTRL
, lch_queue
);
1237 * @brief omap_request_dma_chain : Request a chain of DMA channels
1239 * @param dev_id - Device id using the dma channel
1240 * @param dev_name - Device name
1241 * @param callback - Call back function
1243 * @no_of_chans - Number of channels requested
1244 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1245 * OMAP_DMA_DYNAMIC_CHAIN
1246 * @params - Channel parameters
1248 * @return - Success : 0
1249 * Failure: -EINVAL/-ENOMEM
1251 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1252 void (*callback
) (int lch
, u16 ch_status
,
1254 int *chain_id
, int no_of_chans
, int chain_mode
,
1255 struct omap_dma_channel_params params
)
1260 /* Is the chain mode valid ? */
1261 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1262 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1263 printk(KERN_ERR
"Invalid chain mode requested\n");
1267 if (unlikely((no_of_chans
< 1
1268 || no_of_chans
> dma_lch_count
))) {
1269 printk(KERN_ERR
"Invalid Number of channels requested\n");
1274 * Allocate a queue to maintain the status of the channels
1277 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1278 if (channels
== NULL
) {
1279 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1283 /* request and reserve DMA channels for the chain */
1284 for (i
= 0; i
< no_of_chans
; i
++) {
1285 err
= omap_request_dma(dev_id
, dev_name
,
1286 callback
, NULL
, &channels
[i
]);
1289 for (j
= 0; j
< i
; j
++)
1290 omap_free_dma(channels
[j
]);
1292 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1295 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1296 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1299 * Allowing client drivers to set common parameters now,
1300 * so that later only relevant (src_start, dest_start
1301 * and element count) can be set
1303 omap_set_dma_params(channels
[i
], ¶ms
);
1306 *chain_id
= channels
[0];
1307 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1308 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1309 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1310 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1312 for (i
= 0; i
< no_of_chans
; i
++)
1313 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1315 /* Reset the Queue pointers */
1316 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1318 /* Set up the chain */
1319 if (no_of_chans
== 1)
1320 create_dma_lch_chain(channels
[0], channels
[0]);
1322 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1323 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1328 EXPORT_SYMBOL(omap_request_dma_chain
);
1331 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1332 * params after setting it. Dont do this while dma is running!!
1334 * @param chain_id - Chained logical channel id.
1337 * @return - Success : 0
1340 int omap_modify_dma_chain_params(int chain_id
,
1341 struct omap_dma_channel_params params
)
1346 /* Check for input params */
1347 if (unlikely((chain_id
< 0
1348 || chain_id
>= dma_lch_count
))) {
1349 printk(KERN_ERR
"Invalid chain id\n");
1353 /* Check if the chain exists */
1354 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1355 printk(KERN_ERR
"Chain doesn't exists\n");
1358 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1360 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1362 * Allowing client drivers to set common parameters now,
1363 * so that later only relevant (src_start, dest_start
1364 * and element count) can be set
1366 omap_set_dma_params(channels
[i
], ¶ms
);
1371 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1374 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1378 * @return - Success : 0
1381 int omap_free_dma_chain(int chain_id
)
1386 /* Check for input params */
1387 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1388 printk(KERN_ERR
"Invalid chain id\n");
1392 /* Check if the chain exists */
1393 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1394 printk(KERN_ERR
"Chain doesn't exists\n");
1398 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1399 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1400 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1401 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1402 dma_chan
[channels
[i
]].chain_id
= -1;
1403 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1404 omap_free_dma(channels
[i
]);
1409 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1410 dma_linked_lch
[chain_id
].chain_mode
= -1;
1411 dma_linked_lch
[chain_id
].chain_state
= -1;
1415 EXPORT_SYMBOL(omap_free_dma_chain
);
1418 * @brief omap_dma_chain_status - Check if the chain is in
1419 * active / inactive state.
1422 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1425 int omap_dma_chain_status(int chain_id
)
1427 /* Check for input params */
1428 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1429 printk(KERN_ERR
"Invalid chain id\n");
1433 /* Check if the chain exists */
1434 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1435 printk(KERN_ERR
"Chain doesn't exists\n");
1438 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1439 dma_linked_lch
[chain_id
].q_count
);
1441 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1442 return OMAP_DMA_CHAIN_INACTIVE
;
1444 return OMAP_DMA_CHAIN_ACTIVE
;
1446 EXPORT_SYMBOL(omap_dma_chain_status
);
1449 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1450 * set the params and start the transfer.
1453 * @param src_start - buffer start address
1454 * @param dest_start - Dest address
1456 * @param frame_count
1457 * @param callbk_data - channel callback parameter data.
1459 * @return - Success : 0
1460 * Failure: -EINVAL/-EBUSY
1462 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1463 int elem_count
, int frame_count
, void *callbk_data
)
1470 * if buffer size is less than 1 then there is
1471 * no use of starting the chain
1473 if (elem_count
< 1) {
1474 printk(KERN_ERR
"Invalid buffer size\n");
1478 /* Check for input params */
1479 if (unlikely((chain_id
< 0
1480 || chain_id
>= dma_lch_count
))) {
1481 printk(KERN_ERR
"Invalid chain id\n");
1485 /* Check if the chain exists */
1486 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1487 printk(KERN_ERR
"Chain doesn't exist\n");
1491 /* Check if all the channels in chain are in use */
1492 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1495 /* Frame count may be negative in case of indexed transfers */
1496 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1498 /* Get a free channel */
1499 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1501 /* Store the callback data */
1502 dma_chan
[lch
].data
= callbk_data
;
1504 /* Increment the q_tail */
1505 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1507 /* Set the params to the free channel */
1509 p
->dma_write(src_start
, CSSA
, lch
);
1510 if (dest_start
!= 0)
1511 p
->dma_write(dest_start
, CDSA
, lch
);
1513 /* Write the buffer size */
1514 p
->dma_write(elem_count
, CEN
, lch
);
1515 p
->dma_write(frame_count
, CFN
, lch
);
1518 * If the chain is dynamically linked,
1519 * then we may have to start the chain if its not active
1521 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1524 * In Dynamic chain, if the chain is not started,
1527 if (dma_linked_lch
[chain_id
].chain_state
==
1528 DMA_CHAIN_NOTSTARTED
) {
1529 /* Enable the link in previous channel */
1530 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1532 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1533 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1537 * Chain is already started, make sure its active,
1538 * if not then start the chain
1543 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1545 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1546 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1548 if (0 == ((1 << 7) & p
->dma_read(
1549 CCR
, dma_chan
[lch
].prev_linked_ch
))) {
1550 disable_lnk(dma_chan
[lch
].
1552 pr_debug("\n prev ch is stopped\n");
1557 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1559 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1560 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1563 omap_enable_channel_irq(lch
);
1565 l
= p
->dma_read(CCR
, lch
);
1567 if ((0 == (l
& (1 << 24))))
1571 if (start_dma
== 1) {
1572 if (0 == (l
& (1 << 7))) {
1574 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1575 pr_debug("starting %d\n", lch
);
1576 p
->dma_write(l
, CCR
, lch
);
1580 if (0 == (l
& (1 << 7)))
1581 p
->dma_write(l
, CCR
, lch
);
1583 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1589 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1592 * @brief omap_start_dma_chain_transfers - Start the chain
1596 * @return - Success : 0
1597 * Failure : -EINVAL/-EBUSY
1599 int omap_start_dma_chain_transfers(int chain_id
)
1604 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1605 printk(KERN_ERR
"Invalid chain id\n");
1609 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1611 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1612 printk(KERN_ERR
"Chain is already started\n");
1616 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1617 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1619 enable_lnk(channels
[i
]);
1620 omap_enable_channel_irq(channels
[i
]);
1623 omap_enable_channel_irq(channels
[0]);
1626 l
= p
->dma_read(CCR
, channels
[0]);
1628 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1629 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1631 if ((0 == (l
& (1 << 24))))
1635 p
->dma_write(l
, CCR
, channels
[0]);
1637 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1641 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1644 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1648 * @return - Success : 0
1651 int omap_stop_dma_chain_transfers(int chain_id
)
1657 /* Check for input params */
1658 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1659 printk(KERN_ERR
"Invalid chain id\n");
1663 /* Check if the chain exists */
1664 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1665 printk(KERN_ERR
"Chain doesn't exists\n");
1668 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1670 if (IS_DMA_ERRATA(DMA_ERRATA_i88
)) {
1671 sys_cf
= p
->dma_read(OCP_SYSCONFIG
, 0);
1673 /* Middle mode reg set no Standby */
1674 l
&= ~((1 << 12)|(1 << 13));
1675 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
1678 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1680 /* Stop the Channel transmission */
1681 l
= p
->dma_read(CCR
, channels
[i
]);
1683 p
->dma_write(l
, CCR
, channels
[i
]);
1685 /* Disable the link in all the channels */
1686 disable_lnk(channels
[i
]);
1687 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1690 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1692 /* Reset the Queue pointers */
1693 OMAP_DMA_CHAIN_QINIT(chain_id
);
1695 if (IS_DMA_ERRATA(DMA_ERRATA_i88
))
1696 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, 0);
1700 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1702 /* Get the index of the ongoing DMA in chain */
1704 * @brief omap_get_dma_chain_index - Get the element and frame index
1705 * of the ongoing DMA in chain
1708 * @param ei - Element index
1709 * @param fi - Frame index
1711 * @return - Success : 0
1714 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1719 /* Check for input params */
1720 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1721 printk(KERN_ERR
"Invalid chain id\n");
1725 /* Check if the chain exists */
1726 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1727 printk(KERN_ERR
"Chain doesn't exists\n");
1733 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1735 /* Get the current channel */
1736 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1738 *ei
= p
->dma_read(CCEN
, lch
);
1739 *fi
= p
->dma_read(CCFN
, lch
);
1743 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1746 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1747 * ongoing DMA in chain
1751 * @return - Success : Destination position
1754 int omap_get_dma_chain_dst_pos(int chain_id
)
1759 /* Check for input params */
1760 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1761 printk(KERN_ERR
"Invalid chain id\n");
1765 /* Check if the chain exists */
1766 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1767 printk(KERN_ERR
"Chain doesn't exists\n");
1771 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1773 /* Get the current channel */
1774 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1776 return p
->dma_read(CDAC
, lch
);
1778 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1781 * @brief omap_get_dma_chain_src_pos - Get the source position
1782 * of the ongoing DMA in chain
1785 * @return - Success : Destination position
1788 int omap_get_dma_chain_src_pos(int chain_id
)
1793 /* Check for input params */
1794 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1795 printk(KERN_ERR
"Invalid chain id\n");
1799 /* Check if the chain exists */
1800 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1801 printk(KERN_ERR
"Chain doesn't exists\n");
1805 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1807 /* Get the current channel */
1808 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1810 return p
->dma_read(CSAC
, lch
);
1812 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1813 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1815 /*----------------------------------------------------------------------------*/
1817 #ifdef CONFIG_ARCH_OMAP1
1819 static int omap1_dma_handle_ch(int ch
)
1823 if (enable_1510_mode
&& ch
>= 6) {
1824 csr
= dma_chan
[ch
].saved_csr
;
1825 dma_chan
[ch
].saved_csr
= 0;
1827 csr
= p
->dma_read(CSR
, ch
);
1828 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1829 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1832 if ((csr
& 0x3f) == 0)
1834 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1835 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1839 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1840 pr_warn("DMA timeout with device %d\n", dma_chan
[ch
].dev_id
);
1841 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1842 pr_warn("DMA synchronization event drop occurred with device %d\n",
1843 dma_chan
[ch
].dev_id
);
1844 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1845 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1846 if (likely(dma_chan
[ch
].callback
!= NULL
))
1847 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1852 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1854 int ch
= ((int) dev_id
) - 1;
1858 int handled_now
= 0;
1860 handled_now
+= omap1_dma_handle_ch(ch
);
1861 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1862 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1865 handled
+= handled_now
;
1868 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1872 #define omap1_dma_irq_handler NULL
1875 #ifdef CONFIG_ARCH_OMAP2PLUS
1877 static int omap2_dma_handle_ch(int ch
)
1879 u32 status
= p
->dma_read(CSR
, ch
);
1882 if (printk_ratelimit())
1883 pr_warn("Spurious DMA IRQ for lch %d\n", ch
);
1884 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1887 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1888 if (printk_ratelimit())
1889 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1893 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1894 pr_info("DMA synchronization event drop occurred with device %d\n",
1895 dma_chan
[ch
].dev_id
);
1896 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
)) {
1897 printk(KERN_INFO
"DMA transaction error with device %d\n",
1898 dma_chan
[ch
].dev_id
);
1899 if (IS_DMA_ERRATA(DMA_ERRATA_i378
)) {
1902 ccr
= p
->dma_read(CCR
, ch
);
1903 ccr
&= ~OMAP_DMA_CCR_EN
;
1904 p
->dma_write(ccr
, CCR
, ch
);
1905 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1908 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1909 printk(KERN_INFO
"DMA secure error with device %d\n",
1910 dma_chan
[ch
].dev_id
);
1911 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1912 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1913 dma_chan
[ch
].dev_id
);
1915 p
->dma_write(status
, CSR
, ch
);
1916 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1917 /* read back the register to flush the write */
1918 p
->dma_read(IRQSTATUS_L0
, ch
);
1920 /* If the ch is not chained then chain_id will be -1 */
1921 if (dma_chan
[ch
].chain_id
!= -1) {
1922 int chain_id
= dma_chan
[ch
].chain_id
;
1923 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1924 if (p
->dma_read(CLNK_CTRL
, ch
) & (1 << 15))
1925 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1927 if (dma_linked_lch
[chain_id
].chain_mode
==
1928 OMAP_DMA_DYNAMIC_CHAIN
)
1931 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1932 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1934 status
= p
->dma_read(CSR
, ch
);
1935 p
->dma_write(status
, CSR
, ch
);
1938 if (likely(dma_chan
[ch
].callback
!= NULL
))
1939 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1944 /* STATUS register count is from 1-32 while our is 0-31 */
1945 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1947 u32 val
, enable_reg
;
1950 val
= p
->dma_read(IRQSTATUS_L0
, 0);
1952 if (printk_ratelimit())
1953 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1956 enable_reg
= p
->dma_read(IRQENABLE_L0
, 0);
1957 val
&= enable_reg
; /* Dispatch only relevant interrupts */
1958 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1960 omap2_dma_handle_ch(i
);
1967 static struct irqaction omap24xx_dma_irq
= {
1969 .handler
= omap2_dma_irq_handler
,
1970 .flags
= IRQF_DISABLED
1974 static struct irqaction omap24xx_dma_irq
;
1977 /*----------------------------------------------------------------------------*/
1979 void omap_dma_global_context_save(void)
1981 omap_dma_global_context
.dma_irqenable_l0
=
1982 p
->dma_read(IRQENABLE_L0
, 0);
1983 omap_dma_global_context
.dma_ocp_sysconfig
=
1984 p
->dma_read(OCP_SYSCONFIG
, 0);
1985 omap_dma_global_context
.dma_gcr
= p
->dma_read(GCR
, 0);
1988 void omap_dma_global_context_restore(void)
1992 p
->dma_write(omap_dma_global_context
.dma_gcr
, GCR
, 0);
1993 p
->dma_write(omap_dma_global_context
.dma_ocp_sysconfig
,
1995 p
->dma_write(omap_dma_global_context
.dma_irqenable_l0
,
1998 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG
))
1999 p
->dma_write(0x3 , IRQSTATUS_L0
, 0);
2001 for (ch
= 0; ch
< dma_chan_count
; ch
++)
2002 if (dma_chan
[ch
].dev_id
!= -1)
2006 static int __devinit
omap_system_dma_probe(struct platform_device
*pdev
)
2013 p
= pdev
->dev
.platform_data
;
2016 "%s: System DMA initialized without platform data\n",
2024 if ((d
->dev_caps
& RESERVE_CHANNEL
) && omap_dma_reserve_channels
2025 && (omap_dma_reserve_channels
<= dma_lch_count
))
2026 d
->lch_count
= omap_dma_reserve_channels
;
2028 dma_lch_count
= d
->lch_count
;
2029 dma_chan_count
= dma_lch_count
;
2031 enable_1510_mode
= d
->dev_caps
& ENABLE_1510_MODE
;
2033 if (cpu_class_is_omap2()) {
2034 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2035 dma_lch_count
, GFP_KERNEL
);
2036 if (!dma_linked_lch
) {
2038 goto exit_dma_lch_fail
;
2042 spin_lock_init(&dma_chan_lock
);
2043 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2045 if (cpu_class_is_omap2())
2046 omap2_disable_irq_lch(ch
);
2048 dma_chan
[ch
].dev_id
= -1;
2049 dma_chan
[ch
].next_lch
= -1;
2051 if (ch
>= 6 && enable_1510_mode
)
2054 if (cpu_class_is_omap1()) {
2056 * request_irq() doesn't like dev_id (ie. ch) being
2057 * zero, so we have to kludge around this.
2059 sprintf(&irq_name
[0], "%d", ch
);
2060 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2064 goto exit_dma_irq_fail
;
2067 /* INT_DMA_LCD is handled in lcd_dma.c */
2068 if (dma_irq
== INT_DMA_LCD
)
2071 ret
= request_irq(dma_irq
,
2072 omap1_dma_irq_handler
, 0, "DMA",
2075 goto exit_dma_irq_fail
;
2079 if (cpu_class_is_omap2() && !cpu_is_omap242x())
2080 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2081 DMA_DEFAULT_FIFO_DEPTH
, 0);
2083 if (cpu_class_is_omap2()) {
2084 strcpy(irq_name
, "0");
2085 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2087 dev_err(&pdev
->dev
, "failed: request IRQ %d", dma_irq
);
2088 goto exit_dma_lch_fail
;
2090 ret
= setup_irq(dma_irq
, &omap24xx_dma_irq
);
2092 dev_err(&pdev
->dev
, "set_up failed for IRQ %d for DMA (error %d)\n",
2094 goto exit_dma_lch_fail
;
2098 /* reserve dma channels 0 and 1 in high security devices */
2099 if (cpu_is_omap34xx() &&
2100 (omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
2101 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2102 dma_chan
[0].dev_id
= 0;
2103 dma_chan
[1].dev_id
= 1;
2109 dev_err(&pdev
->dev
, "unable to request IRQ %d for DMA (error %d)\n",
2111 for (irq_rel
= 0; irq_rel
< ch
; irq_rel
++) {
2112 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2113 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2123 static int __devexit
omap_system_dma_remove(struct platform_device
*pdev
)
2127 if (cpu_class_is_omap2()) {
2129 strcpy(irq_name
, "0");
2130 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2131 remove_irq(dma_irq
, &omap24xx_dma_irq
);
2134 for ( ; irq_rel
< dma_chan_count
; irq_rel
++) {
2135 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2136 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2145 static struct platform_driver omap_system_dma_driver
= {
2146 .probe
= omap_system_dma_probe
,
2147 .remove
= __devexit_p(omap_system_dma_remove
),
2149 .name
= "omap_dma_system"
2153 static int __init
omap_system_dma_init(void)
2155 return platform_driver_register(&omap_system_dma_driver
);
2157 arch_initcall(omap_system_dma_init
);
2159 static void __exit
omap_system_dma_exit(void)
2161 platform_driver_unregister(&omap_system_dma_driver
);
2164 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2165 MODULE_LICENSE("GPL");
2166 MODULE_ALIAS("platform:" DRIVER_NAME
);
2167 MODULE_AUTHOR("Texas Instruments Inc");
2170 * Reserve the omap SDMA channels using cmdline bootarg
2171 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2173 static int __init
omap_dma_cmdline_reserve_ch(char *str
)
2175 if (get_option(&str
, &omap_dma_reserve_channels
) != 1)
2176 omap_dma_reserve_channels
= 0;
2180 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch
);