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Merge tag 'for-v3.17/omap-clock-b' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <linux/omap-dma.h>
40
41 /*
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
43 * channels that an instance of the SDMA IP block can support. Used
44 * to size arrays. (The actual maximum on a particular SoC may be less
45 * than this -- for example, OMAP1 SDMA instances only support 17 logical
46 * DMA channels.)
47 */
48 #define MAX_LOGICAL_DMA_CH_COUNT 32
49
50 #undef DEBUG
51
52 #ifndef CONFIG_ARCH_OMAP1
53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
54 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
55 };
56
57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
58 #endif
59
60 #define OMAP_DMA_ACTIVE 0x01
61 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
62
63 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
64
65 static struct omap_system_dma_plat_info *p;
66 static struct omap_dma_dev_attr *d;
67
68 static int enable_1510_mode;
69 static u32 errata;
70
71 static struct omap_dma_global_context_registers {
72 u32 dma_irqenable_l0;
73 u32 dma_irqenable_l1;
74 u32 dma_ocp_sysconfig;
75 u32 dma_gcr;
76 } omap_dma_global_context;
77
78 struct dma_link_info {
79 int *linked_dmach_q;
80 int no_of_lchs_linked;
81
82 int q_count;
83 int q_tail;
84 int q_head;
85
86 int chain_state;
87 int chain_mode;
88
89 };
90
91 static struct dma_link_info *dma_linked_lch;
92
93 #ifndef CONFIG_ARCH_OMAP1
94
95 /* Chain handling macros */
96 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 do { \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
101 } while (0)
102 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 do { \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
109 } while (0)
110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112 #define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
118 } while (0)
119
120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
124 } while (0)
125 #endif
126
127 static int dma_lch_count;
128 static int dma_chan_count;
129 static int omap_dma_reserve_channels;
130
131 static spinlock_t dma_chan_lock;
132 static struct omap_dma_lch *dma_chan;
133
134 static inline void disable_lnk(int lch);
135 static void omap_disable_channel_irq(int lch);
136 static inline void omap_enable_channel_irq(int lch);
137
138 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
139 __func__);
140
141 #ifdef CONFIG_ARCH_OMAP15XX
142 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
143 static int omap_dma_in_1510_mode(void)
144 {
145 return enable_1510_mode;
146 }
147 #else
148 #define omap_dma_in_1510_mode() 0
149 #endif
150
151 #ifdef CONFIG_ARCH_OMAP1
152 static inline int get_gdma_dev(int req)
153 {
154 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
155 int shift = ((req - 1) % 5) * 6;
156
157 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
158 }
159
160 static inline void set_gdma_dev(int req, int dev)
161 {
162 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
163 int shift = ((req - 1) % 5) * 6;
164 u32 l;
165
166 l = omap_readl(reg);
167 l &= ~(0x3f << shift);
168 l |= (dev - 1) << shift;
169 omap_writel(l, reg);
170 }
171 #else
172 #define set_gdma_dev(req, dev) do {} while (0)
173 #define omap_readl(reg) 0
174 #define omap_writel(val, reg) do {} while (0)
175 #endif
176
177 #ifdef CONFIG_ARCH_OMAP1
178 void omap_set_dma_priority(int lch, int dst_port, int priority)
179 {
180 unsigned long reg;
181 u32 l;
182
183 if (dma_omap1()) {
184 switch (dst_port) {
185 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
186 reg = OMAP_TC_OCPT1_PRIOR;
187 break;
188 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
189 reg = OMAP_TC_OCPT2_PRIOR;
190 break;
191 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
192 reg = OMAP_TC_EMIFF_PRIOR;
193 break;
194 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
195 reg = OMAP_TC_EMIFS_PRIOR;
196 break;
197 default:
198 BUG();
199 return;
200 }
201 l = omap_readl(reg);
202 l &= ~(0xf << 8);
203 l |= (priority & 0xf) << 8;
204 omap_writel(l, reg);
205 }
206 }
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP2PLUS
210 void omap_set_dma_priority(int lch, int dst_port, int priority)
211 {
212 u32 ccr;
213
214 ccr = p->dma_read(CCR, lch);
215 if (priority)
216 ccr |= (1 << 6);
217 else
218 ccr &= ~(1 << 6);
219 p->dma_write(ccr, CCR, lch);
220 }
221 #endif
222 EXPORT_SYMBOL(omap_set_dma_priority);
223
224 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
225 int frame_count, int sync_mode,
226 int dma_trigger, int src_or_dst_synch)
227 {
228 u32 l;
229
230 l = p->dma_read(CSDP, lch);
231 l &= ~0x03;
232 l |= data_type;
233 p->dma_write(l, CSDP, lch);
234
235 if (dma_omap1()) {
236 u16 ccr;
237
238 ccr = p->dma_read(CCR, lch);
239 ccr &= ~(1 << 5);
240 if (sync_mode == OMAP_DMA_SYNC_FRAME)
241 ccr |= 1 << 5;
242 p->dma_write(ccr, CCR, lch);
243
244 ccr = p->dma_read(CCR2, lch);
245 ccr &= ~(1 << 2);
246 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
247 ccr |= 1 << 2;
248 p->dma_write(ccr, CCR2, lch);
249 }
250
251 if (dma_omap2plus() && dma_trigger) {
252 u32 val;
253
254 val = p->dma_read(CCR, lch);
255
256 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
257 val &= ~((1 << 23) | (3 << 19) | 0x1f);
258 val |= (dma_trigger & ~0x1f) << 14;
259 val |= dma_trigger & 0x1f;
260
261 if (sync_mode & OMAP_DMA_SYNC_FRAME)
262 val |= 1 << 5;
263 else
264 val &= ~(1 << 5);
265
266 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
267 val |= 1 << 18;
268 else
269 val &= ~(1 << 18);
270
271 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
272 val &= ~(1 << 24); /* dest synch */
273 val |= (1 << 23); /* Prefetch */
274 } else if (src_or_dst_synch) {
275 val |= 1 << 24; /* source synch */
276 } else {
277 val &= ~(1 << 24); /* dest synch */
278 }
279 p->dma_write(val, CCR, lch);
280 }
281
282 p->dma_write(elem_count, CEN, lch);
283 p->dma_write(frame_count, CFN, lch);
284 }
285 EXPORT_SYMBOL(omap_set_dma_transfer_params);
286
287 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
288 {
289 BUG_ON(omap_dma_in_1510_mode());
290
291 if (dma_omap1()) {
292 u16 w;
293
294 w = p->dma_read(CCR2, lch);
295 w &= ~0x03;
296
297 switch (mode) {
298 case OMAP_DMA_CONSTANT_FILL:
299 w |= 0x01;
300 break;
301 case OMAP_DMA_TRANSPARENT_COPY:
302 w |= 0x02;
303 break;
304 case OMAP_DMA_COLOR_DIS:
305 break;
306 default:
307 BUG();
308 }
309 p->dma_write(w, CCR2, lch);
310
311 w = p->dma_read(LCH_CTRL, lch);
312 w &= ~0x0f;
313 /* Default is channel type 2D */
314 if (mode) {
315 p->dma_write(color, COLOR, lch);
316 w |= 1; /* Channel type G */
317 }
318 p->dma_write(w, LCH_CTRL, lch);
319 }
320
321 if (dma_omap2plus()) {
322 u32 val;
323
324 val = p->dma_read(CCR, lch);
325 val &= ~((1 << 17) | (1 << 16));
326
327 switch (mode) {
328 case OMAP_DMA_CONSTANT_FILL:
329 val |= 1 << 16;
330 break;
331 case OMAP_DMA_TRANSPARENT_COPY:
332 val |= 1 << 17;
333 break;
334 case OMAP_DMA_COLOR_DIS:
335 break;
336 default:
337 BUG();
338 }
339 p->dma_write(val, CCR, lch);
340
341 color &= 0xffffff;
342 p->dma_write(color, COLOR, lch);
343 }
344 }
345 EXPORT_SYMBOL(omap_set_dma_color_mode);
346
347 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
348 {
349 if (dma_omap2plus()) {
350 u32 csdp;
351
352 csdp = p->dma_read(CSDP, lch);
353 csdp &= ~(0x3 << 16);
354 csdp |= (mode << 16);
355 p->dma_write(csdp, CSDP, lch);
356 }
357 }
358 EXPORT_SYMBOL(omap_set_dma_write_mode);
359
360 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
361 {
362 if (dma_omap1() && !dma_omap15xx()) {
363 u32 l;
364
365 l = p->dma_read(LCH_CTRL, lch);
366 l &= ~0x7;
367 l |= mode;
368 p->dma_write(l, LCH_CTRL, lch);
369 }
370 }
371 EXPORT_SYMBOL(omap_set_dma_channel_mode);
372
373 /* Note that src_port is only for omap1 */
374 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
375 unsigned long src_start,
376 int src_ei, int src_fi)
377 {
378 u32 l;
379
380 if (dma_omap1()) {
381 u16 w;
382
383 w = p->dma_read(CSDP, lch);
384 w &= ~(0x1f << 2);
385 w |= src_port << 2;
386 p->dma_write(w, CSDP, lch);
387 }
388
389 l = p->dma_read(CCR, lch);
390 l &= ~(0x03 << 12);
391 l |= src_amode << 12;
392 p->dma_write(l, CCR, lch);
393
394 p->dma_write(src_start, CSSA, lch);
395
396 p->dma_write(src_ei, CSEI, lch);
397 p->dma_write(src_fi, CSFI, lch);
398 }
399 EXPORT_SYMBOL(omap_set_dma_src_params);
400
401 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
402 {
403 omap_set_dma_transfer_params(lch, params->data_type,
404 params->elem_count, params->frame_count,
405 params->sync_mode, params->trigger,
406 params->src_or_dst_synch);
407 omap_set_dma_src_params(lch, params->src_port,
408 params->src_amode, params->src_start,
409 params->src_ei, params->src_fi);
410
411 omap_set_dma_dest_params(lch, params->dst_port,
412 params->dst_amode, params->dst_start,
413 params->dst_ei, params->dst_fi);
414 if (params->read_prio || params->write_prio)
415 omap_dma_set_prio_lch(lch, params->read_prio,
416 params->write_prio);
417 }
418 EXPORT_SYMBOL(omap_set_dma_params);
419
420 void omap_set_dma_src_index(int lch, int eidx, int fidx)
421 {
422 if (dma_omap2plus())
423 return;
424
425 p->dma_write(eidx, CSEI, lch);
426 p->dma_write(fidx, CSFI, lch);
427 }
428 EXPORT_SYMBOL(omap_set_dma_src_index);
429
430 void omap_set_dma_src_data_pack(int lch, int enable)
431 {
432 u32 l;
433
434 l = p->dma_read(CSDP, lch);
435 l &= ~(1 << 6);
436 if (enable)
437 l |= (1 << 6);
438 p->dma_write(l, CSDP, lch);
439 }
440 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
441
442 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
443 {
444 unsigned int burst = 0;
445 u32 l;
446
447 l = p->dma_read(CSDP, lch);
448 l &= ~(0x03 << 7);
449
450 switch (burst_mode) {
451 case OMAP_DMA_DATA_BURST_DIS:
452 break;
453 case OMAP_DMA_DATA_BURST_4:
454 if (dma_omap2plus())
455 burst = 0x1;
456 else
457 burst = 0x2;
458 break;
459 case OMAP_DMA_DATA_BURST_8:
460 if (dma_omap2plus()) {
461 burst = 0x2;
462 break;
463 }
464 /*
465 * not supported by current hardware on OMAP1
466 * w |= (0x03 << 7);
467 * fall through
468 */
469 case OMAP_DMA_DATA_BURST_16:
470 if (dma_omap2plus()) {
471 burst = 0x3;
472 break;
473 }
474 /*
475 * OMAP1 don't support burst 16
476 * fall through
477 */
478 default:
479 BUG();
480 }
481
482 l |= (burst << 7);
483 p->dma_write(l, CSDP, lch);
484 }
485 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
486
487 /* Note that dest_port is only for OMAP1 */
488 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
489 unsigned long dest_start,
490 int dst_ei, int dst_fi)
491 {
492 u32 l;
493
494 if (dma_omap1()) {
495 l = p->dma_read(CSDP, lch);
496 l &= ~(0x1f << 9);
497 l |= dest_port << 9;
498 p->dma_write(l, CSDP, lch);
499 }
500
501 l = p->dma_read(CCR, lch);
502 l &= ~(0x03 << 14);
503 l |= dest_amode << 14;
504 p->dma_write(l, CCR, lch);
505
506 p->dma_write(dest_start, CDSA, lch);
507
508 p->dma_write(dst_ei, CDEI, lch);
509 p->dma_write(dst_fi, CDFI, lch);
510 }
511 EXPORT_SYMBOL(omap_set_dma_dest_params);
512
513 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
514 {
515 if (dma_omap2plus())
516 return;
517
518 p->dma_write(eidx, CDEI, lch);
519 p->dma_write(fidx, CDFI, lch);
520 }
521 EXPORT_SYMBOL(omap_set_dma_dest_index);
522
523 void omap_set_dma_dest_data_pack(int lch, int enable)
524 {
525 u32 l;
526
527 l = p->dma_read(CSDP, lch);
528 l &= ~(1 << 13);
529 if (enable)
530 l |= 1 << 13;
531 p->dma_write(l, CSDP, lch);
532 }
533 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
534
535 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
536 {
537 unsigned int burst = 0;
538 u32 l;
539
540 l = p->dma_read(CSDP, lch);
541 l &= ~(0x03 << 14);
542
543 switch (burst_mode) {
544 case OMAP_DMA_DATA_BURST_DIS:
545 break;
546 case OMAP_DMA_DATA_BURST_4:
547 if (dma_omap2plus())
548 burst = 0x1;
549 else
550 burst = 0x2;
551 break;
552 case OMAP_DMA_DATA_BURST_8:
553 if (dma_omap2plus())
554 burst = 0x2;
555 else
556 burst = 0x3;
557 break;
558 case OMAP_DMA_DATA_BURST_16:
559 if (dma_omap2plus()) {
560 burst = 0x3;
561 break;
562 }
563 /*
564 * OMAP1 don't support burst 16
565 * fall through
566 */
567 default:
568 printk(KERN_ERR "Invalid DMA burst mode\n");
569 BUG();
570 return;
571 }
572 l |= (burst << 14);
573 p->dma_write(l, CSDP, lch);
574 }
575 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
576
577 static inline void omap_enable_channel_irq(int lch)
578 {
579 /* Clear CSR */
580 if (dma_omap1())
581 p->dma_read(CSR, lch);
582 else
583 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
584
585 /* Enable some nice interrupts. */
586 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
587 }
588
589 static inline void omap_disable_channel_irq(int lch)
590 {
591 /* disable channel interrupts */
592 p->dma_write(0, CICR, lch);
593 /* Clear CSR */
594 if (dma_omap1())
595 p->dma_read(CSR, lch);
596 else
597 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
598 }
599
600 void omap_enable_dma_irq(int lch, u16 bits)
601 {
602 dma_chan[lch].enabled_irqs |= bits;
603 }
604 EXPORT_SYMBOL(omap_enable_dma_irq);
605
606 void omap_disable_dma_irq(int lch, u16 bits)
607 {
608 dma_chan[lch].enabled_irqs &= ~bits;
609 }
610 EXPORT_SYMBOL(omap_disable_dma_irq);
611
612 static inline void enable_lnk(int lch)
613 {
614 u32 l;
615
616 l = p->dma_read(CLNK_CTRL, lch);
617
618 if (dma_omap1())
619 l &= ~(1 << 14);
620
621 /* Set the ENABLE_LNK bits */
622 if (dma_chan[lch].next_lch != -1)
623 l = dma_chan[lch].next_lch | (1 << 15);
624
625 #ifndef CONFIG_ARCH_OMAP1
626 if (dma_omap2plus())
627 if (dma_chan[lch].next_linked_ch != -1)
628 l = dma_chan[lch].next_linked_ch | (1 << 15);
629 #endif
630
631 p->dma_write(l, CLNK_CTRL, lch);
632 }
633
634 static inline void disable_lnk(int lch)
635 {
636 u32 l;
637
638 l = p->dma_read(CLNK_CTRL, lch);
639
640 /* Disable interrupts */
641 omap_disable_channel_irq(lch);
642
643 if (dma_omap1()) {
644 /* Set the STOP_LNK bit */
645 l |= 1 << 14;
646 }
647
648 if (dma_omap2plus()) {
649 /* Clear the ENABLE_LNK bit */
650 l &= ~(1 << 15);
651 }
652
653 p->dma_write(l, CLNK_CTRL, lch);
654 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
655 }
656
657 static inline void omap2_enable_irq_lch(int lch)
658 {
659 u32 val;
660 unsigned long flags;
661
662 if (dma_omap1())
663 return;
664
665 spin_lock_irqsave(&dma_chan_lock, flags);
666 /* clear IRQ STATUS */
667 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
668 /* Enable interrupt */
669 val = p->dma_read(IRQENABLE_L0, lch);
670 val |= 1 << lch;
671 p->dma_write(val, IRQENABLE_L0, lch);
672 spin_unlock_irqrestore(&dma_chan_lock, flags);
673 }
674
675 static inline void omap2_disable_irq_lch(int lch)
676 {
677 u32 val;
678 unsigned long flags;
679
680 if (dma_omap1())
681 return;
682
683 spin_lock_irqsave(&dma_chan_lock, flags);
684 /* Disable interrupt */
685 val = p->dma_read(IRQENABLE_L0, lch);
686 val &= ~(1 << lch);
687 p->dma_write(val, IRQENABLE_L0, lch);
688 /* clear IRQ STATUS */
689 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
690 spin_unlock_irqrestore(&dma_chan_lock, flags);
691 }
692
693 int omap_request_dma(int dev_id, const char *dev_name,
694 void (*callback)(int lch, u16 ch_status, void *data),
695 void *data, int *dma_ch_out)
696 {
697 int ch, free_ch = -1;
698 unsigned long flags;
699 struct omap_dma_lch *chan;
700
701 spin_lock_irqsave(&dma_chan_lock, flags);
702 for (ch = 0; ch < dma_chan_count; ch++) {
703 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
704 free_ch = ch;
705 /* Exit after first free channel found */
706 break;
707 }
708 }
709 if (free_ch == -1) {
710 spin_unlock_irqrestore(&dma_chan_lock, flags);
711 return -EBUSY;
712 }
713 chan = dma_chan + free_ch;
714 chan->dev_id = dev_id;
715
716 if (p->clear_lch_regs)
717 p->clear_lch_regs(free_ch);
718
719 if (dma_omap2plus())
720 omap_clear_dma(free_ch);
721
722 spin_unlock_irqrestore(&dma_chan_lock, flags);
723
724 chan->dev_name = dev_name;
725 chan->callback = callback;
726 chan->data = data;
727 chan->flags = 0;
728
729 #ifndef CONFIG_ARCH_OMAP1
730 if (dma_omap2plus()) {
731 chan->chain_id = -1;
732 chan->next_linked_ch = -1;
733 }
734 #endif
735
736 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
737
738 if (dma_omap1())
739 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
740 else if (dma_omap2plus())
741 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
742 OMAP2_DMA_TRANS_ERR_IRQ;
743
744 if (dma_omap16xx()) {
745 /* If the sync device is set, configure it dynamically. */
746 if (dev_id != 0) {
747 set_gdma_dev(free_ch + 1, dev_id);
748 dev_id = free_ch + 1;
749 }
750 /*
751 * Disable the 1510 compatibility mode and set the sync device
752 * id.
753 */
754 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
755 } else if (dma_omap1()) {
756 p->dma_write(dev_id, CCR, free_ch);
757 }
758
759 if (dma_omap2plus()) {
760 omap_enable_channel_irq(free_ch);
761 omap2_enable_irq_lch(free_ch);
762 }
763
764 *dma_ch_out = free_ch;
765
766 return 0;
767 }
768 EXPORT_SYMBOL(omap_request_dma);
769
770 void omap_free_dma(int lch)
771 {
772 unsigned long flags;
773
774 if (dma_chan[lch].dev_id == -1) {
775 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
776 lch);
777 return;
778 }
779
780 /* Disable interrupt for logical channel */
781 if (dma_omap2plus())
782 omap2_disable_irq_lch(lch);
783
784 /* Disable all DMA interrupts for the channel. */
785 omap_disable_channel_irq(lch);
786
787 /* Make sure the DMA transfer is stopped. */
788 p->dma_write(0, CCR, lch);
789
790 /* Clear registers */
791 if (dma_omap2plus())
792 omap_clear_dma(lch);
793
794 spin_lock_irqsave(&dma_chan_lock, flags);
795 dma_chan[lch].dev_id = -1;
796 dma_chan[lch].next_lch = -1;
797 dma_chan[lch].callback = NULL;
798 spin_unlock_irqrestore(&dma_chan_lock, flags);
799 }
800 EXPORT_SYMBOL(omap_free_dma);
801
802 /**
803 * @brief omap_dma_set_global_params : Set global priority settings for dma
804 *
805 * @param arb_rate
806 * @param max_fifo_depth
807 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
808 * DMA_THREAD_RESERVE_ONET
809 * DMA_THREAD_RESERVE_TWOT
810 * DMA_THREAD_RESERVE_THREET
811 */
812 void
813 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
814 {
815 u32 reg;
816
817 if (dma_omap1()) {
818 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
819 return;
820 }
821
822 if (max_fifo_depth == 0)
823 max_fifo_depth = 1;
824 if (arb_rate == 0)
825 arb_rate = 1;
826
827 reg = 0xff & max_fifo_depth;
828 reg |= (0x3 & tparams) << 12;
829 reg |= (arb_rate & 0xff) << 16;
830
831 p->dma_write(reg, GCR, 0);
832 }
833 EXPORT_SYMBOL(omap_dma_set_global_params);
834
835 /**
836 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
837 *
838 * @param lch
839 * @param read_prio - Read priority
840 * @param write_prio - Write priority
841 * Both of the above can be set with one of the following values :
842 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
843 */
844 int
845 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
846 unsigned char write_prio)
847 {
848 u32 l;
849
850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
851 printk(KERN_ERR "Invalid channel id\n");
852 return -EINVAL;
853 }
854 l = p->dma_read(CCR, lch);
855 l &= ~((1 << 6) | (1 << 26));
856 if (d->dev_caps & IS_RW_PRIORITY)
857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
858 else
859 l |= ((read_prio & 0x1) << 6);
860
861 p->dma_write(l, CCR, lch);
862
863 return 0;
864 }
865 EXPORT_SYMBOL(omap_dma_set_prio_lch);
866
867 /*
868 * Clears any DMA state so the DMA engine is ready to restart with new buffers
869 * through omap_start_dma(). Any buffers in flight are discarded.
870 */
871 void omap_clear_dma(int lch)
872 {
873 unsigned long flags;
874
875 local_irq_save(flags);
876 p->clear_dma(lch);
877 local_irq_restore(flags);
878 }
879 EXPORT_SYMBOL(omap_clear_dma);
880
881 void omap_start_dma(int lch)
882 {
883 u32 l;
884
885 /*
886 * The CPC/CDAC register needs to be initialized to zero
887 * before starting dma transfer.
888 */
889 if (dma_omap15xx())
890 p->dma_write(0, CPC, lch);
891 else
892 p->dma_write(0, CDAC, lch);
893
894 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
895 int next_lch, cur_lch;
896 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
897
898 /* Set the link register of the first channel */
899 enable_lnk(lch);
900
901 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
902 dma_chan_link_map[lch] = 1;
903
904 cur_lch = dma_chan[lch].next_lch;
905 do {
906 next_lch = dma_chan[cur_lch].next_lch;
907
908 /* The loop case: we've been here already */
909 if (dma_chan_link_map[cur_lch])
910 break;
911 /* Mark the current channel */
912 dma_chan_link_map[cur_lch] = 1;
913
914 enable_lnk(cur_lch);
915 omap_enable_channel_irq(cur_lch);
916
917 cur_lch = next_lch;
918 } while (next_lch != -1);
919 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
920 p->dma_write(lch, CLNK_CTRL, lch);
921
922 omap_enable_channel_irq(lch);
923
924 l = p->dma_read(CCR, lch);
925
926 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
927 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
928 l |= OMAP_DMA_CCR_EN;
929
930 /*
931 * As dma_write() uses IO accessors which are weakly ordered, there
932 * is no guarantee that data in coherent DMA memory will be visible
933 * to the DMA device. Add a memory barrier here to ensure that any
934 * such data is visible prior to enabling DMA.
935 */
936 mb();
937 p->dma_write(l, CCR, lch);
938
939 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
940 }
941 EXPORT_SYMBOL(omap_start_dma);
942
943 void omap_stop_dma(int lch)
944 {
945 u32 l;
946
947 /* Disable all interrupts on the channel */
948 omap_disable_channel_irq(lch);
949
950 l = p->dma_read(CCR, lch);
951 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
952 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
953 int i = 0;
954 u32 sys_cf;
955
956 /* Configure No-Standby */
957 l = p->dma_read(OCP_SYSCONFIG, lch);
958 sys_cf = l;
959 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
960 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
961 p->dma_write(l , OCP_SYSCONFIG, 0);
962
963 l = p->dma_read(CCR, lch);
964 l &= ~OMAP_DMA_CCR_EN;
965 p->dma_write(l, CCR, lch);
966
967 /* Wait for sDMA FIFO drain */
968 l = p->dma_read(CCR, lch);
969 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
970 OMAP_DMA_CCR_WR_ACTIVE))) {
971 udelay(5);
972 i++;
973 l = p->dma_read(CCR, lch);
974 }
975 if (i >= 100)
976 pr_err("DMA drain did not complete on lch %d\n", lch);
977 /* Restore OCP_SYSCONFIG */
978 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
979 } else {
980 l &= ~OMAP_DMA_CCR_EN;
981 p->dma_write(l, CCR, lch);
982 }
983
984 /*
985 * Ensure that data transferred by DMA is visible to any access
986 * after DMA has been disabled. This is important for coherent
987 * DMA regions.
988 */
989 mb();
990
991 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
992 int next_lch, cur_lch = lch;
993 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
994
995 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
996 do {
997 /* The loop case: we've been here already */
998 if (dma_chan_link_map[cur_lch])
999 break;
1000 /* Mark the current channel */
1001 dma_chan_link_map[cur_lch] = 1;
1002
1003 disable_lnk(cur_lch);
1004
1005 next_lch = dma_chan[cur_lch].next_lch;
1006 cur_lch = next_lch;
1007 } while (next_lch != -1);
1008 }
1009
1010 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1011 }
1012 EXPORT_SYMBOL(omap_stop_dma);
1013
1014 /*
1015 * Allows changing the DMA callback function or data. This may be needed if
1016 * the driver shares a single DMA channel for multiple dma triggers.
1017 */
1018 int omap_set_dma_callback(int lch,
1019 void (*callback)(int lch, u16 ch_status, void *data),
1020 void *data)
1021 {
1022 unsigned long flags;
1023
1024 if (lch < 0)
1025 return -ENODEV;
1026
1027 spin_lock_irqsave(&dma_chan_lock, flags);
1028 if (dma_chan[lch].dev_id == -1) {
1029 printk(KERN_ERR "DMA callback for not set for free channel\n");
1030 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031 return -EINVAL;
1032 }
1033 dma_chan[lch].callback = callback;
1034 dma_chan[lch].data = data;
1035 spin_unlock_irqrestore(&dma_chan_lock, flags);
1036
1037 return 0;
1038 }
1039 EXPORT_SYMBOL(omap_set_dma_callback);
1040
1041 /*
1042 * Returns current physical source address for the given DMA channel.
1043 * If the channel is running the caller must disable interrupts prior calling
1044 * this function and process the returned value before re-enabling interrupt to
1045 * prevent races with the interrupt handler. Note that in continuous mode there
1046 * is a chance for CSSA_L register overflow between the two reads resulting
1047 * in incorrect return value.
1048 */
1049 dma_addr_t omap_get_dma_src_pos(int lch)
1050 {
1051 dma_addr_t offset = 0;
1052
1053 if (dma_omap15xx())
1054 offset = p->dma_read(CPC, lch);
1055 else
1056 offset = p->dma_read(CSAC, lch);
1057
1058 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1059 offset = p->dma_read(CSAC, lch);
1060
1061 if (!dma_omap15xx()) {
1062 /*
1063 * CDAC == 0 indicates that the DMA transfer on the channel has
1064 * not been started (no data has been transferred so far).
1065 * Return the programmed source start address in this case.
1066 */
1067 if (likely(p->dma_read(CDAC, lch)))
1068 offset = p->dma_read(CSAC, lch);
1069 else
1070 offset = p->dma_read(CSSA, lch);
1071 }
1072
1073 if (dma_omap1())
1074 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1075
1076 return offset;
1077 }
1078 EXPORT_SYMBOL(omap_get_dma_src_pos);
1079
1080 /*
1081 * Returns current physical destination address for the given DMA channel.
1082 * If the channel is running the caller must disable interrupts prior calling
1083 * this function and process the returned value before re-enabling interrupt to
1084 * prevent races with the interrupt handler. Note that in continuous mode there
1085 * is a chance for CDSA_L register overflow between the two reads resulting
1086 * in incorrect return value.
1087 */
1088 dma_addr_t omap_get_dma_dst_pos(int lch)
1089 {
1090 dma_addr_t offset = 0;
1091
1092 if (dma_omap15xx())
1093 offset = p->dma_read(CPC, lch);
1094 else
1095 offset = p->dma_read(CDAC, lch);
1096
1097 /*
1098 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1099 * read before the DMA controller finished disabling the channel.
1100 */
1101 if (!dma_omap15xx() && offset == 0) {
1102 offset = p->dma_read(CDAC, lch);
1103 /*
1104 * CDAC == 0 indicates that the DMA transfer on the channel has
1105 * not been started (no data has been transferred so far).
1106 * Return the programmed destination start address in this case.
1107 */
1108 if (unlikely(!offset))
1109 offset = p->dma_read(CDSA, lch);
1110 }
1111
1112 if (dma_omap1())
1113 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1114
1115 return offset;
1116 }
1117 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1118
1119 int omap_get_dma_active_status(int lch)
1120 {
1121 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1122 }
1123 EXPORT_SYMBOL(omap_get_dma_active_status);
1124
1125 int omap_dma_running(void)
1126 {
1127 int lch;
1128
1129 if (dma_omap1())
1130 if (omap_lcd_dma_running())
1131 return 1;
1132
1133 for (lch = 0; lch < dma_chan_count; lch++)
1134 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1135 return 1;
1136
1137 return 0;
1138 }
1139
1140 /*
1141 * lch_queue DMA will start right after lch_head one is finished.
1142 * For this DMA link to start, you still need to start (see omap_start_dma)
1143 * the first one. That will fire up the entire queue.
1144 */
1145 void omap_dma_link_lch(int lch_head, int lch_queue)
1146 {
1147 if (omap_dma_in_1510_mode()) {
1148 if (lch_head == lch_queue) {
1149 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1150 CCR, lch_head);
1151 return;
1152 }
1153 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1154 BUG();
1155 return;
1156 }
1157
1158 if ((dma_chan[lch_head].dev_id == -1) ||
1159 (dma_chan[lch_queue].dev_id == -1)) {
1160 pr_err("omap_dma: trying to link non requested channels\n");
1161 dump_stack();
1162 }
1163
1164 dma_chan[lch_head].next_lch = lch_queue;
1165 }
1166 EXPORT_SYMBOL(omap_dma_link_lch);
1167
1168 /*
1169 * Once the DMA queue is stopped, we can destroy it.
1170 */
1171 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1172 {
1173 if (omap_dma_in_1510_mode()) {
1174 if (lch_head == lch_queue) {
1175 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1176 CCR, lch_head);
1177 return;
1178 }
1179 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1180 BUG();
1181 return;
1182 }
1183
1184 if (dma_chan[lch_head].next_lch != lch_queue ||
1185 dma_chan[lch_head].next_lch == -1) {
1186 pr_err("omap_dma: trying to unlink non linked channels\n");
1187 dump_stack();
1188 }
1189
1190 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1191 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1192 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1193 dump_stack();
1194 }
1195
1196 dma_chan[lch_head].next_lch = -1;
1197 }
1198 EXPORT_SYMBOL(omap_dma_unlink_lch);
1199
1200 #ifndef CONFIG_ARCH_OMAP1
1201 /* Create chain of DMA channesls */
1202 static void create_dma_lch_chain(int lch_head, int lch_queue)
1203 {
1204 u32 l;
1205
1206 /* Check if this is the first link in chain */
1207 if (dma_chan[lch_head].next_linked_ch == -1) {
1208 dma_chan[lch_head].next_linked_ch = lch_queue;
1209 dma_chan[lch_head].prev_linked_ch = lch_queue;
1210 dma_chan[lch_queue].next_linked_ch = lch_head;
1211 dma_chan[lch_queue].prev_linked_ch = lch_head;
1212 }
1213
1214 /* a link exists, link the new channel in circular chain */
1215 else {
1216 dma_chan[lch_queue].next_linked_ch =
1217 dma_chan[lch_head].next_linked_ch;
1218 dma_chan[lch_queue].prev_linked_ch = lch_head;
1219 dma_chan[lch_head].next_linked_ch = lch_queue;
1220 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1221 lch_queue;
1222 }
1223
1224 l = p->dma_read(CLNK_CTRL, lch_head);
1225 l &= ~(0x1f);
1226 l |= lch_queue;
1227 p->dma_write(l, CLNK_CTRL, lch_head);
1228
1229 l = p->dma_read(CLNK_CTRL, lch_queue);
1230 l &= ~(0x1f);
1231 l |= (dma_chan[lch_queue].next_linked_ch);
1232 p->dma_write(l, CLNK_CTRL, lch_queue);
1233 }
1234
1235 /**
1236 * @brief omap_request_dma_chain : Request a chain of DMA channels
1237 *
1238 * @param dev_id - Device id using the dma channel
1239 * @param dev_name - Device name
1240 * @param callback - Call back function
1241 * @chain_id -
1242 * @no_of_chans - Number of channels requested
1243 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1244 * OMAP_DMA_DYNAMIC_CHAIN
1245 * @params - Channel parameters
1246 *
1247 * @return - Success : 0
1248 * Failure: -EINVAL/-ENOMEM
1249 */
1250 int omap_request_dma_chain(int dev_id, const char *dev_name,
1251 void (*callback) (int lch, u16 ch_status,
1252 void *data),
1253 int *chain_id, int no_of_chans, int chain_mode,
1254 struct omap_dma_channel_params params)
1255 {
1256 int *channels;
1257 int i, err;
1258
1259 /* Is the chain mode valid ? */
1260 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1261 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1262 printk(KERN_ERR "Invalid chain mode requested\n");
1263 return -EINVAL;
1264 }
1265
1266 if (unlikely((no_of_chans < 1
1267 || no_of_chans > dma_lch_count))) {
1268 printk(KERN_ERR "Invalid Number of channels requested\n");
1269 return -EINVAL;
1270 }
1271
1272 /*
1273 * Allocate a queue to maintain the status of the channels
1274 * in the chain
1275 */
1276 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1277 if (channels == NULL) {
1278 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1279 return -ENOMEM;
1280 }
1281
1282 /* request and reserve DMA channels for the chain */
1283 for (i = 0; i < no_of_chans; i++) {
1284 err = omap_request_dma(dev_id, dev_name,
1285 callback, NULL, &channels[i]);
1286 if (err < 0) {
1287 int j;
1288 for (j = 0; j < i; j++)
1289 omap_free_dma(channels[j]);
1290 kfree(channels);
1291 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1292 return err;
1293 }
1294 dma_chan[channels[i]].prev_linked_ch = -1;
1295 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1296
1297 /*
1298 * Allowing client drivers to set common parameters now,
1299 * so that later only relevant (src_start, dest_start
1300 * and element count) can be set
1301 */
1302 omap_set_dma_params(channels[i], &params);
1303 }
1304
1305 *chain_id = channels[0];
1306 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1307 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1308 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1309 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1310
1311 for (i = 0; i < no_of_chans; i++)
1312 dma_chan[channels[i]].chain_id = *chain_id;
1313
1314 /* Reset the Queue pointers */
1315 OMAP_DMA_CHAIN_QINIT(*chain_id);
1316
1317 /* Set up the chain */
1318 if (no_of_chans == 1)
1319 create_dma_lch_chain(channels[0], channels[0]);
1320 else {
1321 for (i = 0; i < (no_of_chans - 1); i++)
1322 create_dma_lch_chain(channels[i], channels[i + 1]);
1323 }
1324
1325 return 0;
1326 }
1327 EXPORT_SYMBOL(omap_request_dma_chain);
1328
1329 /**
1330 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1331 * params after setting it. Dont do this while dma is running!!
1332 *
1333 * @param chain_id - Chained logical channel id.
1334 * @param params
1335 *
1336 * @return - Success : 0
1337 * Failure : -EINVAL
1338 */
1339 int omap_modify_dma_chain_params(int chain_id,
1340 struct omap_dma_channel_params params)
1341 {
1342 int *channels;
1343 u32 i;
1344
1345 /* Check for input params */
1346 if (unlikely((chain_id < 0
1347 || chain_id >= dma_lch_count))) {
1348 printk(KERN_ERR "Invalid chain id\n");
1349 return -EINVAL;
1350 }
1351
1352 /* Check if the chain exists */
1353 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1354 printk(KERN_ERR "Chain doesn't exists\n");
1355 return -EINVAL;
1356 }
1357 channels = dma_linked_lch[chain_id].linked_dmach_q;
1358
1359 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1360 /*
1361 * Allowing client drivers to set common parameters now,
1362 * so that later only relevant (src_start, dest_start
1363 * and element count) can be set
1364 */
1365 omap_set_dma_params(channels[i], &params);
1366 }
1367
1368 return 0;
1369 }
1370 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1371
1372 /**
1373 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1374 *
1375 * @param chain_id
1376 *
1377 * @return - Success : 0
1378 * Failure : -EINVAL
1379 */
1380 int omap_free_dma_chain(int chain_id)
1381 {
1382 int *channels;
1383 u32 i;
1384
1385 /* Check for input params */
1386 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1387 printk(KERN_ERR "Invalid chain id\n");
1388 return -EINVAL;
1389 }
1390
1391 /* Check if the chain exists */
1392 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1393 printk(KERN_ERR "Chain doesn't exists\n");
1394 return -EINVAL;
1395 }
1396
1397 channels = dma_linked_lch[chain_id].linked_dmach_q;
1398 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1399 dma_chan[channels[i]].next_linked_ch = -1;
1400 dma_chan[channels[i]].prev_linked_ch = -1;
1401 dma_chan[channels[i]].chain_id = -1;
1402 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1403 omap_free_dma(channels[i]);
1404 }
1405
1406 kfree(channels);
1407
1408 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1409 dma_linked_lch[chain_id].chain_mode = -1;
1410 dma_linked_lch[chain_id].chain_state = -1;
1411
1412 return (0);
1413 }
1414 EXPORT_SYMBOL(omap_free_dma_chain);
1415
1416 /**
1417 * @brief omap_dma_chain_status - Check if the chain is in
1418 * active / inactive state.
1419 * @param chain_id
1420 *
1421 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1422 * Failure : -EINVAL
1423 */
1424 int omap_dma_chain_status(int chain_id)
1425 {
1426 /* Check for input params */
1427 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1428 printk(KERN_ERR "Invalid chain id\n");
1429 return -EINVAL;
1430 }
1431
1432 /* Check if the chain exists */
1433 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1434 printk(KERN_ERR "Chain doesn't exists\n");
1435 return -EINVAL;
1436 }
1437 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1438 dma_linked_lch[chain_id].q_count);
1439
1440 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1441 return OMAP_DMA_CHAIN_INACTIVE;
1442
1443 return OMAP_DMA_CHAIN_ACTIVE;
1444 }
1445 EXPORT_SYMBOL(omap_dma_chain_status);
1446
1447 /**
1448 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1449 * set the params and start the transfer.
1450 *
1451 * @param chain_id
1452 * @param src_start - buffer start address
1453 * @param dest_start - Dest address
1454 * @param elem_count
1455 * @param frame_count
1456 * @param callbk_data - channel callback parameter data.
1457 *
1458 * @return - Success : 0
1459 * Failure: -EINVAL/-EBUSY
1460 */
1461 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1462 int elem_count, int frame_count, void *callbk_data)
1463 {
1464 int *channels;
1465 u32 l, lch;
1466 int start_dma = 0;
1467
1468 /*
1469 * if buffer size is less than 1 then there is
1470 * no use of starting the chain
1471 */
1472 if (elem_count < 1) {
1473 printk(KERN_ERR "Invalid buffer size\n");
1474 return -EINVAL;
1475 }
1476
1477 /* Check for input params */
1478 if (unlikely((chain_id < 0
1479 || chain_id >= dma_lch_count))) {
1480 printk(KERN_ERR "Invalid chain id\n");
1481 return -EINVAL;
1482 }
1483
1484 /* Check if the chain exists */
1485 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1486 printk(KERN_ERR "Chain doesn't exist\n");
1487 return -EINVAL;
1488 }
1489
1490 /* Check if all the channels in chain are in use */
1491 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1492 return -EBUSY;
1493
1494 /* Frame count may be negative in case of indexed transfers */
1495 channels = dma_linked_lch[chain_id].linked_dmach_q;
1496
1497 /* Get a free channel */
1498 lch = channels[dma_linked_lch[chain_id].q_tail];
1499
1500 /* Store the callback data */
1501 dma_chan[lch].data = callbk_data;
1502
1503 /* Increment the q_tail */
1504 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1505
1506 /* Set the params to the free channel */
1507 if (src_start != 0)
1508 p->dma_write(src_start, CSSA, lch);
1509 if (dest_start != 0)
1510 p->dma_write(dest_start, CDSA, lch);
1511
1512 /* Write the buffer size */
1513 p->dma_write(elem_count, CEN, lch);
1514 p->dma_write(frame_count, CFN, lch);
1515
1516 /*
1517 * If the chain is dynamically linked,
1518 * then we may have to start the chain if its not active
1519 */
1520 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1521
1522 /*
1523 * In Dynamic chain, if the chain is not started,
1524 * queue the channel
1525 */
1526 if (dma_linked_lch[chain_id].chain_state ==
1527 DMA_CHAIN_NOTSTARTED) {
1528 /* Enable the link in previous channel */
1529 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1530 DMA_CH_QUEUED)
1531 enable_lnk(dma_chan[lch].prev_linked_ch);
1532 dma_chan[lch].state = DMA_CH_QUEUED;
1533 }
1534
1535 /*
1536 * Chain is already started, make sure its active,
1537 * if not then start the chain
1538 */
1539 else {
1540 start_dma = 1;
1541
1542 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1543 DMA_CH_STARTED) {
1544 enable_lnk(dma_chan[lch].prev_linked_ch);
1545 dma_chan[lch].state = DMA_CH_QUEUED;
1546 start_dma = 0;
1547 if (0 == ((1 << 7) & p->dma_read(
1548 CCR, dma_chan[lch].prev_linked_ch))) {
1549 disable_lnk(dma_chan[lch].
1550 prev_linked_ch);
1551 pr_debug("\n prev ch is stopped\n");
1552 start_dma = 1;
1553 }
1554 }
1555
1556 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1557 == DMA_CH_QUEUED) {
1558 enable_lnk(dma_chan[lch].prev_linked_ch);
1559 dma_chan[lch].state = DMA_CH_QUEUED;
1560 start_dma = 0;
1561 }
1562 omap_enable_channel_irq(lch);
1563
1564 l = p->dma_read(CCR, lch);
1565
1566 if ((0 == (l & (1 << 24))))
1567 l &= ~(1 << 25);
1568 else
1569 l |= (1 << 25);
1570 if (start_dma == 1) {
1571 if (0 == (l & (1 << 7))) {
1572 l |= (1 << 7);
1573 dma_chan[lch].state = DMA_CH_STARTED;
1574 pr_debug("starting %d\n", lch);
1575 p->dma_write(l, CCR, lch);
1576 } else
1577 start_dma = 0;
1578 } else {
1579 if (0 == (l & (1 << 7)))
1580 p->dma_write(l, CCR, lch);
1581 }
1582 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1583 }
1584 }
1585
1586 return 0;
1587 }
1588 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1589
1590 /**
1591 * @brief omap_start_dma_chain_transfers - Start the chain
1592 *
1593 * @param chain_id
1594 *
1595 * @return - Success : 0
1596 * Failure : -EINVAL/-EBUSY
1597 */
1598 int omap_start_dma_chain_transfers(int chain_id)
1599 {
1600 int *channels;
1601 u32 l, i;
1602
1603 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1604 printk(KERN_ERR "Invalid chain id\n");
1605 return -EINVAL;
1606 }
1607
1608 channels = dma_linked_lch[chain_id].linked_dmach_q;
1609
1610 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1611 printk(KERN_ERR "Chain is already started\n");
1612 return -EBUSY;
1613 }
1614
1615 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1616 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1617 i++) {
1618 enable_lnk(channels[i]);
1619 omap_enable_channel_irq(channels[i]);
1620 }
1621 } else {
1622 omap_enable_channel_irq(channels[0]);
1623 }
1624
1625 l = p->dma_read(CCR, channels[0]);
1626 l |= (1 << 7);
1627 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1628 dma_chan[channels[0]].state = DMA_CH_STARTED;
1629
1630 if ((0 == (l & (1 << 24))))
1631 l &= ~(1 << 25);
1632 else
1633 l |= (1 << 25);
1634 p->dma_write(l, CCR, channels[0]);
1635
1636 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1637
1638 return 0;
1639 }
1640 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1641
1642 /**
1643 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1644 *
1645 * @param chain_id
1646 *
1647 * @return - Success : 0
1648 * Failure : EINVAL
1649 */
1650 int omap_stop_dma_chain_transfers(int chain_id)
1651 {
1652 int *channels;
1653 u32 l, i;
1654 u32 sys_cf = 0;
1655
1656 /* Check for input params */
1657 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1658 printk(KERN_ERR "Invalid chain id\n");
1659 return -EINVAL;
1660 }
1661
1662 /* Check if the chain exists */
1663 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1664 printk(KERN_ERR "Chain doesn't exists\n");
1665 return -EINVAL;
1666 }
1667 channels = dma_linked_lch[chain_id].linked_dmach_q;
1668
1669 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1670 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1671 l = sys_cf;
1672 /* Middle mode reg set no Standby */
1673 l &= ~((1 << 12)|(1 << 13));
1674 p->dma_write(l, OCP_SYSCONFIG, 0);
1675 }
1676
1677 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1678
1679 /* Stop the Channel transmission */
1680 l = p->dma_read(CCR, channels[i]);
1681 l &= ~(1 << 7);
1682 p->dma_write(l, CCR, channels[i]);
1683
1684 /* Disable the link in all the channels */
1685 disable_lnk(channels[i]);
1686 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1687
1688 }
1689 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1690
1691 /* Reset the Queue pointers */
1692 OMAP_DMA_CHAIN_QINIT(chain_id);
1693
1694 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1695 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1696
1697 return 0;
1698 }
1699 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1700
1701 /* Get the index of the ongoing DMA in chain */
1702 /**
1703 * @brief omap_get_dma_chain_index - Get the element and frame index
1704 * of the ongoing DMA in chain
1705 *
1706 * @param chain_id
1707 * @param ei - Element index
1708 * @param fi - Frame index
1709 *
1710 * @return - Success : 0
1711 * Failure : -EINVAL
1712 */
1713 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1714 {
1715 int lch;
1716 int *channels;
1717
1718 /* Check for input params */
1719 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1720 printk(KERN_ERR "Invalid chain id\n");
1721 return -EINVAL;
1722 }
1723
1724 /* Check if the chain exists */
1725 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1726 printk(KERN_ERR "Chain doesn't exists\n");
1727 return -EINVAL;
1728 }
1729 if ((!ei) || (!fi))
1730 return -EINVAL;
1731
1732 channels = dma_linked_lch[chain_id].linked_dmach_q;
1733
1734 /* Get the current channel */
1735 lch = channels[dma_linked_lch[chain_id].q_head];
1736
1737 *ei = p->dma_read(CCEN, lch);
1738 *fi = p->dma_read(CCFN, lch);
1739
1740 return 0;
1741 }
1742 EXPORT_SYMBOL(omap_get_dma_chain_index);
1743
1744 /**
1745 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1746 * ongoing DMA in chain
1747 *
1748 * @param chain_id
1749 *
1750 * @return - Success : Destination position
1751 * Failure : -EINVAL
1752 */
1753 int omap_get_dma_chain_dst_pos(int chain_id)
1754 {
1755 int lch;
1756 int *channels;
1757
1758 /* Check for input params */
1759 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1760 printk(KERN_ERR "Invalid chain id\n");
1761 return -EINVAL;
1762 }
1763
1764 /* Check if the chain exists */
1765 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1766 printk(KERN_ERR "Chain doesn't exists\n");
1767 return -EINVAL;
1768 }
1769
1770 channels = dma_linked_lch[chain_id].linked_dmach_q;
1771
1772 /* Get the current channel */
1773 lch = channels[dma_linked_lch[chain_id].q_head];
1774
1775 return p->dma_read(CDAC, lch);
1776 }
1777 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1778
1779 /**
1780 * @brief omap_get_dma_chain_src_pos - Get the source position
1781 * of the ongoing DMA in chain
1782 * @param chain_id
1783 *
1784 * @return - Success : Destination position
1785 * Failure : -EINVAL
1786 */
1787 int omap_get_dma_chain_src_pos(int chain_id)
1788 {
1789 int lch;
1790 int *channels;
1791
1792 /* Check for input params */
1793 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1794 printk(KERN_ERR "Invalid chain id\n");
1795 return -EINVAL;
1796 }
1797
1798 /* Check if the chain exists */
1799 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1800 printk(KERN_ERR "Chain doesn't exists\n");
1801 return -EINVAL;
1802 }
1803
1804 channels = dma_linked_lch[chain_id].linked_dmach_q;
1805
1806 /* Get the current channel */
1807 lch = channels[dma_linked_lch[chain_id].q_head];
1808
1809 return p->dma_read(CSAC, lch);
1810 }
1811 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1812 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1813
1814 /*----------------------------------------------------------------------------*/
1815
1816 #ifdef CONFIG_ARCH_OMAP1
1817
1818 static int omap1_dma_handle_ch(int ch)
1819 {
1820 u32 csr;
1821
1822 if (enable_1510_mode && ch >= 6) {
1823 csr = dma_chan[ch].saved_csr;
1824 dma_chan[ch].saved_csr = 0;
1825 } else
1826 csr = p->dma_read(CSR, ch);
1827 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1828 dma_chan[ch + 6].saved_csr = csr >> 7;
1829 csr &= 0x7f;
1830 }
1831 if ((csr & 0x3f) == 0)
1832 return 0;
1833 if (unlikely(dma_chan[ch].dev_id == -1)) {
1834 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1835 ch, csr);
1836 return 0;
1837 }
1838 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1839 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1840 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1841 pr_warn("DMA synchronization event drop occurred with device %d\n",
1842 dma_chan[ch].dev_id);
1843 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1844 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1845 if (likely(dma_chan[ch].callback != NULL))
1846 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1847
1848 return 1;
1849 }
1850
1851 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1852 {
1853 int ch = ((int) dev_id) - 1;
1854 int handled = 0;
1855
1856 for (;;) {
1857 int handled_now = 0;
1858
1859 handled_now += omap1_dma_handle_ch(ch);
1860 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1861 handled_now += omap1_dma_handle_ch(ch + 6);
1862 if (!handled_now)
1863 break;
1864 handled += handled_now;
1865 }
1866
1867 return handled ? IRQ_HANDLED : IRQ_NONE;
1868 }
1869
1870 #else
1871 #define omap1_dma_irq_handler NULL
1872 #endif
1873
1874 #ifdef CONFIG_ARCH_OMAP2PLUS
1875
1876 static int omap2_dma_handle_ch(int ch)
1877 {
1878 u32 status = p->dma_read(CSR, ch);
1879
1880 if (!status) {
1881 if (printk_ratelimit())
1882 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1883 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1884 return 0;
1885 }
1886 if (unlikely(dma_chan[ch].dev_id == -1)) {
1887 if (printk_ratelimit())
1888 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1889 status, ch);
1890 return 0;
1891 }
1892 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1893 pr_info("DMA synchronization event drop occurred with device %d\n",
1894 dma_chan[ch].dev_id);
1895 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1896 printk(KERN_INFO "DMA transaction error with device %d\n",
1897 dma_chan[ch].dev_id);
1898 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1899 u32 ccr;
1900
1901 ccr = p->dma_read(CCR, ch);
1902 ccr &= ~OMAP_DMA_CCR_EN;
1903 p->dma_write(ccr, CCR, ch);
1904 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1905 }
1906 }
1907 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1908 printk(KERN_INFO "DMA secure error with device %d\n",
1909 dma_chan[ch].dev_id);
1910 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1911 printk(KERN_INFO "DMA misaligned error with device %d\n",
1912 dma_chan[ch].dev_id);
1913
1914 p->dma_write(status, CSR, ch);
1915 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1916 /* read back the register to flush the write */
1917 p->dma_read(IRQSTATUS_L0, ch);
1918
1919 /* If the ch is not chained then chain_id will be -1 */
1920 if (dma_chan[ch].chain_id != -1) {
1921 int chain_id = dma_chan[ch].chain_id;
1922 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1923 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1924 dma_chan[dma_chan[ch].next_linked_ch].state =
1925 DMA_CH_STARTED;
1926 if (dma_linked_lch[chain_id].chain_mode ==
1927 OMAP_DMA_DYNAMIC_CHAIN)
1928 disable_lnk(ch);
1929
1930 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1931 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1932
1933 status = p->dma_read(CSR, ch);
1934 p->dma_write(status, CSR, ch);
1935 }
1936
1937 if (likely(dma_chan[ch].callback != NULL))
1938 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1939
1940 return 0;
1941 }
1942
1943 /* STATUS register count is from 1-32 while our is 0-31 */
1944 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1945 {
1946 u32 val, enable_reg;
1947 int i;
1948
1949 val = p->dma_read(IRQSTATUS_L0, 0);
1950 if (val == 0) {
1951 if (printk_ratelimit())
1952 printk(KERN_WARNING "Spurious DMA IRQ\n");
1953 return IRQ_HANDLED;
1954 }
1955 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1956 val &= enable_reg; /* Dispatch only relevant interrupts */
1957 for (i = 0; i < dma_lch_count && val != 0; i++) {
1958 if (val & 1)
1959 omap2_dma_handle_ch(i);
1960 val >>= 1;
1961 }
1962
1963 return IRQ_HANDLED;
1964 }
1965
1966 static struct irqaction omap24xx_dma_irq = {
1967 .name = "DMA",
1968 .handler = omap2_dma_irq_handler,
1969 };
1970
1971 #else
1972 static struct irqaction omap24xx_dma_irq;
1973 #endif
1974
1975 /*----------------------------------------------------------------------------*/
1976
1977 /*
1978 * Note that we are currently using only IRQENABLE_L0 and L1.
1979 * As the DSP may be using IRQENABLE_L2 and L3, let's not
1980 * touch those for now.
1981 */
1982 void omap_dma_global_context_save(void)
1983 {
1984 omap_dma_global_context.dma_irqenable_l0 =
1985 p->dma_read(IRQENABLE_L0, 0);
1986 omap_dma_global_context.dma_irqenable_l1 =
1987 p->dma_read(IRQENABLE_L1, 0);
1988 omap_dma_global_context.dma_ocp_sysconfig =
1989 p->dma_read(OCP_SYSCONFIG, 0);
1990 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1991 }
1992
1993 void omap_dma_global_context_restore(void)
1994 {
1995 int ch;
1996
1997 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1998 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1999 OCP_SYSCONFIG, 0);
2000 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
2001 IRQENABLE_L0, 0);
2002 p->dma_write(omap_dma_global_context.dma_irqenable_l1,
2003 IRQENABLE_L1, 0);
2004
2005 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
2006 p->dma_write(0x3 , IRQSTATUS_L0, 0);
2007
2008 for (ch = 0; ch < dma_chan_count; ch++)
2009 if (dma_chan[ch].dev_id != -1)
2010 omap_clear_dma(ch);
2011 }
2012
2013 struct omap_system_dma_plat_info *omap_get_plat_info(void)
2014 {
2015 return p;
2016 }
2017 EXPORT_SYMBOL_GPL(omap_get_plat_info);
2018
2019 static int omap_system_dma_probe(struct platform_device *pdev)
2020 {
2021 int ch, ret = 0;
2022 int dma_irq;
2023 char irq_name[4];
2024 int irq_rel;
2025
2026 p = pdev->dev.platform_data;
2027 if (!p) {
2028 dev_err(&pdev->dev,
2029 "%s: System DMA initialized without platform data\n",
2030 __func__);
2031 return -EINVAL;
2032 }
2033
2034 d = p->dma_attr;
2035 errata = p->errata;
2036
2037 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2038 && (omap_dma_reserve_channels < d->lch_count))
2039 d->lch_count = omap_dma_reserve_channels;
2040
2041 dma_lch_count = d->lch_count;
2042 dma_chan_count = dma_lch_count;
2043 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2044
2045 dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
2046 sizeof(struct omap_dma_lch), GFP_KERNEL);
2047 if (!dma_chan) {
2048 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
2049 return -ENOMEM;
2050 }
2051
2052
2053 if (dma_omap2plus()) {
2054 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2055 dma_lch_count, GFP_KERNEL);
2056 if (!dma_linked_lch) {
2057 ret = -ENOMEM;
2058 goto exit_dma_lch_fail;
2059 }
2060 }
2061
2062 spin_lock_init(&dma_chan_lock);
2063 for (ch = 0; ch < dma_chan_count; ch++) {
2064 omap_clear_dma(ch);
2065 if (dma_omap2plus())
2066 omap2_disable_irq_lch(ch);
2067
2068 dma_chan[ch].dev_id = -1;
2069 dma_chan[ch].next_lch = -1;
2070
2071 if (ch >= 6 && enable_1510_mode)
2072 continue;
2073
2074 if (dma_omap1()) {
2075 /*
2076 * request_irq() doesn't like dev_id (ie. ch) being
2077 * zero, so we have to kludge around this.
2078 */
2079 sprintf(&irq_name[0], "%d", ch);
2080 dma_irq = platform_get_irq_byname(pdev, irq_name);
2081
2082 if (dma_irq < 0) {
2083 ret = dma_irq;
2084 goto exit_dma_irq_fail;
2085 }
2086
2087 /* INT_DMA_LCD is handled in lcd_dma.c */
2088 if (dma_irq == INT_DMA_LCD)
2089 continue;
2090
2091 ret = request_irq(dma_irq,
2092 omap1_dma_irq_handler, 0, "DMA",
2093 (void *) (ch + 1));
2094 if (ret != 0)
2095 goto exit_dma_irq_fail;
2096 }
2097 }
2098
2099 if (d->dev_caps & IS_RW_PRIORITY)
2100 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2101 DMA_DEFAULT_FIFO_DEPTH, 0);
2102
2103 if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
2104 strcpy(irq_name, "0");
2105 dma_irq = platform_get_irq_byname(pdev, irq_name);
2106 if (dma_irq < 0) {
2107 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2108 ret = dma_irq;
2109 goto exit_dma_lch_fail;
2110 }
2111 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2112 if (ret) {
2113 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
2114 dma_irq, ret);
2115 goto exit_dma_lch_fail;
2116 }
2117 }
2118
2119 /* reserve dma channels 0 and 1 in high security devices on 34xx */
2120 if (d->dev_caps & HS_CHANNELS_RESERVED) {
2121 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2122 dma_chan[0].dev_id = 0;
2123 dma_chan[1].dev_id = 1;
2124 }
2125 p->show_dma_caps();
2126 return 0;
2127
2128 exit_dma_irq_fail:
2129 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
2130 dma_irq, ret);
2131 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2132 dma_irq = platform_get_irq(pdev, irq_rel);
2133 free_irq(dma_irq, (void *)(irq_rel + 1));
2134 }
2135
2136 exit_dma_lch_fail:
2137 return ret;
2138 }
2139
2140 static int omap_system_dma_remove(struct platform_device *pdev)
2141 {
2142 int dma_irq;
2143
2144 if (dma_omap2plus()) {
2145 char irq_name[4];
2146 strcpy(irq_name, "0");
2147 dma_irq = platform_get_irq_byname(pdev, irq_name);
2148 if (dma_irq >= 0)
2149 remove_irq(dma_irq, &omap24xx_dma_irq);
2150 } else {
2151 int irq_rel = 0;
2152 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2153 dma_irq = platform_get_irq(pdev, irq_rel);
2154 free_irq(dma_irq, (void *)(irq_rel + 1));
2155 }
2156 }
2157 return 0;
2158 }
2159
2160 static struct platform_driver omap_system_dma_driver = {
2161 .probe = omap_system_dma_probe,
2162 .remove = omap_system_dma_remove,
2163 .driver = {
2164 .name = "omap_dma_system"
2165 },
2166 };
2167
2168 static int __init omap_system_dma_init(void)
2169 {
2170 return platform_driver_register(&omap_system_dma_driver);
2171 }
2172 arch_initcall(omap_system_dma_init);
2173
2174 static void __exit omap_system_dma_exit(void)
2175 {
2176 platform_driver_unregister(&omap_system_dma_driver);
2177 }
2178
2179 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2180 MODULE_LICENSE("GPL");
2181 MODULE_ALIAS("platform:" DRIVER_NAME);
2182 MODULE_AUTHOR("Texas Instruments Inc");
2183
2184 /*
2185 * Reserve the omap SDMA channels using cmdline bootarg
2186 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2187 */
2188 static int __init omap_dma_cmdline_reserve_ch(char *str)
2189 {
2190 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2191 omap_dma_reserve_channels = 0;
2192 return 1;
2193 }
2194
2195 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2196
2197
Linux kernel - Deliverables
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