2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <mach/hardware.h>
45 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
46 * channels that an instance of the SDMA IP block can support. Used
47 * to size arrays. (The actual maximum on a particular SoC may be less
48 * than this -- for example, OMAP1 SDMA instances only support 17 logical
51 #define MAX_LOGICAL_DMA_CH_COUNT 32
55 #ifndef CONFIG_ARCH_OMAP1
56 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
57 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
60 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
63 #define OMAP_DMA_ACTIVE 0x01
64 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
66 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
68 static struct omap_system_dma_plat_info
*p
;
69 static struct omap_dma_dev_attr
*d
;
71 static int enable_1510_mode
;
74 static struct omap_dma_global_context_registers
{
76 u32 dma_ocp_sysconfig
;
78 } omap_dma_global_context
;
80 struct dma_link_info
{
82 int no_of_lchs_linked
;
93 static struct dma_link_info
*dma_linked_lch
;
95 #ifndef CONFIG_ARCH_OMAP1
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
129 static int dma_lch_count
;
130 static int dma_chan_count
;
131 static int omap_dma_reserve_channels
;
133 static spinlock_t dma_chan_lock
;
134 static struct omap_dma_lch
*dma_chan
;
136 static inline void disable_lnk(int lch
);
137 static void omap_disable_channel_irq(int lch
);
138 static inline void omap_enable_channel_irq(int lch
);
140 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
143 #ifdef CONFIG_ARCH_OMAP15XX
144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
145 static int omap_dma_in_1510_mode(void)
147 return enable_1510_mode
;
150 #define omap_dma_in_1510_mode() 0
153 #ifdef CONFIG_ARCH_OMAP1
154 static inline int get_gdma_dev(int req
)
156 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
157 int shift
= ((req
- 1) % 5) * 6;
159 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
162 static inline void set_gdma_dev(int req
, int dev
)
164 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
165 int shift
= ((req
- 1) % 5) * 6;
169 l
&= ~(0x3f << shift
);
170 l
|= (dev
- 1) << shift
;
174 #define set_gdma_dev(req, dev) do {} while (0)
175 #define omap_readl(reg) 0
176 #define omap_writel(val, reg) do {} while (0)
179 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
184 if (cpu_class_is_omap1()) {
186 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
187 reg
= OMAP_TC_OCPT1_PRIOR
;
189 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
190 reg
= OMAP_TC_OCPT2_PRIOR
;
192 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
193 reg
= OMAP_TC_EMIFF_PRIOR
;
195 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
196 reg
= OMAP_TC_EMIFS_PRIOR
;
204 l
|= (priority
& 0xf) << 8;
208 if (cpu_class_is_omap2()) {
211 ccr
= p
->dma_read(CCR
, lch
);
216 p
->dma_write(ccr
, CCR
, lch
);
219 EXPORT_SYMBOL(omap_set_dma_priority
);
221 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
222 int frame_count
, int sync_mode
,
223 int dma_trigger
, int src_or_dst_synch
)
227 l
= p
->dma_read(CSDP
, lch
);
230 p
->dma_write(l
, CSDP
, lch
);
232 if (cpu_class_is_omap1()) {
235 ccr
= p
->dma_read(CCR
, lch
);
237 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
239 p
->dma_write(ccr
, CCR
, lch
);
241 ccr
= p
->dma_read(CCR2
, lch
);
243 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
245 p
->dma_write(ccr
, CCR2
, lch
);
248 if (cpu_class_is_omap2() && dma_trigger
) {
251 val
= p
->dma_read(CCR
, lch
);
253 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
254 val
&= ~((1 << 23) | (3 << 19) | 0x1f);
255 val
|= (dma_trigger
& ~0x1f) << 14;
256 val
|= dma_trigger
& 0x1f;
258 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
263 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
268 if (src_or_dst_synch
== OMAP_DMA_DST_SYNC_PREFETCH
) {
269 val
&= ~(1 << 24); /* dest synch */
270 val
|= (1 << 23); /* Prefetch */
271 } else if (src_or_dst_synch
) {
272 val
|= 1 << 24; /* source synch */
274 val
&= ~(1 << 24); /* dest synch */
276 p
->dma_write(val
, CCR
, lch
);
279 p
->dma_write(elem_count
, CEN
, lch
);
280 p
->dma_write(frame_count
, CFN
, lch
);
282 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
284 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
286 BUG_ON(omap_dma_in_1510_mode());
288 if (cpu_class_is_omap1()) {
291 w
= p
->dma_read(CCR2
, lch
);
295 case OMAP_DMA_CONSTANT_FILL
:
298 case OMAP_DMA_TRANSPARENT_COPY
:
301 case OMAP_DMA_COLOR_DIS
:
306 p
->dma_write(w
, CCR2
, lch
);
308 w
= p
->dma_read(LCH_CTRL
, lch
);
310 /* Default is channel type 2D */
312 p
->dma_write(color
, COLOR
, lch
);
313 w
|= 1; /* Channel type G */
315 p
->dma_write(w
, LCH_CTRL
, lch
);
318 if (cpu_class_is_omap2()) {
321 val
= p
->dma_read(CCR
, lch
);
322 val
&= ~((1 << 17) | (1 << 16));
325 case OMAP_DMA_CONSTANT_FILL
:
328 case OMAP_DMA_TRANSPARENT_COPY
:
331 case OMAP_DMA_COLOR_DIS
:
336 p
->dma_write(val
, CCR
, lch
);
339 p
->dma_write(color
, COLOR
, lch
);
342 EXPORT_SYMBOL(omap_set_dma_color_mode
);
344 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
346 if (cpu_class_is_omap2()) {
349 csdp
= p
->dma_read(CSDP
, lch
);
350 csdp
&= ~(0x3 << 16);
351 csdp
|= (mode
<< 16);
352 p
->dma_write(csdp
, CSDP
, lch
);
355 EXPORT_SYMBOL(omap_set_dma_write_mode
);
357 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
359 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
362 l
= p
->dma_read(LCH_CTRL
, lch
);
365 p
->dma_write(l
, LCH_CTRL
, lch
);
368 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
370 /* Note that src_port is only for omap1 */
371 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
372 unsigned long src_start
,
373 int src_ei
, int src_fi
)
377 if (cpu_class_is_omap1()) {
380 w
= p
->dma_read(CSDP
, lch
);
383 p
->dma_write(w
, CSDP
, lch
);
386 l
= p
->dma_read(CCR
, lch
);
388 l
|= src_amode
<< 12;
389 p
->dma_write(l
, CCR
, lch
);
391 p
->dma_write(src_start
, CSSA
, lch
);
393 p
->dma_write(src_ei
, CSEI
, lch
);
394 p
->dma_write(src_fi
, CSFI
, lch
);
396 EXPORT_SYMBOL(omap_set_dma_src_params
);
398 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
400 omap_set_dma_transfer_params(lch
, params
->data_type
,
401 params
->elem_count
, params
->frame_count
,
402 params
->sync_mode
, params
->trigger
,
403 params
->src_or_dst_synch
);
404 omap_set_dma_src_params(lch
, params
->src_port
,
405 params
->src_amode
, params
->src_start
,
406 params
->src_ei
, params
->src_fi
);
408 omap_set_dma_dest_params(lch
, params
->dst_port
,
409 params
->dst_amode
, params
->dst_start
,
410 params
->dst_ei
, params
->dst_fi
);
411 if (params
->read_prio
|| params
->write_prio
)
412 omap_dma_set_prio_lch(lch
, params
->read_prio
,
415 EXPORT_SYMBOL(omap_set_dma_params
);
417 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
419 if (cpu_class_is_omap2())
422 p
->dma_write(eidx
, CSEI
, lch
);
423 p
->dma_write(fidx
, CSFI
, lch
);
425 EXPORT_SYMBOL(omap_set_dma_src_index
);
427 void omap_set_dma_src_data_pack(int lch
, int enable
)
431 l
= p
->dma_read(CSDP
, lch
);
435 p
->dma_write(l
, CSDP
, lch
);
437 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
439 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
441 unsigned int burst
= 0;
444 l
= p
->dma_read(CSDP
, lch
);
447 switch (burst_mode
) {
448 case OMAP_DMA_DATA_BURST_DIS
:
450 case OMAP_DMA_DATA_BURST_4
:
451 if (cpu_class_is_omap2())
456 case OMAP_DMA_DATA_BURST_8
:
457 if (cpu_class_is_omap2()) {
462 * not supported by current hardware on OMAP1
466 case OMAP_DMA_DATA_BURST_16
:
467 if (cpu_class_is_omap2()) {
472 * OMAP1 don't support burst 16
480 p
->dma_write(l
, CSDP
, lch
);
482 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
484 /* Note that dest_port is only for OMAP1 */
485 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
486 unsigned long dest_start
,
487 int dst_ei
, int dst_fi
)
491 if (cpu_class_is_omap1()) {
492 l
= p
->dma_read(CSDP
, lch
);
495 p
->dma_write(l
, CSDP
, lch
);
498 l
= p
->dma_read(CCR
, lch
);
500 l
|= dest_amode
<< 14;
501 p
->dma_write(l
, CCR
, lch
);
503 p
->dma_write(dest_start
, CDSA
, lch
);
505 p
->dma_write(dst_ei
, CDEI
, lch
);
506 p
->dma_write(dst_fi
, CDFI
, lch
);
508 EXPORT_SYMBOL(omap_set_dma_dest_params
);
510 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
512 if (cpu_class_is_omap2())
515 p
->dma_write(eidx
, CDEI
, lch
);
516 p
->dma_write(fidx
, CDFI
, lch
);
518 EXPORT_SYMBOL(omap_set_dma_dest_index
);
520 void omap_set_dma_dest_data_pack(int lch
, int enable
)
524 l
= p
->dma_read(CSDP
, lch
);
528 p
->dma_write(l
, CSDP
, lch
);
530 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
532 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
534 unsigned int burst
= 0;
537 l
= p
->dma_read(CSDP
, lch
);
540 switch (burst_mode
) {
541 case OMAP_DMA_DATA_BURST_DIS
:
543 case OMAP_DMA_DATA_BURST_4
:
544 if (cpu_class_is_omap2())
549 case OMAP_DMA_DATA_BURST_8
:
550 if (cpu_class_is_omap2())
555 case OMAP_DMA_DATA_BURST_16
:
556 if (cpu_class_is_omap2()) {
561 * OMAP1 don't support burst 16
565 printk(KERN_ERR
"Invalid DMA burst mode\n");
570 p
->dma_write(l
, CSDP
, lch
);
572 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
574 static inline void omap_enable_channel_irq(int lch
)
577 if (cpu_class_is_omap1())
578 p
->dma_read(CSR
, lch
);
580 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
582 /* Enable some nice interrupts. */
583 p
->dma_write(dma_chan
[lch
].enabled_irqs
, CICR
, lch
);
586 static inline void omap_disable_channel_irq(int lch
)
588 /* disable channel interrupts */
589 p
->dma_write(0, CICR
, lch
);
591 if (cpu_class_is_omap1())
592 p
->dma_read(CSR
, lch
);
594 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
597 void omap_enable_dma_irq(int lch
, u16 bits
)
599 dma_chan
[lch
].enabled_irqs
|= bits
;
601 EXPORT_SYMBOL(omap_enable_dma_irq
);
603 void omap_disable_dma_irq(int lch
, u16 bits
)
605 dma_chan
[lch
].enabled_irqs
&= ~bits
;
607 EXPORT_SYMBOL(omap_disable_dma_irq
);
609 static inline void enable_lnk(int lch
)
613 l
= p
->dma_read(CLNK_CTRL
, lch
);
615 if (cpu_class_is_omap1())
618 /* Set the ENABLE_LNK bits */
619 if (dma_chan
[lch
].next_lch
!= -1)
620 l
= dma_chan
[lch
].next_lch
| (1 << 15);
622 #ifndef CONFIG_ARCH_OMAP1
623 if (cpu_class_is_omap2())
624 if (dma_chan
[lch
].next_linked_ch
!= -1)
625 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
628 p
->dma_write(l
, CLNK_CTRL
, lch
);
631 static inline void disable_lnk(int lch
)
635 l
= p
->dma_read(CLNK_CTRL
, lch
);
637 /* Disable interrupts */
638 omap_disable_channel_irq(lch
);
640 if (cpu_class_is_omap1()) {
641 /* Set the STOP_LNK bit */
645 if (cpu_class_is_omap2()) {
646 /* Clear the ENABLE_LNK bit */
650 p
->dma_write(l
, CLNK_CTRL
, lch
);
651 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
654 static inline void omap2_enable_irq_lch(int lch
)
659 if (!cpu_class_is_omap2())
662 spin_lock_irqsave(&dma_chan_lock
, flags
);
663 /* clear IRQ STATUS */
664 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
665 /* Enable interrupt */
666 val
= p
->dma_read(IRQENABLE_L0
, lch
);
668 p
->dma_write(val
, IRQENABLE_L0
, lch
);
669 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
672 static inline void omap2_disable_irq_lch(int lch
)
677 if (!cpu_class_is_omap2())
680 spin_lock_irqsave(&dma_chan_lock
, flags
);
681 /* Disable interrupt */
682 val
= p
->dma_read(IRQENABLE_L0
, lch
);
684 p
->dma_write(val
, IRQENABLE_L0
, lch
);
685 /* clear IRQ STATUS */
686 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
687 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
690 int omap_request_dma(int dev_id
, const char *dev_name
,
691 void (*callback
)(int lch
, u16 ch_status
, void *data
),
692 void *data
, int *dma_ch_out
)
694 int ch
, free_ch
= -1;
696 struct omap_dma_lch
*chan
;
698 spin_lock_irqsave(&dma_chan_lock
, flags
);
699 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
700 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
707 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
710 chan
= dma_chan
+ free_ch
;
711 chan
->dev_id
= dev_id
;
713 if (p
->clear_lch_regs
)
714 p
->clear_lch_regs(free_ch
);
716 if (cpu_class_is_omap2())
717 omap_clear_dma(free_ch
);
719 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
721 chan
->dev_name
= dev_name
;
722 chan
->callback
= callback
;
726 #ifndef CONFIG_ARCH_OMAP1
727 if (cpu_class_is_omap2()) {
729 chan
->next_linked_ch
= -1;
733 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
735 if (cpu_class_is_omap1())
736 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
737 else if (cpu_class_is_omap2())
738 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
739 OMAP2_DMA_TRANS_ERR_IRQ
;
741 if (cpu_is_omap16xx()) {
742 /* If the sync device is set, configure it dynamically. */
744 set_gdma_dev(free_ch
+ 1, dev_id
);
745 dev_id
= free_ch
+ 1;
748 * Disable the 1510 compatibility mode and set the sync device
751 p
->dma_write(dev_id
| (1 << 10), CCR
, free_ch
);
752 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
753 p
->dma_write(dev_id
, CCR
, free_ch
);
756 if (cpu_class_is_omap2()) {
757 omap_enable_channel_irq(free_ch
);
758 omap2_enable_irq_lch(free_ch
);
761 *dma_ch_out
= free_ch
;
765 EXPORT_SYMBOL(omap_request_dma
);
767 void omap_free_dma(int lch
)
771 if (dma_chan
[lch
].dev_id
== -1) {
772 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
777 /* Disable interrupt for logical channel */
778 if (cpu_class_is_omap2())
779 omap2_disable_irq_lch(lch
);
781 /* Disable all DMA interrupts for the channel. */
782 omap_disable_channel_irq(lch
);
784 /* Make sure the DMA transfer is stopped. */
785 p
->dma_write(0, CCR
, lch
);
787 /* Clear registers */
788 if (cpu_class_is_omap2())
791 spin_lock_irqsave(&dma_chan_lock
, flags
);
792 dma_chan
[lch
].dev_id
= -1;
793 dma_chan
[lch
].next_lch
= -1;
794 dma_chan
[lch
].callback
= NULL
;
795 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
797 EXPORT_SYMBOL(omap_free_dma
);
800 * @brief omap_dma_set_global_params : Set global priority settings for dma
803 * @param max_fifo_depth
804 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
805 * DMA_THREAD_RESERVE_ONET
806 * DMA_THREAD_RESERVE_TWOT
807 * DMA_THREAD_RESERVE_THREET
810 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
814 if (!cpu_class_is_omap2()) {
815 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
819 if (max_fifo_depth
== 0)
824 reg
= 0xff & max_fifo_depth
;
825 reg
|= (0x3 & tparams
) << 12;
826 reg
|= (arb_rate
& 0xff) << 16;
828 p
->dma_write(reg
, GCR
, 0);
830 EXPORT_SYMBOL(omap_dma_set_global_params
);
833 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
836 * @param read_prio - Read priority
837 * @param write_prio - Write priority
838 * Both of the above can be set with one of the following values :
839 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
842 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
843 unsigned char write_prio
)
847 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
848 printk(KERN_ERR
"Invalid channel id\n");
851 l
= p
->dma_read(CCR
, lch
);
852 l
&= ~((1 << 6) | (1 << 26));
853 if (cpu_class_is_omap2() && !cpu_is_omap242x())
854 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
856 l
|= ((read_prio
& 0x1) << 6);
858 p
->dma_write(l
, CCR
, lch
);
862 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
865 * Clears any DMA state so the DMA engine is ready to restart with new buffers
866 * through omap_start_dma(). Any buffers in flight are discarded.
868 void omap_clear_dma(int lch
)
872 local_irq_save(flags
);
874 local_irq_restore(flags
);
876 EXPORT_SYMBOL(omap_clear_dma
);
878 void omap_start_dma(int lch
)
883 * The CPC/CDAC register needs to be initialized to zero
884 * before starting dma transfer.
886 if (cpu_is_omap15xx())
887 p
->dma_write(0, CPC
, lch
);
889 p
->dma_write(0, CDAC
, lch
);
891 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
892 int next_lch
, cur_lch
;
893 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
895 dma_chan_link_map
[lch
] = 1;
896 /* Set the link register of the first channel */
899 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
900 cur_lch
= dma_chan
[lch
].next_lch
;
902 next_lch
= dma_chan
[cur_lch
].next_lch
;
904 /* The loop case: we've been here already */
905 if (dma_chan_link_map
[cur_lch
])
907 /* Mark the current channel */
908 dma_chan_link_map
[cur_lch
] = 1;
911 omap_enable_channel_irq(cur_lch
);
914 } while (next_lch
!= -1);
915 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS
))
916 p
->dma_write(lch
, CLNK_CTRL
, lch
);
918 omap_enable_channel_irq(lch
);
920 l
= p
->dma_read(CCR
, lch
);
922 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING
))
923 l
|= OMAP_DMA_CCR_BUFFERING_DISABLE
;
924 l
|= OMAP_DMA_CCR_EN
;
927 * As dma_write() uses IO accessors which are weakly ordered, there
928 * is no guarantee that data in coherent DMA memory will be visible
929 * to the DMA device. Add a memory barrier here to ensure that any
930 * such data is visible prior to enabling DMA.
933 p
->dma_write(l
, CCR
, lch
);
935 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
937 EXPORT_SYMBOL(omap_start_dma
);
939 void omap_stop_dma(int lch
)
943 /* Disable all interrupts on the channel */
944 omap_disable_channel_irq(lch
);
946 l
= p
->dma_read(CCR
, lch
);
947 if (IS_DMA_ERRATA(DMA_ERRATA_i541
) &&
948 (l
& OMAP_DMA_CCR_SEL_SRC_DST_SYNC
)) {
952 /* Configure No-Standby */
953 l
= p
->dma_read(OCP_SYSCONFIG
, lch
);
955 l
&= ~DMA_SYSCONFIG_MIDLEMODE_MASK
;
956 l
|= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE
);
957 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
959 l
= p
->dma_read(CCR
, lch
);
960 l
&= ~OMAP_DMA_CCR_EN
;
961 p
->dma_write(l
, CCR
, lch
);
963 /* Wait for sDMA FIFO drain */
964 l
= p
->dma_read(CCR
, lch
);
965 while (i
< 100 && (l
& (OMAP_DMA_CCR_RD_ACTIVE
|
966 OMAP_DMA_CCR_WR_ACTIVE
))) {
969 l
= p
->dma_read(CCR
, lch
);
972 printk(KERN_ERR
"DMA drain did not complete on "
974 /* Restore OCP_SYSCONFIG */
975 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, lch
);
977 l
&= ~OMAP_DMA_CCR_EN
;
978 p
->dma_write(l
, CCR
, lch
);
982 * Ensure that data transferred by DMA is visible to any access
983 * after DMA has been disabled. This is important for coherent
988 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
989 int next_lch
, cur_lch
= lch
;
990 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
992 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
994 /* The loop case: we've been here already */
995 if (dma_chan_link_map
[cur_lch
])
997 /* Mark the current channel */
998 dma_chan_link_map
[cur_lch
] = 1;
1000 disable_lnk(cur_lch
);
1002 next_lch
= dma_chan
[cur_lch
].next_lch
;
1004 } while (next_lch
!= -1);
1007 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
1009 EXPORT_SYMBOL(omap_stop_dma
);
1012 * Allows changing the DMA callback function or data. This may be needed if
1013 * the driver shares a single DMA channel for multiple dma triggers.
1015 int omap_set_dma_callback(int lch
,
1016 void (*callback
)(int lch
, u16 ch_status
, void *data
),
1019 unsigned long flags
;
1024 spin_lock_irqsave(&dma_chan_lock
, flags
);
1025 if (dma_chan
[lch
].dev_id
== -1) {
1026 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1027 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1030 dma_chan
[lch
].callback
= callback
;
1031 dma_chan
[lch
].data
= data
;
1032 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1036 EXPORT_SYMBOL(omap_set_dma_callback
);
1039 * Returns current physical source address for the given DMA channel.
1040 * If the channel is running the caller must disable interrupts prior calling
1041 * this function and process the returned value before re-enabling interrupt to
1042 * prevent races with the interrupt handler. Note that in continuous mode there
1043 * is a chance for CSSA_L register overflow between the two reads resulting
1044 * in incorrect return value.
1046 dma_addr_t
omap_get_dma_src_pos(int lch
)
1048 dma_addr_t offset
= 0;
1050 if (cpu_is_omap15xx())
1051 offset
= p
->dma_read(CPC
, lch
);
1053 offset
= p
->dma_read(CSAC
, lch
);
1055 if (IS_DMA_ERRATA(DMA_ERRATA_3_3
) && offset
== 0)
1056 offset
= p
->dma_read(CSAC
, lch
);
1058 if (!cpu_is_omap15xx()) {
1060 * CDAC == 0 indicates that the DMA transfer on the channel has
1061 * not been started (no data has been transferred so far).
1062 * Return the programmed source start address in this case.
1064 if (likely(p
->dma_read(CDAC
, lch
)))
1065 offset
= p
->dma_read(CSAC
, lch
);
1067 offset
= p
->dma_read(CSSA
, lch
);
1070 if (cpu_class_is_omap1())
1071 offset
|= (p
->dma_read(CSSA
, lch
) & 0xFFFF0000);
1075 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1078 * Returns current physical destination address for the given DMA channel.
1079 * If the channel is running the caller must disable interrupts prior calling
1080 * this function and process the returned value before re-enabling interrupt to
1081 * prevent races with the interrupt handler. Note that in continuous mode there
1082 * is a chance for CDSA_L register overflow between the two reads resulting
1083 * in incorrect return value.
1085 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1087 dma_addr_t offset
= 0;
1089 if (cpu_is_omap15xx())
1090 offset
= p
->dma_read(CPC
, lch
);
1092 offset
= p
->dma_read(CDAC
, lch
);
1095 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1096 * read before the DMA controller finished disabling the channel.
1098 if (!cpu_is_omap15xx() && offset
== 0) {
1099 offset
= p
->dma_read(CDAC
, lch
);
1101 * CDAC == 0 indicates that the DMA transfer on the channel has
1102 * not been started (no data has been transferred so far).
1103 * Return the programmed destination start address in this case.
1105 if (unlikely(!offset
))
1106 offset
= p
->dma_read(CDSA
, lch
);
1109 if (cpu_class_is_omap1())
1110 offset
|= (p
->dma_read(CDSA
, lch
) & 0xFFFF0000);
1114 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1116 int omap_get_dma_active_status(int lch
)
1118 return (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
) != 0;
1120 EXPORT_SYMBOL(omap_get_dma_active_status
);
1122 int omap_dma_running(void)
1126 if (cpu_class_is_omap1())
1127 if (omap_lcd_dma_running())
1130 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1131 if (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
)
1138 * lch_queue DMA will start right after lch_head one is finished.
1139 * For this DMA link to start, you still need to start (see omap_start_dma)
1140 * the first one. That will fire up the entire queue.
1142 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1144 if (omap_dma_in_1510_mode()) {
1145 if (lch_head
== lch_queue
) {
1146 p
->dma_write(p
->dma_read(CCR
, lch_head
) | (3 << 8),
1150 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1155 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1156 (dma_chan
[lch_queue
].dev_id
== -1)) {
1157 printk(KERN_ERR
"omap_dma: trying to link "
1158 "non requested channels\n");
1162 dma_chan
[lch_head
].next_lch
= lch_queue
;
1164 EXPORT_SYMBOL(omap_dma_link_lch
);
1167 * Once the DMA queue is stopped, we can destroy it.
1169 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1171 if (omap_dma_in_1510_mode()) {
1172 if (lch_head
== lch_queue
) {
1173 p
->dma_write(p
->dma_read(CCR
, lch_head
) & ~(3 << 8),
1177 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1182 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1183 dma_chan
[lch_head
].next_lch
== -1) {
1184 printk(KERN_ERR
"omap_dma: trying to unlink "
1185 "non linked channels\n");
1189 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1190 (dma_chan
[lch_queue
].flags
& OMAP_DMA_ACTIVE
)) {
1191 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
1192 "before unlinking\n");
1196 dma_chan
[lch_head
].next_lch
= -1;
1198 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1200 #ifndef CONFIG_ARCH_OMAP1
1201 /* Create chain of DMA channesls */
1202 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1206 /* Check if this is the first link in chain */
1207 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1208 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1209 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1210 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1211 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1214 /* a link exists, link the new channel in circular chain */
1216 dma_chan
[lch_queue
].next_linked_ch
=
1217 dma_chan
[lch_head
].next_linked_ch
;
1218 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1219 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1220 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1224 l
= p
->dma_read(CLNK_CTRL
, lch_head
);
1227 p
->dma_write(l
, CLNK_CTRL
, lch_head
);
1229 l
= p
->dma_read(CLNK_CTRL
, lch_queue
);
1231 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1232 p
->dma_write(l
, CLNK_CTRL
, lch_queue
);
1236 * @brief omap_request_dma_chain : Request a chain of DMA channels
1238 * @param dev_id - Device id using the dma channel
1239 * @param dev_name - Device name
1240 * @param callback - Call back function
1242 * @no_of_chans - Number of channels requested
1243 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1244 * OMAP_DMA_DYNAMIC_CHAIN
1245 * @params - Channel parameters
1247 * @return - Success : 0
1248 * Failure: -EINVAL/-ENOMEM
1250 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1251 void (*callback
) (int lch
, u16 ch_status
,
1253 int *chain_id
, int no_of_chans
, int chain_mode
,
1254 struct omap_dma_channel_params params
)
1259 /* Is the chain mode valid ? */
1260 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1261 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1262 printk(KERN_ERR
"Invalid chain mode requested\n");
1266 if (unlikely((no_of_chans
< 1
1267 || no_of_chans
> dma_lch_count
))) {
1268 printk(KERN_ERR
"Invalid Number of channels requested\n");
1273 * Allocate a queue to maintain the status of the channels
1276 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1277 if (channels
== NULL
) {
1278 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1282 /* request and reserve DMA channels for the chain */
1283 for (i
= 0; i
< no_of_chans
; i
++) {
1284 err
= omap_request_dma(dev_id
, dev_name
,
1285 callback
, NULL
, &channels
[i
]);
1288 for (j
= 0; j
< i
; j
++)
1289 omap_free_dma(channels
[j
]);
1291 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1294 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1295 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1298 * Allowing client drivers to set common parameters now,
1299 * so that later only relevant (src_start, dest_start
1300 * and element count) can be set
1302 omap_set_dma_params(channels
[i
], ¶ms
);
1305 *chain_id
= channels
[0];
1306 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1307 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1308 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1309 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1311 for (i
= 0; i
< no_of_chans
; i
++)
1312 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1314 /* Reset the Queue pointers */
1315 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1317 /* Set up the chain */
1318 if (no_of_chans
== 1)
1319 create_dma_lch_chain(channels
[0], channels
[0]);
1321 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1322 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1327 EXPORT_SYMBOL(omap_request_dma_chain
);
1330 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1331 * params after setting it. Dont do this while dma is running!!
1333 * @param chain_id - Chained logical channel id.
1336 * @return - Success : 0
1339 int omap_modify_dma_chain_params(int chain_id
,
1340 struct omap_dma_channel_params params
)
1345 /* Check for input params */
1346 if (unlikely((chain_id
< 0
1347 || chain_id
>= dma_lch_count
))) {
1348 printk(KERN_ERR
"Invalid chain id\n");
1352 /* Check if the chain exists */
1353 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1354 printk(KERN_ERR
"Chain doesn't exists\n");
1357 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1359 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1361 * Allowing client drivers to set common parameters now,
1362 * so that later only relevant (src_start, dest_start
1363 * and element count) can be set
1365 omap_set_dma_params(channels
[i
], ¶ms
);
1370 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1373 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1377 * @return - Success : 0
1380 int omap_free_dma_chain(int chain_id
)
1385 /* Check for input params */
1386 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1387 printk(KERN_ERR
"Invalid chain id\n");
1391 /* Check if the chain exists */
1392 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1393 printk(KERN_ERR
"Chain doesn't exists\n");
1397 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1398 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1399 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1400 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1401 dma_chan
[channels
[i
]].chain_id
= -1;
1402 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1403 omap_free_dma(channels
[i
]);
1408 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1409 dma_linked_lch
[chain_id
].chain_mode
= -1;
1410 dma_linked_lch
[chain_id
].chain_state
= -1;
1414 EXPORT_SYMBOL(omap_free_dma_chain
);
1417 * @brief omap_dma_chain_status - Check if the chain is in
1418 * active / inactive state.
1421 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1424 int omap_dma_chain_status(int chain_id
)
1426 /* Check for input params */
1427 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1428 printk(KERN_ERR
"Invalid chain id\n");
1432 /* Check if the chain exists */
1433 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1434 printk(KERN_ERR
"Chain doesn't exists\n");
1437 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1438 dma_linked_lch
[chain_id
].q_count
);
1440 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1441 return OMAP_DMA_CHAIN_INACTIVE
;
1443 return OMAP_DMA_CHAIN_ACTIVE
;
1445 EXPORT_SYMBOL(omap_dma_chain_status
);
1448 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1449 * set the params and start the transfer.
1452 * @param src_start - buffer start address
1453 * @param dest_start - Dest address
1455 * @param frame_count
1456 * @param callbk_data - channel callback parameter data.
1458 * @return - Success : 0
1459 * Failure: -EINVAL/-EBUSY
1461 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1462 int elem_count
, int frame_count
, void *callbk_data
)
1469 * if buffer size is less than 1 then there is
1470 * no use of starting the chain
1472 if (elem_count
< 1) {
1473 printk(KERN_ERR
"Invalid buffer size\n");
1477 /* Check for input params */
1478 if (unlikely((chain_id
< 0
1479 || chain_id
>= dma_lch_count
))) {
1480 printk(KERN_ERR
"Invalid chain id\n");
1484 /* Check if the chain exists */
1485 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1486 printk(KERN_ERR
"Chain doesn't exist\n");
1490 /* Check if all the channels in chain are in use */
1491 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1494 /* Frame count may be negative in case of indexed transfers */
1495 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1497 /* Get a free channel */
1498 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1500 /* Store the callback data */
1501 dma_chan
[lch
].data
= callbk_data
;
1503 /* Increment the q_tail */
1504 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1506 /* Set the params to the free channel */
1508 p
->dma_write(src_start
, CSSA
, lch
);
1509 if (dest_start
!= 0)
1510 p
->dma_write(dest_start
, CDSA
, lch
);
1512 /* Write the buffer size */
1513 p
->dma_write(elem_count
, CEN
, lch
);
1514 p
->dma_write(frame_count
, CFN
, lch
);
1517 * If the chain is dynamically linked,
1518 * then we may have to start the chain if its not active
1520 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1523 * In Dynamic chain, if the chain is not started,
1526 if (dma_linked_lch
[chain_id
].chain_state
==
1527 DMA_CHAIN_NOTSTARTED
) {
1528 /* Enable the link in previous channel */
1529 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1531 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1532 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1536 * Chain is already started, make sure its active,
1537 * if not then start the chain
1542 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1544 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1545 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1547 if (0 == ((1 << 7) & p
->dma_read(
1548 CCR
, dma_chan
[lch
].prev_linked_ch
))) {
1549 disable_lnk(dma_chan
[lch
].
1551 pr_debug("\n prev ch is stopped\n");
1556 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1558 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1559 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1562 omap_enable_channel_irq(lch
);
1564 l
= p
->dma_read(CCR
, lch
);
1566 if ((0 == (l
& (1 << 24))))
1570 if (start_dma
== 1) {
1571 if (0 == (l
& (1 << 7))) {
1573 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1574 pr_debug("starting %d\n", lch
);
1575 p
->dma_write(l
, CCR
, lch
);
1579 if (0 == (l
& (1 << 7)))
1580 p
->dma_write(l
, CCR
, lch
);
1582 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1588 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1591 * @brief omap_start_dma_chain_transfers - Start the chain
1595 * @return - Success : 0
1596 * Failure : -EINVAL/-EBUSY
1598 int omap_start_dma_chain_transfers(int chain_id
)
1603 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1604 printk(KERN_ERR
"Invalid chain id\n");
1608 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1610 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1611 printk(KERN_ERR
"Chain is already started\n");
1615 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1616 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1618 enable_lnk(channels
[i
]);
1619 omap_enable_channel_irq(channels
[i
]);
1622 omap_enable_channel_irq(channels
[0]);
1625 l
= p
->dma_read(CCR
, channels
[0]);
1627 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1628 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1630 if ((0 == (l
& (1 << 24))))
1634 p
->dma_write(l
, CCR
, channels
[0]);
1636 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1640 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1643 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1647 * @return - Success : 0
1650 int omap_stop_dma_chain_transfers(int chain_id
)
1656 /* Check for input params */
1657 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1658 printk(KERN_ERR
"Invalid chain id\n");
1662 /* Check if the chain exists */
1663 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1664 printk(KERN_ERR
"Chain doesn't exists\n");
1667 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1669 if (IS_DMA_ERRATA(DMA_ERRATA_i88
)) {
1670 sys_cf
= p
->dma_read(OCP_SYSCONFIG
, 0);
1672 /* Middle mode reg set no Standby */
1673 l
&= ~((1 << 12)|(1 << 13));
1674 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
1677 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1679 /* Stop the Channel transmission */
1680 l
= p
->dma_read(CCR
, channels
[i
]);
1682 p
->dma_write(l
, CCR
, channels
[i
]);
1684 /* Disable the link in all the channels */
1685 disable_lnk(channels
[i
]);
1686 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1689 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1691 /* Reset the Queue pointers */
1692 OMAP_DMA_CHAIN_QINIT(chain_id
);
1694 if (IS_DMA_ERRATA(DMA_ERRATA_i88
))
1695 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, 0);
1699 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1701 /* Get the index of the ongoing DMA in chain */
1703 * @brief omap_get_dma_chain_index - Get the element and frame index
1704 * of the ongoing DMA in chain
1707 * @param ei - Element index
1708 * @param fi - Frame index
1710 * @return - Success : 0
1713 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1718 /* Check for input params */
1719 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1720 printk(KERN_ERR
"Invalid chain id\n");
1724 /* Check if the chain exists */
1725 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1726 printk(KERN_ERR
"Chain doesn't exists\n");
1732 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1734 /* Get the current channel */
1735 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1737 *ei
= p
->dma_read(CCEN
, lch
);
1738 *fi
= p
->dma_read(CCFN
, lch
);
1742 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1745 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1746 * ongoing DMA in chain
1750 * @return - Success : Destination position
1753 int omap_get_dma_chain_dst_pos(int chain_id
)
1758 /* Check for input params */
1759 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1760 printk(KERN_ERR
"Invalid chain id\n");
1764 /* Check if the chain exists */
1765 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1766 printk(KERN_ERR
"Chain doesn't exists\n");
1770 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1772 /* Get the current channel */
1773 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1775 return p
->dma_read(CDAC
, lch
);
1777 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1780 * @brief omap_get_dma_chain_src_pos - Get the source position
1781 * of the ongoing DMA in chain
1784 * @return - Success : Destination position
1787 int omap_get_dma_chain_src_pos(int chain_id
)
1792 /* Check for input params */
1793 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1794 printk(KERN_ERR
"Invalid chain id\n");
1798 /* Check if the chain exists */
1799 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1800 printk(KERN_ERR
"Chain doesn't exists\n");
1804 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1806 /* Get the current channel */
1807 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1809 return p
->dma_read(CSAC
, lch
);
1811 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1812 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1814 /*----------------------------------------------------------------------------*/
1816 #ifdef CONFIG_ARCH_OMAP1
1818 static int omap1_dma_handle_ch(int ch
)
1822 if (enable_1510_mode
&& ch
>= 6) {
1823 csr
= dma_chan
[ch
].saved_csr
;
1824 dma_chan
[ch
].saved_csr
= 0;
1826 csr
= p
->dma_read(CSR
, ch
);
1827 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1828 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1831 if ((csr
& 0x3f) == 0)
1833 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1834 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
1835 "%d (CSR %04x)\n", ch
, csr
);
1838 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1839 printk(KERN_WARNING
"DMA timeout with device %d\n",
1840 dma_chan
[ch
].dev_id
);
1841 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1842 printk(KERN_WARNING
"DMA synchronization event drop occurred "
1843 "with device %d\n", dma_chan
[ch
].dev_id
);
1844 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1845 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1846 if (likely(dma_chan
[ch
].callback
!= NULL
))
1847 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1852 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1854 int ch
= ((int) dev_id
) - 1;
1858 int handled_now
= 0;
1860 handled_now
+= omap1_dma_handle_ch(ch
);
1861 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1862 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1865 handled
+= handled_now
;
1868 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1872 #define omap1_dma_irq_handler NULL
1875 #ifdef CONFIG_ARCH_OMAP2PLUS
1877 static int omap2_dma_handle_ch(int ch
)
1879 u32 status
= p
->dma_read(CSR
, ch
);
1882 if (printk_ratelimit())
1883 printk(KERN_WARNING
"Spurious DMA IRQ for lch %d\n",
1885 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1888 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1889 if (printk_ratelimit())
1890 printk(KERN_WARNING
"IRQ %04x for non-allocated DMA"
1891 "channel %d\n", status
, ch
);
1894 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1896 "DMA synchronization event drop occurred with device "
1897 "%d\n", dma_chan
[ch
].dev_id
);
1898 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
)) {
1899 printk(KERN_INFO
"DMA transaction error with device %d\n",
1900 dma_chan
[ch
].dev_id
);
1901 if (IS_DMA_ERRATA(DMA_ERRATA_i378
)) {
1904 ccr
= p
->dma_read(CCR
, ch
);
1905 ccr
&= ~OMAP_DMA_CCR_EN
;
1906 p
->dma_write(ccr
, CCR
, ch
);
1907 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1910 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1911 printk(KERN_INFO
"DMA secure error with device %d\n",
1912 dma_chan
[ch
].dev_id
);
1913 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1914 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1915 dma_chan
[ch
].dev_id
);
1917 p
->dma_write(status
, CSR
, ch
);
1918 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1919 /* read back the register to flush the write */
1920 p
->dma_read(IRQSTATUS_L0
, ch
);
1922 /* If the ch is not chained then chain_id will be -1 */
1923 if (dma_chan
[ch
].chain_id
!= -1) {
1924 int chain_id
= dma_chan
[ch
].chain_id
;
1925 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1926 if (p
->dma_read(CLNK_CTRL
, ch
) & (1 << 15))
1927 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1929 if (dma_linked_lch
[chain_id
].chain_mode
==
1930 OMAP_DMA_DYNAMIC_CHAIN
)
1933 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1934 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1936 status
= p
->dma_read(CSR
, ch
);
1937 p
->dma_write(status
, CSR
, ch
);
1940 if (likely(dma_chan
[ch
].callback
!= NULL
))
1941 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1946 /* STATUS register count is from 1-32 while our is 0-31 */
1947 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1949 u32 val
, enable_reg
;
1952 val
= p
->dma_read(IRQSTATUS_L0
, 0);
1954 if (printk_ratelimit())
1955 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1958 enable_reg
= p
->dma_read(IRQENABLE_L0
, 0);
1959 val
&= enable_reg
; /* Dispatch only relevant interrupts */
1960 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1962 omap2_dma_handle_ch(i
);
1969 static struct irqaction omap24xx_dma_irq
= {
1971 .handler
= omap2_dma_irq_handler
,
1972 .flags
= IRQF_DISABLED
1976 static struct irqaction omap24xx_dma_irq
;
1979 /*----------------------------------------------------------------------------*/
1981 void omap_dma_global_context_save(void)
1983 omap_dma_global_context
.dma_irqenable_l0
=
1984 p
->dma_read(IRQENABLE_L0
, 0);
1985 omap_dma_global_context
.dma_ocp_sysconfig
=
1986 p
->dma_read(OCP_SYSCONFIG
, 0);
1987 omap_dma_global_context
.dma_gcr
= p
->dma_read(GCR
, 0);
1990 void omap_dma_global_context_restore(void)
1994 p
->dma_write(omap_dma_global_context
.dma_gcr
, GCR
, 0);
1995 p
->dma_write(omap_dma_global_context
.dma_ocp_sysconfig
,
1997 p
->dma_write(omap_dma_global_context
.dma_irqenable_l0
,
2000 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG
))
2001 p
->dma_write(0x3 , IRQSTATUS_L0
, 0);
2003 for (ch
= 0; ch
< dma_chan_count
; ch
++)
2004 if (dma_chan
[ch
].dev_id
!= -1)
2008 static int __devinit
omap_system_dma_probe(struct platform_device
*pdev
)
2015 p
= pdev
->dev
.platform_data
;
2017 dev_err(&pdev
->dev
, "%s: System DMA initialized without"
2018 "platform data\n", __func__
);
2025 if ((d
->dev_caps
& RESERVE_CHANNEL
) && omap_dma_reserve_channels
2026 && (omap_dma_reserve_channels
<= dma_lch_count
))
2027 d
->lch_count
= omap_dma_reserve_channels
;
2029 dma_lch_count
= d
->lch_count
;
2030 dma_chan_count
= dma_lch_count
;
2032 enable_1510_mode
= d
->dev_caps
& ENABLE_1510_MODE
;
2034 if (cpu_class_is_omap2()) {
2035 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2036 dma_lch_count
, GFP_KERNEL
);
2037 if (!dma_linked_lch
) {
2039 goto exit_dma_lch_fail
;
2043 spin_lock_init(&dma_chan_lock
);
2044 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2046 if (cpu_class_is_omap2())
2047 omap2_disable_irq_lch(ch
);
2049 dma_chan
[ch
].dev_id
= -1;
2050 dma_chan
[ch
].next_lch
= -1;
2052 if (ch
>= 6 && enable_1510_mode
)
2055 if (cpu_class_is_omap1()) {
2057 * request_irq() doesn't like dev_id (ie. ch) being
2058 * zero, so we have to kludge around this.
2060 sprintf(&irq_name
[0], "%d", ch
);
2061 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2065 goto exit_dma_irq_fail
;
2068 /* INT_DMA_LCD is handled in lcd_dma.c */
2069 if (dma_irq
== INT_DMA_LCD
)
2072 ret
= request_irq(dma_irq
,
2073 omap1_dma_irq_handler
, 0, "DMA",
2076 goto exit_dma_irq_fail
;
2080 if (cpu_class_is_omap2() && !cpu_is_omap242x())
2081 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2082 DMA_DEFAULT_FIFO_DEPTH
, 0);
2084 if (cpu_class_is_omap2()) {
2085 strcpy(irq_name
, "0");
2086 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2088 dev_err(&pdev
->dev
, "failed: request IRQ %d", dma_irq
);
2089 goto exit_dma_lch_fail
;
2091 ret
= setup_irq(dma_irq
, &omap24xx_dma_irq
);
2093 dev_err(&pdev
->dev
, "set_up failed for IRQ %d"
2094 "for DMA (error %d)\n", dma_irq
, ret
);
2095 goto exit_dma_lch_fail
;
2099 /* reserve dma channels 0 and 1 in high security devices */
2100 if (cpu_is_omap34xx() &&
2101 (omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
2102 printk(KERN_INFO
"Reserving DMA channels 0 and 1 for "
2104 dma_chan
[0].dev_id
= 0;
2105 dma_chan
[1].dev_id
= 1;
2111 dev_err(&pdev
->dev
, "unable to request IRQ %d"
2112 "for DMA (error %d)\n", dma_irq
, ret
);
2113 for (irq_rel
= 0; irq_rel
< ch
; irq_rel
++) {
2114 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2115 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2125 static int __devexit
omap_system_dma_remove(struct platform_device
*pdev
)
2129 if (cpu_class_is_omap2()) {
2131 strcpy(irq_name
, "0");
2132 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2133 remove_irq(dma_irq
, &omap24xx_dma_irq
);
2136 for ( ; irq_rel
< dma_chan_count
; irq_rel
++) {
2137 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2138 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2147 static struct platform_driver omap_system_dma_driver
= {
2148 .probe
= omap_system_dma_probe
,
2149 .remove
= __devexit_p(omap_system_dma_remove
),
2151 .name
= "omap_dma_system"
2155 static int __init
omap_system_dma_init(void)
2157 return platform_driver_register(&omap_system_dma_driver
);
2159 arch_initcall(omap_system_dma_init
);
2161 static void __exit
omap_system_dma_exit(void)
2163 platform_driver_unregister(&omap_system_dma_driver
);
2166 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2167 MODULE_LICENSE("GPL");
2168 MODULE_ALIAS("platform:" DRIVER_NAME
);
2169 MODULE_AUTHOR("Texas Instruments Inc");
2172 * Reserve the omap SDMA channels using cmdline bootarg
2173 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2175 static int __init
omap_dma_cmdline_reserve_ch(char *str
)
2177 if (get_option(&str
, &omap_dma_reserve_channels
) != 1)
2178 omap_dma_reserve_channels
= 0;
2182 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch
);