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[ARM] replace remaining __FUNCTION__ occurrences
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28
29 #include <asm/system.h>
30 #include <asm/hardware.h>
31 #include <asm/dma.h>
32 #include <asm/io.h>
33
34 #include <asm/arch/tc.h>
35
36 #undef DEBUG
37
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41 };
42
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44 #endif
45
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51
52 static int enable_1510_mode = 0;
53
54 struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
60 void (* callback)(int lch, u16 ch_status, void *data);
61 void *data;
62
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71 #endif
72 long flags;
73 };
74
75 #ifndef CONFIG_ARCH_OMAP1
76 struct dma_link_info {
77 int *linked_dmach_q;
78 int no_of_lchs_linked;
79
80 int q_count;
81 int q_tail;
82 int q_head;
83
84 int chain_state;
85 int chain_mode;
86
87 };
88
89 static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
90
91 /* Chain handling macros */
92 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
93 do { \
94 dma_linked_lch[chain_id].q_head = \
95 dma_linked_lch[chain_id].q_tail = \
96 dma_linked_lch[chain_id].q_count = 0; \
97 } while (0)
98 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
99 (dma_linked_lch[chain_id].no_of_lchs_linked == \
100 dma_linked_lch[chain_id].q_count)
101 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
102 do { \
103 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
104 dma_linked_lch[chain_id].q_count) \
105 } while (0)
106 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
107 (0 == dma_linked_lch[chain_id].q_count)
108 #define __OMAP_DMA_CHAIN_INCQ(end) \
109 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
110 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
111 do { \
112 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
113 dma_linked_lch[chain_id].q_count--; \
114 } while (0)
115
116 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
117 do { \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
119 dma_linked_lch[chain_id].q_count++; \
120 } while (0)
121 #endif
122 static int dma_chan_count;
123
124 static spinlock_t dma_chan_lock;
125 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
126
127 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
128 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
129 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
130 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
131 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
132 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
133 };
134
135 static inline void disable_lnk(int lch);
136 static void omap_disable_channel_irq(int lch);
137 static inline void omap_enable_channel_irq(int lch);
138
139 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 __func__);
141
142 #ifdef CONFIG_ARCH_OMAP15XX
143 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144 int omap_dma_in_1510_mode(void)
145 {
146 return enable_1510_mode;
147 }
148 #else
149 #define omap_dma_in_1510_mode() 0
150 #endif
151
152 #ifdef CONFIG_ARCH_OMAP1
153 static inline int get_gdma_dev(int req)
154 {
155 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
156 int shift = ((req - 1) % 5) * 6;
157
158 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
159 }
160
161 static inline void set_gdma_dev(int req, int dev)
162 {
163 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
164 int shift = ((req - 1) % 5) * 6;
165 u32 l;
166
167 l = omap_readl(reg);
168 l &= ~(0x3f << shift);
169 l |= (dev - 1) << shift;
170 omap_writel(l, reg);
171 }
172 #else
173 #define set_gdma_dev(req, dev) do {} while (0)
174 #endif
175
176 static void clear_lch_regs(int lch)
177 {
178 int i;
179 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
180
181 for (i = 0; i < 0x2c; i += 2)
182 omap_writew(0, lch_base + i);
183 }
184
185 void omap_set_dma_priority(int lch, int dst_port, int priority)
186 {
187 unsigned long reg;
188 u32 l;
189
190 if (cpu_class_is_omap1()) {
191 switch (dst_port) {
192 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
193 reg = OMAP_TC_OCPT1_PRIOR;
194 break;
195 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
196 reg = OMAP_TC_OCPT2_PRIOR;
197 break;
198 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
199 reg = OMAP_TC_EMIFF_PRIOR;
200 break;
201 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
202 reg = OMAP_TC_EMIFS_PRIOR;
203 break;
204 default:
205 BUG();
206 return;
207 }
208 l = omap_readl(reg);
209 l &= ~(0xf << 8);
210 l |= (priority & 0xf) << 8;
211 omap_writel(l, reg);
212 }
213
214 if (cpu_class_is_omap2()) {
215 if (priority)
216 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
217 else
218 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
219 }
220 }
221
222 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
223 int frame_count, int sync_mode,
224 int dma_trigger, int src_or_dst_synch)
225 {
226 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
227 OMAP_DMA_CSDP_REG(lch) |= data_type;
228
229 if (cpu_class_is_omap1()) {
230 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
231 if (sync_mode == OMAP_DMA_SYNC_FRAME)
232 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
233
234 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
235 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
237 }
238
239 if (cpu_class_is_omap2() && dma_trigger) {
240 u32 val = OMAP_DMA_CCR_REG(lch);
241
242 val &= ~(3 << 19);
243 if (dma_trigger > 63)
244 val |= 1 << 20;
245 if (dma_trigger > 31)
246 val |= 1 << 19;
247
248 val &= ~(0x1f);
249 val |= (dma_trigger & 0x1f);
250
251 if (sync_mode & OMAP_DMA_SYNC_FRAME)
252 val |= 1 << 5;
253 else
254 val &= ~(1 << 5);
255
256 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
257 val |= 1 << 18;
258 else
259 val &= ~(1 << 18);
260
261 if (src_or_dst_synch)
262 val |= 1 << 24; /* source synch */
263 else
264 val &= ~(1 << 24); /* dest synch */
265
266 OMAP_DMA_CCR_REG(lch) = val;
267 }
268
269 OMAP_DMA_CEN_REG(lch) = elem_count;
270 OMAP_DMA_CFN_REG(lch) = frame_count;
271 }
272
273 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
274 {
275 u16 w;
276
277 BUG_ON(omap_dma_in_1510_mode());
278
279 if (cpu_class_is_omap2()) {
280 REVISIT_24XX();
281 return;
282 }
283
284 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
285 switch (mode) {
286 case OMAP_DMA_CONSTANT_FILL:
287 w |= 0x01;
288 break;
289 case OMAP_DMA_TRANSPARENT_COPY:
290 w |= 0x02;
291 break;
292 case OMAP_DMA_COLOR_DIS:
293 break;
294 default:
295 BUG();
296 }
297 OMAP1_DMA_CCR2_REG(lch) = w;
298
299 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
300 /* Default is channel type 2D */
301 if (mode) {
302 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
303 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
304 w |= 1; /* Channel type G */
305 }
306 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
307 }
308
309 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
310 {
311 if (cpu_class_is_omap2()) {
312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
314 }
315 }
316
317 /* Note that src_port is only for omap1 */
318 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start,
320 int src_ei, int src_fi)
321 {
322 if (cpu_class_is_omap1()) {
323 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
324 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
325 }
326
327 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
328 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
329
330 if (cpu_class_is_omap1()) {
331 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
332 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
333 }
334
335 if (cpu_class_is_omap2())
336 OMAP2_DMA_CSSA_REG(lch) = src_start;
337
338 OMAP_DMA_CSEI_REG(lch) = src_ei;
339 OMAP_DMA_CSFI_REG(lch) = src_fi;
340 }
341
342 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
343 {
344 omap_set_dma_transfer_params(lch, params->data_type,
345 params->elem_count, params->frame_count,
346 params->sync_mode, params->trigger,
347 params->src_or_dst_synch);
348 omap_set_dma_src_params(lch, params->src_port,
349 params->src_amode, params->src_start,
350 params->src_ei, params->src_fi);
351
352 omap_set_dma_dest_params(lch, params->dst_port,
353 params->dst_amode, params->dst_start,
354 params->dst_ei, params->dst_fi);
355 if (params->read_prio || params->write_prio)
356 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio);
358 }
359
360 void omap_set_dma_src_index(int lch, int eidx, int fidx)
361 {
362 if (cpu_class_is_omap2()) {
363 REVISIT_24XX();
364 return;
365 }
366 OMAP_DMA_CSEI_REG(lch) = eidx;
367 OMAP_DMA_CSFI_REG(lch) = fidx;
368 }
369
370 void omap_set_dma_src_data_pack(int lch, int enable)
371 {
372 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
373 if (enable)
374 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
375 }
376
377 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
378 {
379 unsigned int burst = 0;
380 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
381
382 switch (burst_mode) {
383 case OMAP_DMA_DATA_BURST_DIS:
384 break;
385 case OMAP_DMA_DATA_BURST_4:
386 if (cpu_class_is_omap2())
387 burst = 0x1;
388 else
389 burst = 0x2;
390 break;
391 case OMAP_DMA_DATA_BURST_8:
392 if (cpu_class_is_omap2()) {
393 burst = 0x2;
394 break;
395 }
396 /* not supported by current hardware on OMAP1
397 * w |= (0x03 << 7);
398 * fall through
399 */
400 case OMAP_DMA_DATA_BURST_16:
401 if (cpu_class_is_omap2()) {
402 burst = 0x3;
403 break;
404 }
405 /* OMAP1 don't support burst 16
406 * fall through
407 */
408 default:
409 BUG();
410 }
411 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
412 }
413
414 /* Note that dest_port is only for OMAP1 */
415 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
416 unsigned long dest_start,
417 int dst_ei, int dst_fi)
418 {
419 if (cpu_class_is_omap1()) {
420 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
421 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
422 }
423
424 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
425 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
426
427 if (cpu_class_is_omap1()) {
428 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
430 }
431
432 if (cpu_class_is_omap2())
433 OMAP2_DMA_CDSA_REG(lch) = dest_start;
434
435 OMAP_DMA_CDEI_REG(lch) = dst_ei;
436 OMAP_DMA_CDFI_REG(lch) = dst_fi;
437 }
438
439 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
440 {
441 if (cpu_class_is_omap2()) {
442 REVISIT_24XX();
443 return;
444 }
445 OMAP_DMA_CDEI_REG(lch) = eidx;
446 OMAP_DMA_CDFI_REG(lch) = fidx;
447 }
448
449 void omap_set_dma_dest_data_pack(int lch, int enable)
450 {
451 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
452 if (enable)
453 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
454 }
455
456 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
457 {
458 unsigned int burst = 0;
459 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
460
461 switch (burst_mode) {
462 case OMAP_DMA_DATA_BURST_DIS:
463 break;
464 case OMAP_DMA_DATA_BURST_4:
465 if (cpu_class_is_omap2())
466 burst = 0x1;
467 else
468 burst = 0x2;
469 break;
470 case OMAP_DMA_DATA_BURST_8:
471 if (cpu_class_is_omap2())
472 burst = 0x2;
473 else
474 burst = 0x3;
475 break;
476 case OMAP_DMA_DATA_BURST_16:
477 if (cpu_class_is_omap2()) {
478 burst = 0x3;
479 break;
480 }
481 /* OMAP1 don't support burst 16
482 * fall through
483 */
484 default:
485 printk(KERN_ERR "Invalid DMA burst mode\n");
486 BUG();
487 return;
488 }
489 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
490 }
491
492 static inline void omap_enable_channel_irq(int lch)
493 {
494 u32 status;
495
496 /* Clear CSR */
497 if (cpu_class_is_omap1())
498 status = OMAP_DMA_CSR_REG(lch);
499 else if (cpu_class_is_omap2())
500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
501
502 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
504
505 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
506 }
507
508 static void omap_disable_channel_irq(int lch)
509 {
510 if (cpu_class_is_omap2())
511 OMAP_DMA_CICR_REG(lch) = 0;
512 }
513
514 void omap_enable_dma_irq(int lch, u16 bits)
515 {
516 dma_chan[lch].enabled_irqs |= bits;
517 }
518
519 void omap_disable_dma_irq(int lch, u16 bits)
520 {
521 dma_chan[lch].enabled_irqs &= ~bits;
522 }
523
524 static inline void enable_lnk(int lch)
525 {
526 if (cpu_class_is_omap1())
527 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
528
529 /* Set the ENABLE_LNK bits */
530 if (dma_chan[lch].next_lch != -1)
531 OMAP_DMA_CLNK_CTRL_REG(lch) =
532 dma_chan[lch].next_lch | (1 << 15);
533
534 #ifndef CONFIG_ARCH_OMAP1
535 if (dma_chan[lch].next_linked_ch != -1)
536 OMAP_DMA_CLNK_CTRL_REG(lch) =
537 dma_chan[lch].next_linked_ch | (1 << 15);
538 #endif
539 }
540
541 static inline void disable_lnk(int lch)
542 {
543 /* Disable interrupts */
544 if (cpu_class_is_omap1()) {
545 OMAP_DMA_CICR_REG(lch) = 0;
546 /* Set the STOP_LNK bit */
547 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
548 }
549
550 if (cpu_class_is_omap2()) {
551 omap_disable_channel_irq(lch);
552 /* Clear the ENABLE_LNK bit */
553 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
554 }
555
556 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
557 }
558
559 static inline void omap2_enable_irq_lch(int lch)
560 {
561 u32 val;
562
563 if (!cpu_class_is_omap2())
564 return;
565
566 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
567 val |= 1 << lch;
568 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
569 }
570
571 int omap_request_dma(int dev_id, const char *dev_name,
572 void (* callback)(int lch, u16 ch_status, void *data),
573 void *data, int *dma_ch_out)
574 {
575 int ch, free_ch = -1;
576 unsigned long flags;
577 struct omap_dma_lch *chan;
578
579 spin_lock_irqsave(&dma_chan_lock, flags);
580 for (ch = 0; ch < dma_chan_count; ch++) {
581 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
582 free_ch = ch;
583 if (dev_id == 0)
584 break;
585 }
586 }
587 if (free_ch == -1) {
588 spin_unlock_irqrestore(&dma_chan_lock, flags);
589 return -EBUSY;
590 }
591 chan = dma_chan + free_ch;
592 chan->dev_id = dev_id;
593
594 if (cpu_class_is_omap1())
595 clear_lch_regs(free_ch);
596
597 if (cpu_class_is_omap2())
598 omap_clear_dma(free_ch);
599
600 spin_unlock_irqrestore(&dma_chan_lock, flags);
601
602 chan->dev_name = dev_name;
603 chan->callback = callback;
604 chan->data = data;
605 #ifndef CONFIG_ARCH_OMAP1
606 chan->chain_id = -1;
607 #endif
608 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
609
610 if (cpu_class_is_omap1())
611 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
612 else if (cpu_class_is_omap2())
613 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
614 OMAP2_DMA_TRANS_ERR_IRQ;
615
616 if (cpu_is_omap16xx()) {
617 /* If the sync device is set, configure it dynamically. */
618 if (dev_id != 0) {
619 set_gdma_dev(free_ch + 1, dev_id);
620 dev_id = free_ch + 1;
621 }
622 /* Disable the 1510 compatibility mode and set the sync device
623 * id. */
624 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
625 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
626 OMAP_DMA_CCR_REG(free_ch) = dev_id;
627 }
628
629 if (cpu_class_is_omap2()) {
630 omap2_enable_irq_lch(free_ch);
631
632 omap_enable_channel_irq(free_ch);
633 /* Clear the CSR register and IRQ status register */
634 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
635 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
636 }
637
638 *dma_ch_out = free_ch;
639
640 return 0;
641 }
642
643 void omap_free_dma(int lch)
644 {
645 unsigned long flags;
646
647 spin_lock_irqsave(&dma_chan_lock, flags);
648 if (dma_chan[lch].dev_id == -1) {
649 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
650 lch);
651 spin_unlock_irqrestore(&dma_chan_lock, flags);
652 return;
653 }
654 dma_chan[lch].dev_id = -1;
655 dma_chan[lch].next_lch = -1;
656 dma_chan[lch].callback = NULL;
657 spin_unlock_irqrestore(&dma_chan_lock, flags);
658
659 if (cpu_class_is_omap1()) {
660 /* Disable all DMA interrupts for the channel. */
661 OMAP_DMA_CICR_REG(lch) = 0;
662 /* Make sure the DMA transfer is stopped. */
663 OMAP_DMA_CCR_REG(lch) = 0;
664 }
665
666 if (cpu_class_is_omap2()) {
667 u32 val;
668 /* Disable interrupts */
669 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
670 val &= ~(1 << lch);
671 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
672
673 /* Clear the CSR register and IRQ status register */
674 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
675 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
676
677 /* Disable all DMA interrupts for the channel. */
678 OMAP_DMA_CICR_REG(lch) = 0;
679
680 /* Make sure the DMA transfer is stopped. */
681 OMAP_DMA_CCR_REG(lch) = 0;
682 omap_clear_dma(lch);
683 }
684 }
685
686 /**
687 * @brief omap_dma_set_global_params : Set global priority settings for dma
688 *
689 * @param arb_rate
690 * @param max_fifo_depth
691 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
692 * DMA_THREAD_RESERVE_ONET
693 * DMA_THREAD_RESERVE_TWOT
694 * DMA_THREAD_RESERVE_THREET
695 */
696 void
697 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
698 {
699 u32 reg;
700
701 if (!cpu_class_is_omap2()) {
702 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
703 return;
704 }
705
706 if (arb_rate == 0)
707 arb_rate = 1;
708
709 reg = (arb_rate & 0xff) << 16;
710 reg |= (0xff & max_fifo_depth);
711
712 omap_writel(reg, OMAP_DMA4_GCR_REG);
713 }
714 EXPORT_SYMBOL(omap_dma_set_global_params);
715
716 /**
717 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
718 *
719 * @param lch
720 * @param read_prio - Read priority
721 * @param write_prio - Write priority
722 * Both of the above can be set with one of the following values :
723 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
724 */
725 int
726 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
727 unsigned char write_prio)
728 {
729 u32 w;
730
731 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
732 printk(KERN_ERR "Invalid channel id\n");
733 return -EINVAL;
734 }
735 w = OMAP_DMA_CCR_REG(lch);
736 w &= ~((1 << 6) | (1 << 26));
737 if (cpu_is_omap2430() || cpu_is_omap34xx())
738 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
739 else
740 w |= ((read_prio & 0x1) << 6);
741
742 OMAP_DMA_CCR_REG(lch) = w;
743 return 0;
744 }
745 EXPORT_SYMBOL(omap_dma_set_prio_lch);
746
747 /*
748 * Clears any DMA state so the DMA engine is ready to restart with new buffers
749 * through omap_start_dma(). Any buffers in flight are discarded.
750 */
751 void omap_clear_dma(int lch)
752 {
753 unsigned long flags;
754
755 local_irq_save(flags);
756
757 if (cpu_class_is_omap1()) {
758 int status;
759 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
760
761 /* Clear pending interrupts */
762 status = OMAP_DMA_CSR_REG(lch);
763 }
764
765 if (cpu_class_is_omap2()) {
766 int i;
767 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
768 for (i = 0; i < 0x44; i += 4)
769 omap_writel(0, lch_base + i);
770 }
771
772 local_irq_restore(flags);
773 }
774
775 void omap_start_dma(int lch)
776 {
777 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
778 int next_lch, cur_lch;
779 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
780
781 dma_chan_link_map[lch] = 1;
782 /* Set the link register of the first channel */
783 enable_lnk(lch);
784
785 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
786 cur_lch = dma_chan[lch].next_lch;
787 do {
788 next_lch = dma_chan[cur_lch].next_lch;
789
790 /* The loop case: we've been here already */
791 if (dma_chan_link_map[cur_lch])
792 break;
793 /* Mark the current channel */
794 dma_chan_link_map[cur_lch] = 1;
795
796 enable_lnk(cur_lch);
797 omap_enable_channel_irq(cur_lch);
798
799 cur_lch = next_lch;
800 } while (next_lch != -1);
801 } else if (cpu_class_is_omap2()) {
802 /* Errata: Need to write lch even if not using chaining */
803 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
804 }
805
806 omap_enable_channel_irq(lch);
807
808 /* Errata: On ES2.0 BUFFERING disable must be set.
809 * This will always fail on ES1.0 */
810 if (cpu_is_omap24xx()) {
811 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
812 }
813
814 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
815
816 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
817 }
818
819 void omap_stop_dma(int lch)
820 {
821 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
822 int next_lch, cur_lch = lch;
823 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
824
825 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
826 do {
827 /* The loop case: we've been here already */
828 if (dma_chan_link_map[cur_lch])
829 break;
830 /* Mark the current channel */
831 dma_chan_link_map[cur_lch] = 1;
832
833 disable_lnk(cur_lch);
834
835 next_lch = dma_chan[cur_lch].next_lch;
836 cur_lch = next_lch;
837 } while (next_lch != -1);
838
839 return;
840 }
841
842 /* Disable all interrupts on the channel */
843 if (cpu_class_is_omap1())
844 OMAP_DMA_CICR_REG(lch) = 0;
845
846 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
847 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
848 }
849
850 /*
851 * Allows changing the DMA callback function or data. This may be needed if
852 * the driver shares a single DMA channel for multiple dma triggers.
853 */
854 int omap_set_dma_callback(int lch,
855 void (* callback)(int lch, u16 ch_status, void *data),
856 void *data)
857 {
858 unsigned long flags;
859
860 if (lch < 0)
861 return -ENODEV;
862
863 spin_lock_irqsave(&dma_chan_lock, flags);
864 if (dma_chan[lch].dev_id == -1) {
865 printk(KERN_ERR "DMA callback for not set for free channel\n");
866 spin_unlock_irqrestore(&dma_chan_lock, flags);
867 return -EINVAL;
868 }
869 dma_chan[lch].callback = callback;
870 dma_chan[lch].data = data;
871 spin_unlock_irqrestore(&dma_chan_lock, flags);
872
873 return 0;
874 }
875
876 /*
877 * Returns current physical source address for the given DMA channel.
878 * If the channel is running the caller must disable interrupts prior calling
879 * this function and process the returned value before re-enabling interrupt to
880 * prevent races with the interrupt handler. Note that in continuous mode there
881 * is a chance for CSSA_L register overflow inbetween the two reads resulting
882 * in incorrect return value.
883 */
884 dma_addr_t omap_get_dma_src_pos(int lch)
885 {
886 dma_addr_t offset = 0;
887
888 if (cpu_class_is_omap1())
889 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
890 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
891
892 if (cpu_class_is_omap2())
893 offset = OMAP_DMA_CSAC_REG(lch);
894
895 return offset;
896 }
897
898 /*
899 * Returns current physical destination address for the given DMA channel.
900 * If the channel is running the caller must disable interrupts prior calling
901 * this function and process the returned value before re-enabling interrupt to
902 * prevent races with the interrupt handler. Note that in continuous mode there
903 * is a chance for CDSA_L register overflow inbetween the two reads resulting
904 * in incorrect return value.
905 */
906 dma_addr_t omap_get_dma_dst_pos(int lch)
907 {
908 dma_addr_t offset = 0;
909
910 if (cpu_class_is_omap1())
911 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
912 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
913
914 if (cpu_class_is_omap2())
915 offset = OMAP_DMA_CDAC_REG(lch);
916
917 return offset;
918 }
919
920 /*
921 * Returns current source transfer counting for the given DMA channel.
922 * Can be used to monitor the progress of a transfer inside a block.
923 * It must be called with disabled interrupts.
924 */
925 int omap_get_dma_src_addr_counter(int lch)
926 {
927 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
928 }
929
930 int omap_dma_running(void)
931 {
932 int lch;
933
934 /* Check if LCD DMA is running */
935 if (cpu_is_omap16xx())
936 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
937 return 1;
938
939 for (lch = 0; lch < dma_chan_count; lch++)
940 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
941 return 1;
942
943 return 0;
944 }
945
946 /*
947 * lch_queue DMA will start right after lch_head one is finished.
948 * For this DMA link to start, you still need to start (see omap_start_dma)
949 * the first one. That will fire up the entire queue.
950 */
951 void omap_dma_link_lch (int lch_head, int lch_queue)
952 {
953 if (omap_dma_in_1510_mode()) {
954 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
955 BUG();
956 return;
957 }
958
959 if ((dma_chan[lch_head].dev_id == -1) ||
960 (dma_chan[lch_queue].dev_id == -1)) {
961 printk(KERN_ERR "omap_dma: trying to link "
962 "non requested channels\n");
963 dump_stack();
964 }
965
966 dma_chan[lch_head].next_lch = lch_queue;
967 }
968
969 /*
970 * Once the DMA queue is stopped, we can destroy it.
971 */
972 void omap_dma_unlink_lch (int lch_head, int lch_queue)
973 {
974 if (omap_dma_in_1510_mode()) {
975 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
976 BUG();
977 return;
978 }
979
980 if (dma_chan[lch_head].next_lch != lch_queue ||
981 dma_chan[lch_head].next_lch == -1) {
982 printk(KERN_ERR "omap_dma: trying to unlink "
983 "non linked channels\n");
984 dump_stack();
985 }
986
987
988 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
989 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
990 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
991 "before unlinking\n");
992 dump_stack();
993 }
994
995 dma_chan[lch_head].next_lch = -1;
996 }
997
998 #ifndef CONFIG_ARCH_OMAP1
999 /* Create chain of DMA channesls */
1000 static void create_dma_lch_chain(int lch_head, int lch_queue)
1001 {
1002 u32 w;
1003
1004 /* Check if this is the first link in chain */
1005 if (dma_chan[lch_head].next_linked_ch == -1) {
1006 dma_chan[lch_head].next_linked_ch = lch_queue;
1007 dma_chan[lch_head].prev_linked_ch = lch_queue;
1008 dma_chan[lch_queue].next_linked_ch = lch_head;
1009 dma_chan[lch_queue].prev_linked_ch = lch_head;
1010 }
1011
1012 /* a link exists, link the new channel in circular chain */
1013 else {
1014 dma_chan[lch_queue].next_linked_ch =
1015 dma_chan[lch_head].next_linked_ch;
1016 dma_chan[lch_queue].prev_linked_ch = lch_head;
1017 dma_chan[lch_head].next_linked_ch = lch_queue;
1018 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1019 lch_queue;
1020 }
1021
1022 w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1023 w &= ~(0x0f);
1024 w |= lch_queue;
1025 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1026
1027 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1028 w &= ~(0x0f);
1029 w |= (dma_chan[lch_queue].next_linked_ch);
1030 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1031 }
1032
1033 /**
1034 * @brief omap_request_dma_chain : Request a chain of DMA channels
1035 *
1036 * @param dev_id - Device id using the dma channel
1037 * @param dev_name - Device name
1038 * @param callback - Call back function
1039 * @chain_id -
1040 * @no_of_chans - Number of channels requested
1041 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1042 * OMAP_DMA_DYNAMIC_CHAIN
1043 * @params - Channel parameters
1044 *
1045 * @return - Succes : 0
1046 * Failure: -EINVAL/-ENOMEM
1047 */
1048 int omap_request_dma_chain(int dev_id, const char *dev_name,
1049 void (*callback) (int chain_id, u16 ch_status,
1050 void *data),
1051 int *chain_id, int no_of_chans, int chain_mode,
1052 struct omap_dma_channel_params params)
1053 {
1054 int *channels;
1055 int i, err;
1056
1057 /* Is the chain mode valid ? */
1058 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1059 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1060 printk(KERN_ERR "Invalid chain mode requested\n");
1061 return -EINVAL;
1062 }
1063
1064 if (unlikely((no_of_chans < 1
1065 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
1066 printk(KERN_ERR "Invalid Number of channels requested\n");
1067 return -EINVAL;
1068 }
1069
1070 /* Allocate a queue to maintain the status of the channels
1071 * in the chain */
1072 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1073 if (channels == NULL) {
1074 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1075 return -ENOMEM;
1076 }
1077
1078 /* request and reserve DMA channels for the chain */
1079 for (i = 0; i < no_of_chans; i++) {
1080 err = omap_request_dma(dev_id, dev_name,
1081 callback, 0, &channels[i]);
1082 if (err < 0) {
1083 int j;
1084 for (j = 0; j < i; j++)
1085 omap_free_dma(channels[j]);
1086 kfree(channels);
1087 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1088 return err;
1089 }
1090 dma_chan[channels[i]].next_linked_ch = -1;
1091 dma_chan[channels[i]].prev_linked_ch = -1;
1092 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1093
1094 /*
1095 * Allowing client drivers to set common parameters now,
1096 * so that later only relevant (src_start, dest_start
1097 * and element count) can be set
1098 */
1099 omap_set_dma_params(channels[i], &params);
1100 }
1101
1102 *chain_id = channels[0];
1103 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1104 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1105 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1106 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1107
1108 for (i = 0; i < no_of_chans; i++)
1109 dma_chan[channels[i]].chain_id = *chain_id;
1110
1111 /* Reset the Queue pointers */
1112 OMAP_DMA_CHAIN_QINIT(*chain_id);
1113
1114 /* Set up the chain */
1115 if (no_of_chans == 1)
1116 create_dma_lch_chain(channels[0], channels[0]);
1117 else {
1118 for (i = 0; i < (no_of_chans - 1); i++)
1119 create_dma_lch_chain(channels[i], channels[i + 1]);
1120 }
1121 return 0;
1122 }
1123 EXPORT_SYMBOL(omap_request_dma_chain);
1124
1125 /**
1126 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1127 * params after setting it. Dont do this while dma is running!!
1128 *
1129 * @param chain_id - Chained logical channel id.
1130 * @param params
1131 *
1132 * @return - Success : 0
1133 * Failure : -EINVAL
1134 */
1135 int omap_modify_dma_chain_params(int chain_id,
1136 struct omap_dma_channel_params params)
1137 {
1138 int *channels;
1139 u32 i;
1140
1141 /* Check for input params */
1142 if (unlikely((chain_id < 0
1143 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1144 printk(KERN_ERR "Invalid chain id\n");
1145 return -EINVAL;
1146 }
1147
1148 /* Check if the chain exists */
1149 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1150 printk(KERN_ERR "Chain doesn't exists\n");
1151 return -EINVAL;
1152 }
1153 channels = dma_linked_lch[chain_id].linked_dmach_q;
1154
1155 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1156 /*
1157 * Allowing client drivers to set common parameters now,
1158 * so that later only relevant (src_start, dest_start
1159 * and element count) can be set
1160 */
1161 omap_set_dma_params(channels[i], &params);
1162 }
1163 return 0;
1164 }
1165 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1166
1167 /**
1168 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1169 *
1170 * @param chain_id
1171 *
1172 * @return - Success : 0
1173 * Failure : -EINVAL
1174 */
1175 int omap_free_dma_chain(int chain_id)
1176 {
1177 int *channels;
1178 u32 i;
1179
1180 /* Check for input params */
1181 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1182 printk(KERN_ERR "Invalid chain id\n");
1183 return -EINVAL;
1184 }
1185
1186 /* Check if the chain exists */
1187 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1188 printk(KERN_ERR "Chain doesn't exists\n");
1189 return -EINVAL;
1190 }
1191
1192 channels = dma_linked_lch[chain_id].linked_dmach_q;
1193 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1194 dma_chan[channels[i]].next_linked_ch = -1;
1195 dma_chan[channels[i]].prev_linked_ch = -1;
1196 dma_chan[channels[i]].chain_id = -1;
1197 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1198 omap_free_dma(channels[i]);
1199 }
1200
1201 kfree(channels);
1202
1203 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1204 dma_linked_lch[chain_id].chain_mode = -1;
1205 dma_linked_lch[chain_id].chain_state = -1;
1206 return (0);
1207 }
1208 EXPORT_SYMBOL(omap_free_dma_chain);
1209
1210 /**
1211 * @brief omap_dma_chain_status - Check if the chain is in
1212 * active / inactive state.
1213 * @param chain_id
1214 *
1215 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1216 * Failure : -EINVAL
1217 */
1218 int omap_dma_chain_status(int chain_id)
1219 {
1220 /* Check for input params */
1221 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1222 printk(KERN_ERR "Invalid chain id\n");
1223 return -EINVAL;
1224 }
1225
1226 /* Check if the chain exists */
1227 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1228 printk(KERN_ERR "Chain doesn't exists\n");
1229 return -EINVAL;
1230 }
1231 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1232 dma_linked_lch[chain_id].q_count);
1233
1234 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1235 return OMAP_DMA_CHAIN_INACTIVE;
1236 return OMAP_DMA_CHAIN_ACTIVE;
1237 }
1238 EXPORT_SYMBOL(omap_dma_chain_status);
1239
1240 /**
1241 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1242 * set the params and start the transfer.
1243 *
1244 * @param chain_id
1245 * @param src_start - buffer start address
1246 * @param dest_start - Dest address
1247 * @param elem_count
1248 * @param frame_count
1249 * @param callbk_data - channel callback parameter data.
1250 *
1251 * @return - Success : start_dma status
1252 * Failure: -EINVAL/-EBUSY
1253 */
1254 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1255 int elem_count, int frame_count, void *callbk_data)
1256 {
1257 int *channels;
1258 u32 w, lch;
1259 int start_dma = 0;
1260
1261 /* if buffer size is less than 1 then there is
1262 * no use of starting the chain */
1263 if (elem_count < 1) {
1264 printk(KERN_ERR "Invalid buffer size\n");
1265 return -EINVAL;
1266 }
1267
1268 /* Check for input params */
1269 if (unlikely((chain_id < 0
1270 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1271 printk(KERN_ERR "Invalid chain id\n");
1272 return -EINVAL;
1273 }
1274
1275 /* Check if the chain exists */
1276 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1277 printk(KERN_ERR "Chain doesn't exist\n");
1278 return -EINVAL;
1279 }
1280
1281 /* Check if all the channels in chain are in use */
1282 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1283 return -EBUSY;
1284
1285 /* Frame count may be negative in case of indexed transfers */
1286 channels = dma_linked_lch[chain_id].linked_dmach_q;
1287
1288 /* Get a free channel */
1289 lch = channels[dma_linked_lch[chain_id].q_tail];
1290
1291 /* Store the callback data */
1292 dma_chan[lch].data = callbk_data;
1293
1294 /* Increment the q_tail */
1295 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1296
1297 /* Set the params to the free channel */
1298 if (src_start != 0)
1299 OMAP2_DMA_CSSA_REG(lch) = src_start;
1300 if (dest_start != 0)
1301 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1302
1303 /* Write the buffer size */
1304 OMAP_DMA_CEN_REG(lch) = elem_count;
1305 OMAP_DMA_CFN_REG(lch) = frame_count;
1306
1307 /* If the chain is dynamically linked,
1308 * then we may have to start the chain if its not active */
1309 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1310
1311 /* In Dynamic chain, if the chain is not started,
1312 * queue the channel */
1313 if (dma_linked_lch[chain_id].chain_state ==
1314 DMA_CHAIN_NOTSTARTED) {
1315 /* Enable the link in previous channel */
1316 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1317 DMA_CH_QUEUED)
1318 enable_lnk(dma_chan[lch].prev_linked_ch);
1319 dma_chan[lch].state = DMA_CH_QUEUED;
1320 }
1321
1322 /* Chain is already started, make sure its active,
1323 * if not then start the chain */
1324 else {
1325 start_dma = 1;
1326
1327 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1328 DMA_CH_STARTED) {
1329 enable_lnk(dma_chan[lch].prev_linked_ch);
1330 dma_chan[lch].state = DMA_CH_QUEUED;
1331 start_dma = 0;
1332 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1333 (dma_chan[lch].prev_linked_ch)))) {
1334 disable_lnk(dma_chan[lch].
1335 prev_linked_ch);
1336 pr_debug("\n prev ch is stopped\n");
1337 start_dma = 1;
1338 }
1339 }
1340
1341 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1342 == DMA_CH_QUEUED) {
1343 enable_lnk(dma_chan[lch].prev_linked_ch);
1344 dma_chan[lch].state = DMA_CH_QUEUED;
1345 start_dma = 0;
1346 }
1347 omap_enable_channel_irq(lch);
1348
1349 w = OMAP_DMA_CCR_REG(lch);
1350
1351 if ((0 == (w & (1 << 24))))
1352 w &= ~(1 << 25);
1353 else
1354 w |= (1 << 25);
1355 if (start_dma == 1) {
1356 if (0 == (w & (1 << 7))) {
1357 w |= (1 << 7);
1358 dma_chan[lch].state = DMA_CH_STARTED;
1359 pr_debug("starting %d\n", lch);
1360 OMAP_DMA_CCR_REG(lch) = w;
1361 } else
1362 start_dma = 0;
1363 } else {
1364 if (0 == (w & (1 << 7)))
1365 OMAP_DMA_CCR_REG(lch) = w;
1366 }
1367 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1368 }
1369 }
1370 return start_dma;
1371 }
1372 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1373
1374 /**
1375 * @brief omap_start_dma_chain_transfers - Start the chain
1376 *
1377 * @param chain_id
1378 *
1379 * @return - Success : 0
1380 * Failure : -EINVAL/-EBUSY
1381 */
1382 int omap_start_dma_chain_transfers(int chain_id)
1383 {
1384 int *channels;
1385 u32 w, i;
1386
1387 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1388 printk(KERN_ERR "Invalid chain id\n");
1389 return -EINVAL;
1390 }
1391
1392 channels = dma_linked_lch[chain_id].linked_dmach_q;
1393
1394 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1395 printk(KERN_ERR "Chain is already started\n");
1396 return -EBUSY;
1397 }
1398
1399 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1400 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1401 i++) {
1402 enable_lnk(channels[i]);
1403 omap_enable_channel_irq(channels[i]);
1404 }
1405 } else {
1406 omap_enable_channel_irq(channels[0]);
1407 }
1408
1409 w = OMAP_DMA_CCR_REG(channels[0]);
1410 w |= (1 << 7);
1411 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1412 dma_chan[channels[0]].state = DMA_CH_STARTED;
1413
1414 if ((0 == (w & (1 << 24))))
1415 w &= ~(1 << 25);
1416 else
1417 w |= (1 << 25);
1418 OMAP_DMA_CCR_REG(channels[0]) = w;
1419
1420 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1421 return 0;
1422 }
1423 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1424
1425 /**
1426 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1427 *
1428 * @param chain_id
1429 *
1430 * @return - Success : 0
1431 * Failure : EINVAL
1432 */
1433 int omap_stop_dma_chain_transfers(int chain_id)
1434 {
1435 int *channels;
1436 u32 w, i;
1437 u32 sys_cf;
1438
1439 /* Check for input params */
1440 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1441 printk(KERN_ERR "Invalid chain id\n");
1442 return -EINVAL;
1443 }
1444
1445 /* Check if the chain exists */
1446 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1447 printk(KERN_ERR "Chain doesn't exists\n");
1448 return -EINVAL;
1449 }
1450 channels = dma_linked_lch[chain_id].linked_dmach_q;
1451
1452 /* DMA Errata:
1453 * Special programming model needed to disable DMA before end of block
1454 */
1455 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1456 w = sys_cf;
1457 /* Middle mode reg set no Standby */
1458 w &= ~((1 << 12)|(1 << 13));
1459 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1460
1461 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1462
1463 /* Stop the Channel transmission */
1464 w = OMAP_DMA_CCR_REG(channels[i]);
1465 w &= ~(1 << 7);
1466 OMAP_DMA_CCR_REG(channels[i]) = w;
1467
1468 /* Disable the link in all the channels */
1469 disable_lnk(channels[i]);
1470 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1471
1472 }
1473 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1474
1475 /* Reset the Queue pointers */
1476 OMAP_DMA_CHAIN_QINIT(chain_id);
1477
1478 /* Errata - put in the old value */
1479 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1480 return 0;
1481 }
1482 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1483
1484 /* Get the index of the ongoing DMA in chain */
1485 /**
1486 * @brief omap_get_dma_chain_index - Get the element and frame index
1487 * of the ongoing DMA in chain
1488 *
1489 * @param chain_id
1490 * @param ei - Element index
1491 * @param fi - Frame index
1492 *
1493 * @return - Success : 0
1494 * Failure : -EINVAL
1495 */
1496 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1497 {
1498 int lch;
1499 int *channels;
1500
1501 /* Check for input params */
1502 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1503 printk(KERN_ERR "Invalid chain id\n");
1504 return -EINVAL;
1505 }
1506
1507 /* Check if the chain exists */
1508 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1509 printk(KERN_ERR "Chain doesn't exists\n");
1510 return -EINVAL;
1511 }
1512 if ((!ei) || (!fi))
1513 return -EINVAL;
1514
1515 channels = dma_linked_lch[chain_id].linked_dmach_q;
1516
1517 /* Get the current channel */
1518 lch = channels[dma_linked_lch[chain_id].q_head];
1519
1520 *ei = OMAP2_DMA_CCEN_REG(lch);
1521 *fi = OMAP2_DMA_CCFN_REG(lch);
1522
1523 return 0;
1524 }
1525 EXPORT_SYMBOL(omap_get_dma_chain_index);
1526
1527 /**
1528 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1529 * ongoing DMA in chain
1530 *
1531 * @param chain_id
1532 *
1533 * @return - Success : Destination position
1534 * Failure : -EINVAL
1535 */
1536 int omap_get_dma_chain_dst_pos(int chain_id)
1537 {
1538 int lch;
1539 int *channels;
1540
1541 /* Check for input params */
1542 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1543 printk(KERN_ERR "Invalid chain id\n");
1544 return -EINVAL;
1545 }
1546
1547 /* Check if the chain exists */
1548 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1549 printk(KERN_ERR "Chain doesn't exists\n");
1550 return -EINVAL;
1551 }
1552
1553 channels = dma_linked_lch[chain_id].linked_dmach_q;
1554
1555 /* Get the current channel */
1556 lch = channels[dma_linked_lch[chain_id].q_head];
1557
1558 return (OMAP_DMA_CDAC_REG(lch));
1559 }
1560 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1561
1562 /**
1563 * @brief omap_get_dma_chain_src_pos - Get the source position
1564 * of the ongoing DMA in chain
1565 * @param chain_id
1566 *
1567 * @return - Success : Destination position
1568 * Failure : -EINVAL
1569 */
1570 int omap_get_dma_chain_src_pos(int chain_id)
1571 {
1572 int lch;
1573 int *channels;
1574
1575 /* Check for input params */
1576 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1577 printk(KERN_ERR "Invalid chain id\n");
1578 return -EINVAL;
1579 }
1580
1581 /* Check if the chain exists */
1582 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1583 printk(KERN_ERR "Chain doesn't exists\n");
1584 return -EINVAL;
1585 }
1586
1587 channels = dma_linked_lch[chain_id].linked_dmach_q;
1588
1589 /* Get the current channel */
1590 lch = channels[dma_linked_lch[chain_id].q_head];
1591
1592 return (OMAP_DMA_CSAC_REG(lch));
1593 }
1594 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1595 #endif
1596
1597 /*----------------------------------------------------------------------------*/
1598
1599 #ifdef CONFIG_ARCH_OMAP1
1600
1601 static int omap1_dma_handle_ch(int ch)
1602 {
1603 u16 csr;
1604
1605 if (enable_1510_mode && ch >= 6) {
1606 csr = dma_chan[ch].saved_csr;
1607 dma_chan[ch].saved_csr = 0;
1608 } else
1609 csr = OMAP_DMA_CSR_REG(ch);
1610 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1611 dma_chan[ch + 6].saved_csr = csr >> 7;
1612 csr &= 0x7f;
1613 }
1614 if ((csr & 0x3f) == 0)
1615 return 0;
1616 if (unlikely(dma_chan[ch].dev_id == -1)) {
1617 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1618 "%d (CSR %04x)\n", ch, csr);
1619 return 0;
1620 }
1621 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1622 printk(KERN_WARNING "DMA timeout with device %d\n",
1623 dma_chan[ch].dev_id);
1624 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1625 printk(KERN_WARNING "DMA synchronization event drop occurred "
1626 "with device %d\n", dma_chan[ch].dev_id);
1627 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1628 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1629 if (likely(dma_chan[ch].callback != NULL))
1630 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1631 return 1;
1632 }
1633
1634 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1635 {
1636 int ch = ((int) dev_id) - 1;
1637 int handled = 0;
1638
1639 for (;;) {
1640 int handled_now = 0;
1641
1642 handled_now += omap1_dma_handle_ch(ch);
1643 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1644 handled_now += omap1_dma_handle_ch(ch + 6);
1645 if (!handled_now)
1646 break;
1647 handled += handled_now;
1648 }
1649
1650 return handled ? IRQ_HANDLED : IRQ_NONE;
1651 }
1652
1653 #else
1654 #define omap1_dma_irq_handler NULL
1655 #endif
1656
1657 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1658
1659 static int omap2_dma_handle_ch(int ch)
1660 {
1661 u32 status = OMAP_DMA_CSR_REG(ch);
1662
1663 if (!status) {
1664 if (printk_ratelimit())
1665 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
1666 return 0;
1667 }
1668 if (unlikely(dma_chan[ch].dev_id == -1)) {
1669 if (printk_ratelimit())
1670 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1671 "channel %d\n", status, ch);
1672 return 0;
1673 }
1674 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1675 printk(KERN_INFO
1676 "DMA synchronization event drop occurred with device "
1677 "%d\n", dma_chan[ch].dev_id);
1678 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1679 printk(KERN_INFO "DMA transaction error with device %d\n",
1680 dma_chan[ch].dev_id);
1681 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1682 printk(KERN_INFO "DMA secure error with device %d\n",
1683 dma_chan[ch].dev_id);
1684 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1685 printk(KERN_INFO "DMA misaligned error with device %d\n",
1686 dma_chan[ch].dev_id);
1687
1688 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
1689 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1690
1691 /* If the ch is not chained then chain_id will be -1 */
1692 if (dma_chan[ch].chain_id != -1) {
1693 int chain_id = dma_chan[ch].chain_id;
1694 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1695 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1696 dma_chan[dma_chan[ch].next_linked_ch].state =
1697 DMA_CH_STARTED;
1698 if (dma_linked_lch[chain_id].chain_mode ==
1699 OMAP_DMA_DYNAMIC_CHAIN)
1700 disable_lnk(ch);
1701
1702 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1703 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1704
1705 status = OMAP_DMA_CSR_REG(ch);
1706 }
1707
1708 if (likely(dma_chan[ch].callback != NULL)) {
1709 if (dma_chan[ch].chain_id != -1)
1710 dma_chan[ch].callback(dma_chan[ch].chain_id, status,
1711 dma_chan[ch].data);
1712 else
1713 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1714
1715 }
1716
1717 OMAP_DMA_CSR_REG(ch) = status;
1718
1719 return 0;
1720 }
1721
1722 /* STATUS register count is from 1-32 while our is 0-31 */
1723 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1724 {
1725 u32 val;
1726 int i;
1727
1728 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
1729 if (val == 0) {
1730 if (printk_ratelimit())
1731 printk(KERN_WARNING "Spurious DMA IRQ\n");
1732 return IRQ_HANDLED;
1733 }
1734 for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) {
1735 if (val & 1)
1736 omap2_dma_handle_ch(i);
1737 val >>= 1;
1738 }
1739
1740 return IRQ_HANDLED;
1741 }
1742
1743 static struct irqaction omap24xx_dma_irq = {
1744 .name = "DMA",
1745 .handler = omap2_dma_irq_handler,
1746 .flags = IRQF_DISABLED
1747 };
1748
1749 #else
1750 static struct irqaction omap24xx_dma_irq;
1751 #endif
1752
1753 /*----------------------------------------------------------------------------*/
1754
1755 static struct lcd_dma_info {
1756 spinlock_t lock;
1757 int reserved;
1758 void (* callback)(u16 status, void *data);
1759 void *cb_data;
1760
1761 int active;
1762 unsigned long addr, size;
1763 int rotate, data_type, xres, yres;
1764 int vxres;
1765 int mirror;
1766 int xscale, yscale;
1767 int ext_ctrl;
1768 int src_port;
1769 int single_transfer;
1770 } lcd_dma;
1771
1772 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1773 int data_type)
1774 {
1775 lcd_dma.addr = addr;
1776 lcd_dma.data_type = data_type;
1777 lcd_dma.xres = fb_xres;
1778 lcd_dma.yres = fb_yres;
1779 }
1780
1781 void omap_set_lcd_dma_src_port(int port)
1782 {
1783 lcd_dma.src_port = port;
1784 }
1785
1786 void omap_set_lcd_dma_ext_controller(int external)
1787 {
1788 lcd_dma.ext_ctrl = external;
1789 }
1790
1791 void omap_set_lcd_dma_single_transfer(int single)
1792 {
1793 lcd_dma.single_transfer = single;
1794 }
1795
1796
1797 void omap_set_lcd_dma_b1_rotation(int rotate)
1798 {
1799 if (omap_dma_in_1510_mode()) {
1800 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1801 BUG();
1802 return;
1803 }
1804 lcd_dma.rotate = rotate;
1805 }
1806
1807 void omap_set_lcd_dma_b1_mirror(int mirror)
1808 {
1809 if (omap_dma_in_1510_mode()) {
1810 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1811 BUG();
1812 }
1813 lcd_dma.mirror = mirror;
1814 }
1815
1816 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1817 {
1818 if (omap_dma_in_1510_mode()) {
1819 printk(KERN_ERR "DMA virtual resulotion is not supported "
1820 "in 1510 mode\n");
1821 BUG();
1822 }
1823 lcd_dma.vxres = vxres;
1824 }
1825
1826 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1827 {
1828 if (omap_dma_in_1510_mode()) {
1829 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1830 BUG();
1831 }
1832 lcd_dma.xscale = xscale;
1833 lcd_dma.yscale = yscale;
1834 }
1835
1836 static void set_b1_regs(void)
1837 {
1838 unsigned long top, bottom;
1839 int es;
1840 u16 w;
1841 unsigned long en, fn;
1842 long ei, fi;
1843 unsigned long vxres;
1844 unsigned int xscale, yscale;
1845
1846 switch (lcd_dma.data_type) {
1847 case OMAP_DMA_DATA_TYPE_S8:
1848 es = 1;
1849 break;
1850 case OMAP_DMA_DATA_TYPE_S16:
1851 es = 2;
1852 break;
1853 case OMAP_DMA_DATA_TYPE_S32:
1854 es = 4;
1855 break;
1856 default:
1857 BUG();
1858 return;
1859 }
1860
1861 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1862 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1863 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1864 BUG_ON(vxres < lcd_dma.xres);
1865 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1866 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1867 switch (lcd_dma.rotate) {
1868 case 0:
1869 if (!lcd_dma.mirror) {
1870 top = PIXADDR(0, 0);
1871 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1872 /* 1510 DMA requires the bottom address to be 2 more
1873 * than the actual last memory access location. */
1874 if (omap_dma_in_1510_mode() &&
1875 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1876 bottom += 2;
1877 ei = PIXSTEP(0, 0, 1, 0);
1878 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1879 } else {
1880 top = PIXADDR(lcd_dma.xres - 1, 0);
1881 bottom = PIXADDR(0, lcd_dma.yres - 1);
1882 ei = PIXSTEP(1, 0, 0, 0);
1883 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1884 }
1885 en = lcd_dma.xres;
1886 fn = lcd_dma.yres;
1887 break;
1888 case 90:
1889 if (!lcd_dma.mirror) {
1890 top = PIXADDR(0, lcd_dma.yres - 1);
1891 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1892 ei = PIXSTEP(0, 1, 0, 0);
1893 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1894 } else {
1895 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1896 bottom = PIXADDR(0, 0);
1897 ei = PIXSTEP(0, 1, 0, 0);
1898 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1899 }
1900 en = lcd_dma.yres;
1901 fn = lcd_dma.xres;
1902 break;
1903 case 180:
1904 if (!lcd_dma.mirror) {
1905 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1906 bottom = PIXADDR(0, 0);
1907 ei = PIXSTEP(1, 0, 0, 0);
1908 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1909 } else {
1910 top = PIXADDR(0, lcd_dma.yres - 1);
1911 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1912 ei = PIXSTEP(0, 0, 1, 0);
1913 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1914 }
1915 en = lcd_dma.xres;
1916 fn = lcd_dma.yres;
1917 break;
1918 case 270:
1919 if (!lcd_dma.mirror) {
1920 top = PIXADDR(lcd_dma.xres - 1, 0);
1921 bottom = PIXADDR(0, lcd_dma.yres - 1);
1922 ei = PIXSTEP(0, 0, 0, 1);
1923 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1924 } else {
1925 top = PIXADDR(0, 0);
1926 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1927 ei = PIXSTEP(0, 0, 0, 1);
1928 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1929 }
1930 en = lcd_dma.yres;
1931 fn = lcd_dma.xres;
1932 break;
1933 default:
1934 BUG();
1935 return; /* Suppress warning about uninitialized vars */
1936 }
1937
1938 if (omap_dma_in_1510_mode()) {
1939 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1940 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1941 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1942 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1943
1944 return;
1945 }
1946
1947 /* 1610 regs */
1948 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1949 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1950 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1951 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1952
1953 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1954 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1955
1956 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1957 w &= ~0x03;
1958 w |= lcd_dma.data_type;
1959 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1960
1961 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1962 /* Always set the source port as SDRAM for now*/
1963 w &= ~(0x03 << 6);
1964 if (lcd_dma.callback != NULL)
1965 w |= 1 << 1; /* Block interrupt enable */
1966 else
1967 w &= ~(1 << 1);
1968 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1969
1970 if (!(lcd_dma.rotate || lcd_dma.mirror ||
1971 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1972 return;
1973
1974 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1975 /* Set the double-indexed addressing mode */
1976 w |= (0x03 << 12);
1977 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1978
1979 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1980 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1981 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1982 }
1983
1984 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1985 {
1986 u16 w;
1987
1988 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1989 if (unlikely(!(w & (1 << 3)))) {
1990 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1991 return IRQ_NONE;
1992 }
1993 /* Ack the IRQ */
1994 w |= (1 << 3);
1995 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1996 lcd_dma.active = 0;
1997 if (lcd_dma.callback != NULL)
1998 lcd_dma.callback(w, lcd_dma.cb_data);
1999
2000 return IRQ_HANDLED;
2001 }
2002
2003 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2004 void *data)
2005 {
2006 spin_lock_irq(&lcd_dma.lock);
2007 if (lcd_dma.reserved) {
2008 spin_unlock_irq(&lcd_dma.lock);
2009 printk(KERN_ERR "LCD DMA channel already reserved\n");
2010 BUG();
2011 return -EBUSY;
2012 }
2013 lcd_dma.reserved = 1;
2014 spin_unlock_irq(&lcd_dma.lock);
2015 lcd_dma.callback = callback;
2016 lcd_dma.cb_data = data;
2017 lcd_dma.active = 0;
2018 lcd_dma.single_transfer = 0;
2019 lcd_dma.rotate = 0;
2020 lcd_dma.vxres = 0;
2021 lcd_dma.mirror = 0;
2022 lcd_dma.xscale = 0;
2023 lcd_dma.yscale = 0;
2024 lcd_dma.ext_ctrl = 0;
2025 lcd_dma.src_port = 0;
2026
2027 return 0;
2028 }
2029
2030 void omap_free_lcd_dma(void)
2031 {
2032 spin_lock(&lcd_dma.lock);
2033 if (!lcd_dma.reserved) {
2034 spin_unlock(&lcd_dma.lock);
2035 printk(KERN_ERR "LCD DMA is not reserved\n");
2036 BUG();
2037 return;
2038 }
2039 if (!enable_1510_mode)
2040 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2041 OMAP1610_DMA_LCD_CCR);
2042 lcd_dma.reserved = 0;
2043 spin_unlock(&lcd_dma.lock);
2044 }
2045
2046 void omap_enable_lcd_dma(void)
2047 {
2048 u16 w;
2049
2050 /* Set the Enable bit only if an external controller is
2051 * connected. Otherwise the OMAP internal controller will
2052 * start the transfer when it gets enabled.
2053 */
2054 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2055 return;
2056
2057 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2058 w |= 1 << 8;
2059 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2060
2061 lcd_dma.active = 1;
2062
2063 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2064 w |= 1 << 7;
2065 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2066 }
2067
2068 void omap_setup_lcd_dma(void)
2069 {
2070 BUG_ON(lcd_dma.active);
2071 if (!enable_1510_mode) {
2072 /* Set some reasonable defaults */
2073 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2074 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2075 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2076 }
2077 set_b1_regs();
2078 if (!enable_1510_mode) {
2079 u16 w;
2080
2081 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2082 /* If DMA was already active set the end_prog bit to have
2083 * the programmed register set loaded into the active
2084 * register set.
2085 */
2086 w |= 1 << 11; /* End_prog */
2087 if (!lcd_dma.single_transfer)
2088 w |= (3 << 8); /* Auto_init, repeat */
2089 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2090 }
2091 }
2092
2093 void omap_stop_lcd_dma(void)
2094 {
2095 u16 w;
2096
2097 lcd_dma.active = 0;
2098 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2099 return;
2100
2101 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2102 w &= ~(1 << 7);
2103 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2104
2105 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2106 w &= ~(1 << 8);
2107 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2108 }
2109
2110 /*----------------------------------------------------------------------------*/
2111
2112 static int __init omap_init_dma(void)
2113 {
2114 int ch, r;
2115
2116 if (cpu_is_omap15xx()) {
2117 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2118 dma_chan_count = 9;
2119 enable_1510_mode = 1;
2120 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2121 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2122 omap_readw(OMAP_DMA_HW_ID));
2123 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2124 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
2125 omap_readw(OMAP_DMA_CAPS_0_L),
2126 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
2127 omap_readw(OMAP_DMA_CAPS_1_L),
2128 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
2129 omap_readw(OMAP_DMA_CAPS_4));
2130 if (!enable_1510_mode) {
2131 u16 w;
2132
2133 /* Disable OMAP 3.0/3.1 compatibility mode. */
2134 w = omap_readw(OMAP_DMA_GSCR);
2135 w |= 1 << 3;
2136 omap_writew(w, OMAP_DMA_GSCR);
2137 dma_chan_count = 16;
2138 } else
2139 dma_chan_count = 9;
2140 if (cpu_is_omap16xx()) {
2141 u16 w;
2142
2143 /* this would prevent OMAP sleep */
2144 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2145 w &= ~(1 << 8);
2146 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2147 }
2148 } else if (cpu_class_is_omap2()) {
2149 u8 revision = omap_readb(OMAP_DMA4_REVISION);
2150 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2151 revision >> 4, revision & 0xf);
2152 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
2153 } else {
2154 dma_chan_count = 0;
2155 return 0;
2156 }
2157
2158 memset(&lcd_dma, 0, sizeof(lcd_dma));
2159 spin_lock_init(&lcd_dma.lock);
2160 spin_lock_init(&dma_chan_lock);
2161 memset(&dma_chan, 0, sizeof(dma_chan));
2162
2163 for (ch = 0; ch < dma_chan_count; ch++) {
2164 omap_clear_dma(ch);
2165 dma_chan[ch].dev_id = -1;
2166 dma_chan[ch].next_lch = -1;
2167
2168 if (ch >= 6 && enable_1510_mode)
2169 continue;
2170
2171 if (cpu_class_is_omap1()) {
2172 /* request_irq() doesn't like dev_id (ie. ch) being
2173 * zero, so we have to kludge around this. */
2174 r = request_irq(omap1_dma_irq[ch],
2175 omap1_dma_irq_handler, 0, "DMA",
2176 (void *) (ch + 1));
2177 if (r != 0) {
2178 int i;
2179
2180 printk(KERN_ERR "unable to request IRQ %d "
2181 "for DMA (error %d)\n",
2182 omap1_dma_irq[ch], r);
2183 for (i = 0; i < ch; i++)
2184 free_irq(omap1_dma_irq[i],
2185 (void *) (i + 1));
2186 return r;
2187 }
2188 }
2189 }
2190
2191 if (cpu_is_omap2430() || cpu_is_omap34xx())
2192 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2193 DMA_DEFAULT_FIFO_DEPTH, 0);
2194
2195 if (cpu_class_is_omap2())
2196 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2197
2198 /* FIXME: Update LCD DMA to work on 24xx */
2199 if (cpu_class_is_omap1()) {
2200 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2201 "LCD DMA", NULL);
2202 if (r != 0) {
2203 int i;
2204
2205 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2206 "(error %d)\n", r);
2207 for (i = 0; i < dma_chan_count; i++)
2208 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2209 return r;
2210 }
2211 }
2212
2213 return 0;
2214 }
2215
2216 arch_initcall(omap_init_dma);
2217
2218 EXPORT_SYMBOL(omap_get_dma_src_pos);
2219 EXPORT_SYMBOL(omap_get_dma_dst_pos);
2220 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2221 EXPORT_SYMBOL(omap_clear_dma);
2222 EXPORT_SYMBOL(omap_set_dma_priority);
2223 EXPORT_SYMBOL(omap_request_dma);
2224 EXPORT_SYMBOL(omap_free_dma);
2225 EXPORT_SYMBOL(omap_start_dma);
2226 EXPORT_SYMBOL(omap_stop_dma);
2227 EXPORT_SYMBOL(omap_set_dma_callback);
2228 EXPORT_SYMBOL(omap_enable_dma_irq);
2229 EXPORT_SYMBOL(omap_disable_dma_irq);
2230
2231 EXPORT_SYMBOL(omap_set_dma_transfer_params);
2232 EXPORT_SYMBOL(omap_set_dma_color_mode);
2233 EXPORT_SYMBOL(omap_set_dma_write_mode);
2234
2235 EXPORT_SYMBOL(omap_set_dma_src_params);
2236 EXPORT_SYMBOL(omap_set_dma_src_index);
2237 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2238 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2239
2240 EXPORT_SYMBOL(omap_set_dma_dest_params);
2241 EXPORT_SYMBOL(omap_set_dma_dest_index);
2242 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2243 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2244
2245 EXPORT_SYMBOL(omap_set_dma_params);
2246
2247 EXPORT_SYMBOL(omap_dma_link_lch);
2248 EXPORT_SYMBOL(omap_dma_unlink_lch);
2249
2250 EXPORT_SYMBOL(omap_request_lcd_dma);
2251 EXPORT_SYMBOL(omap_free_lcd_dma);
2252 EXPORT_SYMBOL(omap_enable_lcd_dma);
2253 EXPORT_SYMBOL(omap_setup_lcd_dma);
2254 EXPORT_SYMBOL(omap_stop_lcd_dma);
2255 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2256 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2257 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2258 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2259 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2260 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2261 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2262
Linux kernel - Deliverables
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