2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
44 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
45 * channels that an instance of the SDMA IP block can support. Used
46 * to size arrays. (The actual maximum on a particular SoC may be less
47 * than this -- for example, OMAP1 SDMA instances only support 17 logical
50 #define MAX_LOGICAL_DMA_CH_COUNT 32
54 #ifndef CONFIG_ARCH_OMAP1
55 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
56 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
59 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
62 #define OMAP_DMA_ACTIVE 0x01
63 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
65 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
67 static struct omap_system_dma_plat_info
*p
;
68 static struct omap_dma_dev_attr
*d
;
70 static int enable_1510_mode
;
73 static struct omap_dma_global_context_registers
{
75 u32 dma_ocp_sysconfig
;
77 } omap_dma_global_context
;
79 struct dma_link_info
{
81 int no_of_lchs_linked
;
92 static struct dma_link_info
*dma_linked_lch
;
94 #ifndef CONFIG_ARCH_OMAP1
96 /* Chain handling macros */
97 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
99 dma_linked_lch[chain_id].q_head = \
100 dma_linked_lch[chain_id].q_tail = \
101 dma_linked_lch[chain_id].q_count = 0; \
103 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
104 (dma_linked_lch[chain_id].no_of_lchs_linked == \
105 dma_linked_lch[chain_id].q_count)
106 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
108 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
109 dma_linked_lch[chain_id].q_count) \
111 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
112 (0 == dma_linked_lch[chain_id].q_count)
113 #define __OMAP_DMA_CHAIN_INCQ(end) \
114 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
115 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
117 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
118 dma_linked_lch[chain_id].q_count--; \
121 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
123 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
124 dma_linked_lch[chain_id].q_count++; \
128 static int dma_lch_count
;
129 static int dma_chan_count
;
130 static int omap_dma_reserve_channels
;
132 static spinlock_t dma_chan_lock
;
133 static struct omap_dma_lch
*dma_chan
;
135 static inline void disable_lnk(int lch
);
136 static void omap_disable_channel_irq(int lch
);
137 static inline void omap_enable_channel_irq(int lch
);
139 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
142 #ifdef CONFIG_ARCH_OMAP15XX
143 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144 static int omap_dma_in_1510_mode(void)
146 return enable_1510_mode
;
149 #define omap_dma_in_1510_mode() 0
152 #ifdef CONFIG_ARCH_OMAP1
153 static inline int get_gdma_dev(int req
)
155 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
156 int shift
= ((req
- 1) % 5) * 6;
158 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
161 static inline void set_gdma_dev(int req
, int dev
)
163 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
164 int shift
= ((req
- 1) % 5) * 6;
168 l
&= ~(0x3f << shift
);
169 l
|= (dev
- 1) << shift
;
173 #define set_gdma_dev(req, dev) do {} while (0)
174 #define omap_readl(reg) 0
175 #define omap_writel(val, reg) do {} while (0)
178 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
183 if (cpu_class_is_omap1()) {
185 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
186 reg
= OMAP_TC_OCPT1_PRIOR
;
188 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
189 reg
= OMAP_TC_OCPT2_PRIOR
;
191 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
192 reg
= OMAP_TC_EMIFF_PRIOR
;
194 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
195 reg
= OMAP_TC_EMIFS_PRIOR
;
203 l
|= (priority
& 0xf) << 8;
207 if (cpu_class_is_omap2()) {
210 ccr
= p
->dma_read(CCR
, lch
);
215 p
->dma_write(ccr
, CCR
, lch
);
218 EXPORT_SYMBOL(omap_set_dma_priority
);
220 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
221 int frame_count
, int sync_mode
,
222 int dma_trigger
, int src_or_dst_synch
)
226 l
= p
->dma_read(CSDP
, lch
);
229 p
->dma_write(l
, CSDP
, lch
);
231 if (cpu_class_is_omap1()) {
234 ccr
= p
->dma_read(CCR
, lch
);
236 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
238 p
->dma_write(ccr
, CCR
, lch
);
240 ccr
= p
->dma_read(CCR2
, lch
);
242 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
244 p
->dma_write(ccr
, CCR2
, lch
);
247 if (cpu_class_is_omap2() && dma_trigger
) {
250 val
= p
->dma_read(CCR
, lch
);
252 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
253 val
&= ~((1 << 23) | (3 << 19) | 0x1f);
254 val
|= (dma_trigger
& ~0x1f) << 14;
255 val
|= dma_trigger
& 0x1f;
257 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
262 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
267 if (src_or_dst_synch
== OMAP_DMA_DST_SYNC_PREFETCH
) {
268 val
&= ~(1 << 24); /* dest synch */
269 val
|= (1 << 23); /* Prefetch */
270 } else if (src_or_dst_synch
) {
271 val
|= 1 << 24; /* source synch */
273 val
&= ~(1 << 24); /* dest synch */
275 p
->dma_write(val
, CCR
, lch
);
278 p
->dma_write(elem_count
, CEN
, lch
);
279 p
->dma_write(frame_count
, CFN
, lch
);
281 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
283 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
285 BUG_ON(omap_dma_in_1510_mode());
287 if (cpu_class_is_omap1()) {
290 w
= p
->dma_read(CCR2
, lch
);
294 case OMAP_DMA_CONSTANT_FILL
:
297 case OMAP_DMA_TRANSPARENT_COPY
:
300 case OMAP_DMA_COLOR_DIS
:
305 p
->dma_write(w
, CCR2
, lch
);
307 w
= p
->dma_read(LCH_CTRL
, lch
);
309 /* Default is channel type 2D */
311 p
->dma_write(color
, COLOR
, lch
);
312 w
|= 1; /* Channel type G */
314 p
->dma_write(w
, LCH_CTRL
, lch
);
317 if (cpu_class_is_omap2()) {
320 val
= p
->dma_read(CCR
, lch
);
321 val
&= ~((1 << 17) | (1 << 16));
324 case OMAP_DMA_CONSTANT_FILL
:
327 case OMAP_DMA_TRANSPARENT_COPY
:
330 case OMAP_DMA_COLOR_DIS
:
335 p
->dma_write(val
, CCR
, lch
);
338 p
->dma_write(color
, COLOR
, lch
);
341 EXPORT_SYMBOL(omap_set_dma_color_mode
);
343 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
345 if (cpu_class_is_omap2()) {
348 csdp
= p
->dma_read(CSDP
, lch
);
349 csdp
&= ~(0x3 << 16);
350 csdp
|= (mode
<< 16);
351 p
->dma_write(csdp
, CSDP
, lch
);
354 EXPORT_SYMBOL(omap_set_dma_write_mode
);
356 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
358 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
361 l
= p
->dma_read(LCH_CTRL
, lch
);
364 p
->dma_write(l
, LCH_CTRL
, lch
);
367 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
369 /* Note that src_port is only for omap1 */
370 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
371 unsigned long src_start
,
372 int src_ei
, int src_fi
)
376 if (cpu_class_is_omap1()) {
379 w
= p
->dma_read(CSDP
, lch
);
382 p
->dma_write(w
, CSDP
, lch
);
385 l
= p
->dma_read(CCR
, lch
);
387 l
|= src_amode
<< 12;
388 p
->dma_write(l
, CCR
, lch
);
390 p
->dma_write(src_start
, CSSA
, lch
);
392 p
->dma_write(src_ei
, CSEI
, lch
);
393 p
->dma_write(src_fi
, CSFI
, lch
);
395 EXPORT_SYMBOL(omap_set_dma_src_params
);
397 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
399 omap_set_dma_transfer_params(lch
, params
->data_type
,
400 params
->elem_count
, params
->frame_count
,
401 params
->sync_mode
, params
->trigger
,
402 params
->src_or_dst_synch
);
403 omap_set_dma_src_params(lch
, params
->src_port
,
404 params
->src_amode
, params
->src_start
,
405 params
->src_ei
, params
->src_fi
);
407 omap_set_dma_dest_params(lch
, params
->dst_port
,
408 params
->dst_amode
, params
->dst_start
,
409 params
->dst_ei
, params
->dst_fi
);
410 if (params
->read_prio
|| params
->write_prio
)
411 omap_dma_set_prio_lch(lch
, params
->read_prio
,
414 EXPORT_SYMBOL(omap_set_dma_params
);
416 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
418 if (cpu_class_is_omap2())
421 p
->dma_write(eidx
, CSEI
, lch
);
422 p
->dma_write(fidx
, CSFI
, lch
);
424 EXPORT_SYMBOL(omap_set_dma_src_index
);
426 void omap_set_dma_src_data_pack(int lch
, int enable
)
430 l
= p
->dma_read(CSDP
, lch
);
434 p
->dma_write(l
, CSDP
, lch
);
436 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
438 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
440 unsigned int burst
= 0;
443 l
= p
->dma_read(CSDP
, lch
);
446 switch (burst_mode
) {
447 case OMAP_DMA_DATA_BURST_DIS
:
449 case OMAP_DMA_DATA_BURST_4
:
450 if (cpu_class_is_omap2())
455 case OMAP_DMA_DATA_BURST_8
:
456 if (cpu_class_is_omap2()) {
461 * not supported by current hardware on OMAP1
465 case OMAP_DMA_DATA_BURST_16
:
466 if (cpu_class_is_omap2()) {
471 * OMAP1 don't support burst 16
479 p
->dma_write(l
, CSDP
, lch
);
481 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
483 /* Note that dest_port is only for OMAP1 */
484 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
485 unsigned long dest_start
,
486 int dst_ei
, int dst_fi
)
490 if (cpu_class_is_omap1()) {
491 l
= p
->dma_read(CSDP
, lch
);
494 p
->dma_write(l
, CSDP
, lch
);
497 l
= p
->dma_read(CCR
, lch
);
499 l
|= dest_amode
<< 14;
500 p
->dma_write(l
, CCR
, lch
);
502 p
->dma_write(dest_start
, CDSA
, lch
);
504 p
->dma_write(dst_ei
, CDEI
, lch
);
505 p
->dma_write(dst_fi
, CDFI
, lch
);
507 EXPORT_SYMBOL(omap_set_dma_dest_params
);
509 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
511 if (cpu_class_is_omap2())
514 p
->dma_write(eidx
, CDEI
, lch
);
515 p
->dma_write(fidx
, CDFI
, lch
);
517 EXPORT_SYMBOL(omap_set_dma_dest_index
);
519 void omap_set_dma_dest_data_pack(int lch
, int enable
)
523 l
= p
->dma_read(CSDP
, lch
);
527 p
->dma_write(l
, CSDP
, lch
);
529 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
531 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
533 unsigned int burst
= 0;
536 l
= p
->dma_read(CSDP
, lch
);
539 switch (burst_mode
) {
540 case OMAP_DMA_DATA_BURST_DIS
:
542 case OMAP_DMA_DATA_BURST_4
:
543 if (cpu_class_is_omap2())
548 case OMAP_DMA_DATA_BURST_8
:
549 if (cpu_class_is_omap2())
554 case OMAP_DMA_DATA_BURST_16
:
555 if (cpu_class_is_omap2()) {
560 * OMAP1 don't support burst 16
564 printk(KERN_ERR
"Invalid DMA burst mode\n");
569 p
->dma_write(l
, CSDP
, lch
);
571 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
573 static inline void omap_enable_channel_irq(int lch
)
576 if (cpu_class_is_omap1())
577 p
->dma_read(CSR
, lch
);
579 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
581 /* Enable some nice interrupts. */
582 p
->dma_write(dma_chan
[lch
].enabled_irqs
, CICR
, lch
);
585 static inline void omap_disable_channel_irq(int lch
)
587 /* disable channel interrupts */
588 p
->dma_write(0, CICR
, lch
);
590 if (cpu_class_is_omap1())
591 p
->dma_read(CSR
, lch
);
593 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
596 void omap_enable_dma_irq(int lch
, u16 bits
)
598 dma_chan
[lch
].enabled_irqs
|= bits
;
600 EXPORT_SYMBOL(omap_enable_dma_irq
);
602 void omap_disable_dma_irq(int lch
, u16 bits
)
604 dma_chan
[lch
].enabled_irqs
&= ~bits
;
606 EXPORT_SYMBOL(omap_disable_dma_irq
);
608 static inline void enable_lnk(int lch
)
612 l
= p
->dma_read(CLNK_CTRL
, lch
);
614 if (cpu_class_is_omap1())
617 /* Set the ENABLE_LNK bits */
618 if (dma_chan
[lch
].next_lch
!= -1)
619 l
= dma_chan
[lch
].next_lch
| (1 << 15);
621 #ifndef CONFIG_ARCH_OMAP1
622 if (cpu_class_is_omap2())
623 if (dma_chan
[lch
].next_linked_ch
!= -1)
624 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
627 p
->dma_write(l
, CLNK_CTRL
, lch
);
630 static inline void disable_lnk(int lch
)
634 l
= p
->dma_read(CLNK_CTRL
, lch
);
636 /* Disable interrupts */
637 omap_disable_channel_irq(lch
);
639 if (cpu_class_is_omap1()) {
640 /* Set the STOP_LNK bit */
644 if (cpu_class_is_omap2()) {
645 /* Clear the ENABLE_LNK bit */
649 p
->dma_write(l
, CLNK_CTRL
, lch
);
650 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
653 static inline void omap2_enable_irq_lch(int lch
)
658 if (!cpu_class_is_omap2())
661 spin_lock_irqsave(&dma_chan_lock
, flags
);
662 /* clear IRQ STATUS */
663 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
664 /* Enable interrupt */
665 val
= p
->dma_read(IRQENABLE_L0
, lch
);
667 p
->dma_write(val
, IRQENABLE_L0
, lch
);
668 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
671 static inline void omap2_disable_irq_lch(int lch
)
676 if (!cpu_class_is_omap2())
679 spin_lock_irqsave(&dma_chan_lock
, flags
);
680 /* Disable interrupt */
681 val
= p
->dma_read(IRQENABLE_L0
, lch
);
683 p
->dma_write(val
, IRQENABLE_L0
, lch
);
684 /* clear IRQ STATUS */
685 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
686 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
689 int omap_request_dma(int dev_id
, const char *dev_name
,
690 void (*callback
)(int lch
, u16 ch_status
, void *data
),
691 void *data
, int *dma_ch_out
)
693 int ch
, free_ch
= -1;
695 struct omap_dma_lch
*chan
;
697 spin_lock_irqsave(&dma_chan_lock
, flags
);
698 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
699 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
706 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
709 chan
= dma_chan
+ free_ch
;
710 chan
->dev_id
= dev_id
;
712 if (p
->clear_lch_regs
)
713 p
->clear_lch_regs(free_ch
);
715 if (cpu_class_is_omap2())
716 omap_clear_dma(free_ch
);
718 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
720 chan
->dev_name
= dev_name
;
721 chan
->callback
= callback
;
725 #ifndef CONFIG_ARCH_OMAP1
726 if (cpu_class_is_omap2()) {
728 chan
->next_linked_ch
= -1;
732 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
734 if (cpu_class_is_omap1())
735 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
736 else if (cpu_class_is_omap2())
737 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
738 OMAP2_DMA_TRANS_ERR_IRQ
;
740 if (cpu_is_omap16xx()) {
741 /* If the sync device is set, configure it dynamically. */
743 set_gdma_dev(free_ch
+ 1, dev_id
);
744 dev_id
= free_ch
+ 1;
747 * Disable the 1510 compatibility mode and set the sync device
750 p
->dma_write(dev_id
| (1 << 10), CCR
, free_ch
);
751 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
752 p
->dma_write(dev_id
, CCR
, free_ch
);
755 if (cpu_class_is_omap2()) {
756 omap_enable_channel_irq(free_ch
);
757 omap2_enable_irq_lch(free_ch
);
760 *dma_ch_out
= free_ch
;
764 EXPORT_SYMBOL(omap_request_dma
);
766 void omap_free_dma(int lch
)
770 if (dma_chan
[lch
].dev_id
== -1) {
771 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
776 /* Disable interrupt for logical channel */
777 if (cpu_class_is_omap2())
778 omap2_disable_irq_lch(lch
);
780 /* Disable all DMA interrupts for the channel. */
781 omap_disable_channel_irq(lch
);
783 /* Make sure the DMA transfer is stopped. */
784 p
->dma_write(0, CCR
, lch
);
786 /* Clear registers */
787 if (cpu_class_is_omap2())
790 spin_lock_irqsave(&dma_chan_lock
, flags
);
791 dma_chan
[lch
].dev_id
= -1;
792 dma_chan
[lch
].next_lch
= -1;
793 dma_chan
[lch
].callback
= NULL
;
794 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
796 EXPORT_SYMBOL(omap_free_dma
);
799 * @brief omap_dma_set_global_params : Set global priority settings for dma
802 * @param max_fifo_depth
803 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
804 * DMA_THREAD_RESERVE_ONET
805 * DMA_THREAD_RESERVE_TWOT
806 * DMA_THREAD_RESERVE_THREET
809 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
813 if (!cpu_class_is_omap2()) {
814 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
818 if (max_fifo_depth
== 0)
823 reg
= 0xff & max_fifo_depth
;
824 reg
|= (0x3 & tparams
) << 12;
825 reg
|= (arb_rate
& 0xff) << 16;
827 p
->dma_write(reg
, GCR
, 0);
829 EXPORT_SYMBOL(omap_dma_set_global_params
);
832 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
835 * @param read_prio - Read priority
836 * @param write_prio - Write priority
837 * Both of the above can be set with one of the following values :
838 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
841 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
842 unsigned char write_prio
)
846 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
847 printk(KERN_ERR
"Invalid channel id\n");
850 l
= p
->dma_read(CCR
, lch
);
851 l
&= ~((1 << 6) | (1 << 26));
852 if (cpu_class_is_omap2() && !cpu_is_omap242x())
853 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
855 l
|= ((read_prio
& 0x1) << 6);
857 p
->dma_write(l
, CCR
, lch
);
861 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
864 * Clears any DMA state so the DMA engine is ready to restart with new buffers
865 * through omap_start_dma(). Any buffers in flight are discarded.
867 void omap_clear_dma(int lch
)
871 local_irq_save(flags
);
873 local_irq_restore(flags
);
875 EXPORT_SYMBOL(omap_clear_dma
);
877 void omap_start_dma(int lch
)
882 * The CPC/CDAC register needs to be initialized to zero
883 * before starting dma transfer.
885 if (cpu_is_omap15xx())
886 p
->dma_write(0, CPC
, lch
);
888 p
->dma_write(0, CDAC
, lch
);
890 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
891 int next_lch
, cur_lch
;
892 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
894 dma_chan_link_map
[lch
] = 1;
895 /* Set the link register of the first channel */
898 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
899 cur_lch
= dma_chan
[lch
].next_lch
;
901 next_lch
= dma_chan
[cur_lch
].next_lch
;
903 /* The loop case: we've been here already */
904 if (dma_chan_link_map
[cur_lch
])
906 /* Mark the current channel */
907 dma_chan_link_map
[cur_lch
] = 1;
910 omap_enable_channel_irq(cur_lch
);
913 } while (next_lch
!= -1);
914 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS
))
915 p
->dma_write(lch
, CLNK_CTRL
, lch
);
917 omap_enable_channel_irq(lch
);
919 l
= p
->dma_read(CCR
, lch
);
921 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING
))
922 l
|= OMAP_DMA_CCR_BUFFERING_DISABLE
;
923 l
|= OMAP_DMA_CCR_EN
;
926 * As dma_write() uses IO accessors which are weakly ordered, there
927 * is no guarantee that data in coherent DMA memory will be visible
928 * to the DMA device. Add a memory barrier here to ensure that any
929 * such data is visible prior to enabling DMA.
932 p
->dma_write(l
, CCR
, lch
);
934 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
936 EXPORT_SYMBOL(omap_start_dma
);
938 void omap_stop_dma(int lch
)
942 /* Disable all interrupts on the channel */
943 omap_disable_channel_irq(lch
);
945 l
= p
->dma_read(CCR
, lch
);
946 if (IS_DMA_ERRATA(DMA_ERRATA_i541
) &&
947 (l
& OMAP_DMA_CCR_SEL_SRC_DST_SYNC
)) {
951 /* Configure No-Standby */
952 l
= p
->dma_read(OCP_SYSCONFIG
, lch
);
954 l
&= ~DMA_SYSCONFIG_MIDLEMODE_MASK
;
955 l
|= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE
);
956 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
958 l
= p
->dma_read(CCR
, lch
);
959 l
&= ~OMAP_DMA_CCR_EN
;
960 p
->dma_write(l
, CCR
, lch
);
962 /* Wait for sDMA FIFO drain */
963 l
= p
->dma_read(CCR
, lch
);
964 while (i
< 100 && (l
& (OMAP_DMA_CCR_RD_ACTIVE
|
965 OMAP_DMA_CCR_WR_ACTIVE
))) {
968 l
= p
->dma_read(CCR
, lch
);
971 pr_err("DMA drain did not complete on lch %d\n", lch
);
972 /* Restore OCP_SYSCONFIG */
973 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, lch
);
975 l
&= ~OMAP_DMA_CCR_EN
;
976 p
->dma_write(l
, CCR
, lch
);
980 * Ensure that data transferred by DMA is visible to any access
981 * after DMA has been disabled. This is important for coherent
986 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
987 int next_lch
, cur_lch
= lch
;
988 char dma_chan_link_map
[MAX_LOGICAL_DMA_CH_COUNT
];
990 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
992 /* The loop case: we've been here already */
993 if (dma_chan_link_map
[cur_lch
])
995 /* Mark the current channel */
996 dma_chan_link_map
[cur_lch
] = 1;
998 disable_lnk(cur_lch
);
1000 next_lch
= dma_chan
[cur_lch
].next_lch
;
1002 } while (next_lch
!= -1);
1005 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
1007 EXPORT_SYMBOL(omap_stop_dma
);
1010 * Allows changing the DMA callback function or data. This may be needed if
1011 * the driver shares a single DMA channel for multiple dma triggers.
1013 int omap_set_dma_callback(int lch
,
1014 void (*callback
)(int lch
, u16 ch_status
, void *data
),
1017 unsigned long flags
;
1022 spin_lock_irqsave(&dma_chan_lock
, flags
);
1023 if (dma_chan
[lch
].dev_id
== -1) {
1024 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1025 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1028 dma_chan
[lch
].callback
= callback
;
1029 dma_chan
[lch
].data
= data
;
1030 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1034 EXPORT_SYMBOL(omap_set_dma_callback
);
1037 * Returns current physical source address for the given DMA channel.
1038 * If the channel is running the caller must disable interrupts prior calling
1039 * this function and process the returned value before re-enabling interrupt to
1040 * prevent races with the interrupt handler. Note that in continuous mode there
1041 * is a chance for CSSA_L register overflow between the two reads resulting
1042 * in incorrect return value.
1044 dma_addr_t
omap_get_dma_src_pos(int lch
)
1046 dma_addr_t offset
= 0;
1048 if (cpu_is_omap15xx())
1049 offset
= p
->dma_read(CPC
, lch
);
1051 offset
= p
->dma_read(CSAC
, lch
);
1053 if (IS_DMA_ERRATA(DMA_ERRATA_3_3
) && offset
== 0)
1054 offset
= p
->dma_read(CSAC
, lch
);
1056 if (!cpu_is_omap15xx()) {
1058 * CDAC == 0 indicates that the DMA transfer on the channel has
1059 * not been started (no data has been transferred so far).
1060 * Return the programmed source start address in this case.
1062 if (likely(p
->dma_read(CDAC
, lch
)))
1063 offset
= p
->dma_read(CSAC
, lch
);
1065 offset
= p
->dma_read(CSSA
, lch
);
1068 if (cpu_class_is_omap1())
1069 offset
|= (p
->dma_read(CSSA
, lch
) & 0xFFFF0000);
1073 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1076 * Returns current physical destination address for the given DMA channel.
1077 * If the channel is running the caller must disable interrupts prior calling
1078 * this function and process the returned value before re-enabling interrupt to
1079 * prevent races with the interrupt handler. Note that in continuous mode there
1080 * is a chance for CDSA_L register overflow between the two reads resulting
1081 * in incorrect return value.
1083 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1085 dma_addr_t offset
= 0;
1087 if (cpu_is_omap15xx())
1088 offset
= p
->dma_read(CPC
, lch
);
1090 offset
= p
->dma_read(CDAC
, lch
);
1093 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1094 * read before the DMA controller finished disabling the channel.
1096 if (!cpu_is_omap15xx() && offset
== 0) {
1097 offset
= p
->dma_read(CDAC
, lch
);
1099 * CDAC == 0 indicates that the DMA transfer on the channel has
1100 * not been started (no data has been transferred so far).
1101 * Return the programmed destination start address in this case.
1103 if (unlikely(!offset
))
1104 offset
= p
->dma_read(CDSA
, lch
);
1107 if (cpu_class_is_omap1())
1108 offset
|= (p
->dma_read(CDSA
, lch
) & 0xFFFF0000);
1112 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1114 int omap_get_dma_active_status(int lch
)
1116 return (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
) != 0;
1118 EXPORT_SYMBOL(omap_get_dma_active_status
);
1120 int omap_dma_running(void)
1124 if (cpu_class_is_omap1())
1125 if (omap_lcd_dma_running())
1128 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1129 if (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
)
1136 * lch_queue DMA will start right after lch_head one is finished.
1137 * For this DMA link to start, you still need to start (see omap_start_dma)
1138 * the first one. That will fire up the entire queue.
1140 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1142 if (omap_dma_in_1510_mode()) {
1143 if (lch_head
== lch_queue
) {
1144 p
->dma_write(p
->dma_read(CCR
, lch_head
) | (3 << 8),
1148 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1153 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1154 (dma_chan
[lch_queue
].dev_id
== -1)) {
1155 pr_err("omap_dma: trying to link non requested channels\n");
1159 dma_chan
[lch_head
].next_lch
= lch_queue
;
1161 EXPORT_SYMBOL(omap_dma_link_lch
);
1164 * Once the DMA queue is stopped, we can destroy it.
1166 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1168 if (omap_dma_in_1510_mode()) {
1169 if (lch_head
== lch_queue
) {
1170 p
->dma_write(p
->dma_read(CCR
, lch_head
) & ~(3 << 8),
1174 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1179 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1180 dma_chan
[lch_head
].next_lch
== -1) {
1181 pr_err("omap_dma: trying to unlink non linked channels\n");
1185 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1186 (dma_chan
[lch_queue
].flags
& OMAP_DMA_ACTIVE
)) {
1187 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1191 dma_chan
[lch_head
].next_lch
= -1;
1193 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1195 #ifndef CONFIG_ARCH_OMAP1
1196 /* Create chain of DMA channesls */
1197 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1201 /* Check if this is the first link in chain */
1202 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1203 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1204 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1205 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1206 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1209 /* a link exists, link the new channel in circular chain */
1211 dma_chan
[lch_queue
].next_linked_ch
=
1212 dma_chan
[lch_head
].next_linked_ch
;
1213 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1214 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1215 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1219 l
= p
->dma_read(CLNK_CTRL
, lch_head
);
1222 p
->dma_write(l
, CLNK_CTRL
, lch_head
);
1224 l
= p
->dma_read(CLNK_CTRL
, lch_queue
);
1226 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1227 p
->dma_write(l
, CLNK_CTRL
, lch_queue
);
1231 * @brief omap_request_dma_chain : Request a chain of DMA channels
1233 * @param dev_id - Device id using the dma channel
1234 * @param dev_name - Device name
1235 * @param callback - Call back function
1237 * @no_of_chans - Number of channels requested
1238 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1239 * OMAP_DMA_DYNAMIC_CHAIN
1240 * @params - Channel parameters
1242 * @return - Success : 0
1243 * Failure: -EINVAL/-ENOMEM
1245 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1246 void (*callback
) (int lch
, u16 ch_status
,
1248 int *chain_id
, int no_of_chans
, int chain_mode
,
1249 struct omap_dma_channel_params params
)
1254 /* Is the chain mode valid ? */
1255 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1256 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1257 printk(KERN_ERR
"Invalid chain mode requested\n");
1261 if (unlikely((no_of_chans
< 1
1262 || no_of_chans
> dma_lch_count
))) {
1263 printk(KERN_ERR
"Invalid Number of channels requested\n");
1268 * Allocate a queue to maintain the status of the channels
1271 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1272 if (channels
== NULL
) {
1273 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1277 /* request and reserve DMA channels for the chain */
1278 for (i
= 0; i
< no_of_chans
; i
++) {
1279 err
= omap_request_dma(dev_id
, dev_name
,
1280 callback
, NULL
, &channels
[i
]);
1283 for (j
= 0; j
< i
; j
++)
1284 omap_free_dma(channels
[j
]);
1286 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1289 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1290 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1293 * Allowing client drivers to set common parameters now,
1294 * so that later only relevant (src_start, dest_start
1295 * and element count) can be set
1297 omap_set_dma_params(channels
[i
], ¶ms
);
1300 *chain_id
= channels
[0];
1301 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1302 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1303 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1304 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1306 for (i
= 0; i
< no_of_chans
; i
++)
1307 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1309 /* Reset the Queue pointers */
1310 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1312 /* Set up the chain */
1313 if (no_of_chans
== 1)
1314 create_dma_lch_chain(channels
[0], channels
[0]);
1316 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1317 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1322 EXPORT_SYMBOL(omap_request_dma_chain
);
1325 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1326 * params after setting it. Dont do this while dma is running!!
1328 * @param chain_id - Chained logical channel id.
1331 * @return - Success : 0
1334 int omap_modify_dma_chain_params(int chain_id
,
1335 struct omap_dma_channel_params params
)
1340 /* Check for input params */
1341 if (unlikely((chain_id
< 0
1342 || chain_id
>= dma_lch_count
))) {
1343 printk(KERN_ERR
"Invalid chain id\n");
1347 /* Check if the chain exists */
1348 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1349 printk(KERN_ERR
"Chain doesn't exists\n");
1352 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1354 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1356 * Allowing client drivers to set common parameters now,
1357 * so that later only relevant (src_start, dest_start
1358 * and element count) can be set
1360 omap_set_dma_params(channels
[i
], ¶ms
);
1365 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1368 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1372 * @return - Success : 0
1375 int omap_free_dma_chain(int chain_id
)
1380 /* Check for input params */
1381 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1382 printk(KERN_ERR
"Invalid chain id\n");
1386 /* Check if the chain exists */
1387 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1388 printk(KERN_ERR
"Chain doesn't exists\n");
1392 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1393 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1394 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1395 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1396 dma_chan
[channels
[i
]].chain_id
= -1;
1397 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1398 omap_free_dma(channels
[i
]);
1403 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1404 dma_linked_lch
[chain_id
].chain_mode
= -1;
1405 dma_linked_lch
[chain_id
].chain_state
= -1;
1409 EXPORT_SYMBOL(omap_free_dma_chain
);
1412 * @brief omap_dma_chain_status - Check if the chain is in
1413 * active / inactive state.
1416 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1419 int omap_dma_chain_status(int chain_id
)
1421 /* Check for input params */
1422 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1423 printk(KERN_ERR
"Invalid chain id\n");
1427 /* Check if the chain exists */
1428 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1429 printk(KERN_ERR
"Chain doesn't exists\n");
1432 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1433 dma_linked_lch
[chain_id
].q_count
);
1435 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1436 return OMAP_DMA_CHAIN_INACTIVE
;
1438 return OMAP_DMA_CHAIN_ACTIVE
;
1440 EXPORT_SYMBOL(omap_dma_chain_status
);
1443 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1444 * set the params and start the transfer.
1447 * @param src_start - buffer start address
1448 * @param dest_start - Dest address
1450 * @param frame_count
1451 * @param callbk_data - channel callback parameter data.
1453 * @return - Success : 0
1454 * Failure: -EINVAL/-EBUSY
1456 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1457 int elem_count
, int frame_count
, void *callbk_data
)
1464 * if buffer size is less than 1 then there is
1465 * no use of starting the chain
1467 if (elem_count
< 1) {
1468 printk(KERN_ERR
"Invalid buffer size\n");
1472 /* Check for input params */
1473 if (unlikely((chain_id
< 0
1474 || chain_id
>= dma_lch_count
))) {
1475 printk(KERN_ERR
"Invalid chain id\n");
1479 /* Check if the chain exists */
1480 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1481 printk(KERN_ERR
"Chain doesn't exist\n");
1485 /* Check if all the channels in chain are in use */
1486 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1489 /* Frame count may be negative in case of indexed transfers */
1490 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1492 /* Get a free channel */
1493 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1495 /* Store the callback data */
1496 dma_chan
[lch
].data
= callbk_data
;
1498 /* Increment the q_tail */
1499 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1501 /* Set the params to the free channel */
1503 p
->dma_write(src_start
, CSSA
, lch
);
1504 if (dest_start
!= 0)
1505 p
->dma_write(dest_start
, CDSA
, lch
);
1507 /* Write the buffer size */
1508 p
->dma_write(elem_count
, CEN
, lch
);
1509 p
->dma_write(frame_count
, CFN
, lch
);
1512 * If the chain is dynamically linked,
1513 * then we may have to start the chain if its not active
1515 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1518 * In Dynamic chain, if the chain is not started,
1521 if (dma_linked_lch
[chain_id
].chain_state
==
1522 DMA_CHAIN_NOTSTARTED
) {
1523 /* Enable the link in previous channel */
1524 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1526 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1527 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1531 * Chain is already started, make sure its active,
1532 * if not then start the chain
1537 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1539 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1540 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1542 if (0 == ((1 << 7) & p
->dma_read(
1543 CCR
, dma_chan
[lch
].prev_linked_ch
))) {
1544 disable_lnk(dma_chan
[lch
].
1546 pr_debug("\n prev ch is stopped\n");
1551 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1553 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1554 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1557 omap_enable_channel_irq(lch
);
1559 l
= p
->dma_read(CCR
, lch
);
1561 if ((0 == (l
& (1 << 24))))
1565 if (start_dma
== 1) {
1566 if (0 == (l
& (1 << 7))) {
1568 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1569 pr_debug("starting %d\n", lch
);
1570 p
->dma_write(l
, CCR
, lch
);
1574 if (0 == (l
& (1 << 7)))
1575 p
->dma_write(l
, CCR
, lch
);
1577 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1583 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1586 * @brief omap_start_dma_chain_transfers - Start the chain
1590 * @return - Success : 0
1591 * Failure : -EINVAL/-EBUSY
1593 int omap_start_dma_chain_transfers(int chain_id
)
1598 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1599 printk(KERN_ERR
"Invalid chain id\n");
1603 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1605 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1606 printk(KERN_ERR
"Chain is already started\n");
1610 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1611 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1613 enable_lnk(channels
[i
]);
1614 omap_enable_channel_irq(channels
[i
]);
1617 omap_enable_channel_irq(channels
[0]);
1620 l
= p
->dma_read(CCR
, channels
[0]);
1622 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1623 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1625 if ((0 == (l
& (1 << 24))))
1629 p
->dma_write(l
, CCR
, channels
[0]);
1631 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1635 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1638 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1642 * @return - Success : 0
1645 int omap_stop_dma_chain_transfers(int chain_id
)
1651 /* Check for input params */
1652 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1653 printk(KERN_ERR
"Invalid chain id\n");
1657 /* Check if the chain exists */
1658 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1659 printk(KERN_ERR
"Chain doesn't exists\n");
1662 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1664 if (IS_DMA_ERRATA(DMA_ERRATA_i88
)) {
1665 sys_cf
= p
->dma_read(OCP_SYSCONFIG
, 0);
1667 /* Middle mode reg set no Standby */
1668 l
&= ~((1 << 12)|(1 << 13));
1669 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
1672 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1674 /* Stop the Channel transmission */
1675 l
= p
->dma_read(CCR
, channels
[i
]);
1677 p
->dma_write(l
, CCR
, channels
[i
]);
1679 /* Disable the link in all the channels */
1680 disable_lnk(channels
[i
]);
1681 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1684 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1686 /* Reset the Queue pointers */
1687 OMAP_DMA_CHAIN_QINIT(chain_id
);
1689 if (IS_DMA_ERRATA(DMA_ERRATA_i88
))
1690 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, 0);
1694 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1696 /* Get the index of the ongoing DMA in chain */
1698 * @brief omap_get_dma_chain_index - Get the element and frame index
1699 * of the ongoing DMA in chain
1702 * @param ei - Element index
1703 * @param fi - Frame index
1705 * @return - Success : 0
1708 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1713 /* Check for input params */
1714 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1715 printk(KERN_ERR
"Invalid chain id\n");
1719 /* Check if the chain exists */
1720 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1721 printk(KERN_ERR
"Chain doesn't exists\n");
1727 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1729 /* Get the current channel */
1730 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1732 *ei
= p
->dma_read(CCEN
, lch
);
1733 *fi
= p
->dma_read(CCFN
, lch
);
1737 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1740 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1741 * ongoing DMA in chain
1745 * @return - Success : Destination position
1748 int omap_get_dma_chain_dst_pos(int chain_id
)
1753 /* Check for input params */
1754 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1755 printk(KERN_ERR
"Invalid chain id\n");
1759 /* Check if the chain exists */
1760 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1761 printk(KERN_ERR
"Chain doesn't exists\n");
1765 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1767 /* Get the current channel */
1768 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1770 return p
->dma_read(CDAC
, lch
);
1772 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1775 * @brief omap_get_dma_chain_src_pos - Get the source position
1776 * of the ongoing DMA in chain
1779 * @return - Success : Destination position
1782 int omap_get_dma_chain_src_pos(int chain_id
)
1787 /* Check for input params */
1788 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1789 printk(KERN_ERR
"Invalid chain id\n");
1793 /* Check if the chain exists */
1794 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1795 printk(KERN_ERR
"Chain doesn't exists\n");
1799 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1801 /* Get the current channel */
1802 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1804 return p
->dma_read(CSAC
, lch
);
1806 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1807 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1809 /*----------------------------------------------------------------------------*/
1811 #ifdef CONFIG_ARCH_OMAP1
1813 static int omap1_dma_handle_ch(int ch
)
1817 if (enable_1510_mode
&& ch
>= 6) {
1818 csr
= dma_chan
[ch
].saved_csr
;
1819 dma_chan
[ch
].saved_csr
= 0;
1821 csr
= p
->dma_read(CSR
, ch
);
1822 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1823 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1826 if ((csr
& 0x3f) == 0)
1828 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1829 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1833 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1834 pr_warn("DMA timeout with device %d\n", dma_chan
[ch
].dev_id
);
1835 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1836 pr_warn("DMA synchronization event drop occurred with device %d\n",
1837 dma_chan
[ch
].dev_id
);
1838 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1839 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1840 if (likely(dma_chan
[ch
].callback
!= NULL
))
1841 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1846 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1848 int ch
= ((int) dev_id
) - 1;
1852 int handled_now
= 0;
1854 handled_now
+= omap1_dma_handle_ch(ch
);
1855 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1856 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1859 handled
+= handled_now
;
1862 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1866 #define omap1_dma_irq_handler NULL
1869 #ifdef CONFIG_ARCH_OMAP2PLUS
1871 static int omap2_dma_handle_ch(int ch
)
1873 u32 status
= p
->dma_read(CSR
, ch
);
1876 if (printk_ratelimit())
1877 pr_warn("Spurious DMA IRQ for lch %d\n", ch
);
1878 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1881 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1882 if (printk_ratelimit())
1883 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1887 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1888 pr_info("DMA synchronization event drop occurred with device %d\n",
1889 dma_chan
[ch
].dev_id
);
1890 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
)) {
1891 printk(KERN_INFO
"DMA transaction error with device %d\n",
1892 dma_chan
[ch
].dev_id
);
1893 if (IS_DMA_ERRATA(DMA_ERRATA_i378
)) {
1896 ccr
= p
->dma_read(CCR
, ch
);
1897 ccr
&= ~OMAP_DMA_CCR_EN
;
1898 p
->dma_write(ccr
, CCR
, ch
);
1899 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1902 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1903 printk(KERN_INFO
"DMA secure error with device %d\n",
1904 dma_chan
[ch
].dev_id
);
1905 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1906 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1907 dma_chan
[ch
].dev_id
);
1909 p
->dma_write(status
, CSR
, ch
);
1910 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1911 /* read back the register to flush the write */
1912 p
->dma_read(IRQSTATUS_L0
, ch
);
1914 /* If the ch is not chained then chain_id will be -1 */
1915 if (dma_chan
[ch
].chain_id
!= -1) {
1916 int chain_id
= dma_chan
[ch
].chain_id
;
1917 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1918 if (p
->dma_read(CLNK_CTRL
, ch
) & (1 << 15))
1919 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1921 if (dma_linked_lch
[chain_id
].chain_mode
==
1922 OMAP_DMA_DYNAMIC_CHAIN
)
1925 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1926 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1928 status
= p
->dma_read(CSR
, ch
);
1929 p
->dma_write(status
, CSR
, ch
);
1932 if (likely(dma_chan
[ch
].callback
!= NULL
))
1933 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1938 /* STATUS register count is from 1-32 while our is 0-31 */
1939 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1941 u32 val
, enable_reg
;
1944 val
= p
->dma_read(IRQSTATUS_L0
, 0);
1946 if (printk_ratelimit())
1947 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1950 enable_reg
= p
->dma_read(IRQENABLE_L0
, 0);
1951 val
&= enable_reg
; /* Dispatch only relevant interrupts */
1952 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1954 omap2_dma_handle_ch(i
);
1961 static struct irqaction omap24xx_dma_irq
= {
1963 .handler
= omap2_dma_irq_handler
,
1964 .flags
= IRQF_DISABLED
1968 static struct irqaction omap24xx_dma_irq
;
1971 /*----------------------------------------------------------------------------*/
1973 void omap_dma_global_context_save(void)
1975 omap_dma_global_context
.dma_irqenable_l0
=
1976 p
->dma_read(IRQENABLE_L0
, 0);
1977 omap_dma_global_context
.dma_ocp_sysconfig
=
1978 p
->dma_read(OCP_SYSCONFIG
, 0);
1979 omap_dma_global_context
.dma_gcr
= p
->dma_read(GCR
, 0);
1982 void omap_dma_global_context_restore(void)
1986 p
->dma_write(omap_dma_global_context
.dma_gcr
, GCR
, 0);
1987 p
->dma_write(omap_dma_global_context
.dma_ocp_sysconfig
,
1989 p
->dma_write(omap_dma_global_context
.dma_irqenable_l0
,
1992 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG
))
1993 p
->dma_write(0x3 , IRQSTATUS_L0
, 0);
1995 for (ch
= 0; ch
< dma_chan_count
; ch
++)
1996 if (dma_chan
[ch
].dev_id
!= -1)
2000 static int __devinit
omap_system_dma_probe(struct platform_device
*pdev
)
2007 p
= pdev
->dev
.platform_data
;
2010 "%s: System DMA initialized without platform data\n",
2018 if ((d
->dev_caps
& RESERVE_CHANNEL
) && omap_dma_reserve_channels
2019 && (omap_dma_reserve_channels
<= dma_lch_count
))
2020 d
->lch_count
= omap_dma_reserve_channels
;
2022 dma_lch_count
= d
->lch_count
;
2023 dma_chan_count
= dma_lch_count
;
2025 enable_1510_mode
= d
->dev_caps
& ENABLE_1510_MODE
;
2027 if (cpu_class_is_omap2()) {
2028 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2029 dma_lch_count
, GFP_KERNEL
);
2030 if (!dma_linked_lch
) {
2032 goto exit_dma_lch_fail
;
2036 spin_lock_init(&dma_chan_lock
);
2037 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2039 if (cpu_class_is_omap2())
2040 omap2_disable_irq_lch(ch
);
2042 dma_chan
[ch
].dev_id
= -1;
2043 dma_chan
[ch
].next_lch
= -1;
2045 if (ch
>= 6 && enable_1510_mode
)
2048 if (cpu_class_is_omap1()) {
2050 * request_irq() doesn't like dev_id (ie. ch) being
2051 * zero, so we have to kludge around this.
2053 sprintf(&irq_name
[0], "%d", ch
);
2054 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2058 goto exit_dma_irq_fail
;
2061 /* INT_DMA_LCD is handled in lcd_dma.c */
2062 if (dma_irq
== INT_DMA_LCD
)
2065 ret
= request_irq(dma_irq
,
2066 omap1_dma_irq_handler
, 0, "DMA",
2069 goto exit_dma_irq_fail
;
2073 if (cpu_class_is_omap2() && !cpu_is_omap242x())
2074 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2075 DMA_DEFAULT_FIFO_DEPTH
, 0);
2077 if (cpu_class_is_omap2()) {
2078 strcpy(irq_name
, "0");
2079 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2081 dev_err(&pdev
->dev
, "failed: request IRQ %d", dma_irq
);
2082 goto exit_dma_lch_fail
;
2084 ret
= setup_irq(dma_irq
, &omap24xx_dma_irq
);
2086 dev_err(&pdev
->dev
, "set_up failed for IRQ %d for DMA (error %d)\n",
2088 goto exit_dma_lch_fail
;
2092 /* reserve dma channels 0 and 1 in high security devices */
2093 if (cpu_is_omap34xx() &&
2094 (omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
2095 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2096 dma_chan
[0].dev_id
= 0;
2097 dma_chan
[1].dev_id
= 1;
2103 dev_err(&pdev
->dev
, "unable to request IRQ %d for DMA (error %d)\n",
2105 for (irq_rel
= 0; irq_rel
< ch
; irq_rel
++) {
2106 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2107 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2117 static int __devexit
omap_system_dma_remove(struct platform_device
*pdev
)
2121 if (cpu_class_is_omap2()) {
2123 strcpy(irq_name
, "0");
2124 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2125 remove_irq(dma_irq
, &omap24xx_dma_irq
);
2128 for ( ; irq_rel
< dma_chan_count
; irq_rel
++) {
2129 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2130 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2139 static struct platform_driver omap_system_dma_driver
= {
2140 .probe
= omap_system_dma_probe
,
2141 .remove
= __devexit_p(omap_system_dma_remove
),
2143 .name
= "omap_dma_system"
2147 static int __init
omap_system_dma_init(void)
2149 return platform_driver_register(&omap_system_dma_driver
);
2151 arch_initcall(omap_system_dma_init
);
2153 static void __exit
omap_system_dma_exit(void)
2155 platform_driver_unregister(&omap_system_dma_driver
);
2158 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2159 MODULE_LICENSE("GPL");
2160 MODULE_ALIAS("platform:" DRIVER_NAME
);
2161 MODULE_AUTHOR("Texas Instruments Inc");
2164 * Reserve the omap SDMA channels using cmdline bootarg
2165 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2167 static int __init
omap_dma_cmdline_reserve_ch(char *str
)
2169 if (get_option(&str
, &omap_dma_reserve_channels
) != 1)
2170 omap_dma_reserve_channels
= 0;
2174 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch
);