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ARM: OMAP1: Move plat/tc.h to mach/tc.h for omap1
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <plat/cpu.h>
40 #include <plat-omap/dma-omap.h>
41
42 /*
43 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
44 * channels that an instance of the SDMA IP block can support. Used
45 * to size arrays. (The actual maximum on a particular SoC may be less
46 * than this -- for example, OMAP1 SDMA instances only support 17 logical
47 * DMA channels.)
48 */
49 #define MAX_LOGICAL_DMA_CH_COUNT 32
50
51 #undef DEBUG
52
53 #ifndef CONFIG_ARCH_OMAP1
54 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
55 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
56 };
57
58 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
59 #endif
60
61 #define OMAP_DMA_ACTIVE 0x01
62 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
63
64 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
65
66 static struct omap_system_dma_plat_info *p;
67 static struct omap_dma_dev_attr *d;
68
69 static int enable_1510_mode;
70 static u32 errata;
71
72 static struct omap_dma_global_context_registers {
73 u32 dma_irqenable_l0;
74 u32 dma_ocp_sysconfig;
75 u32 dma_gcr;
76 } omap_dma_global_context;
77
78 struct dma_link_info {
79 int *linked_dmach_q;
80 int no_of_lchs_linked;
81
82 int q_count;
83 int q_tail;
84 int q_head;
85
86 int chain_state;
87 int chain_mode;
88
89 };
90
91 static struct dma_link_info *dma_linked_lch;
92
93 #ifndef CONFIG_ARCH_OMAP1
94
95 /* Chain handling macros */
96 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 do { \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
101 } while (0)
102 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 do { \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
109 } while (0)
110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112 #define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
118 } while (0)
119
120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
124 } while (0)
125 #endif
126
127 static int dma_lch_count;
128 static int dma_chan_count;
129 static int omap_dma_reserve_channels;
130
131 static spinlock_t dma_chan_lock;
132 static struct omap_dma_lch *dma_chan;
133
134 static inline void disable_lnk(int lch);
135 static void omap_disable_channel_irq(int lch);
136 static inline void omap_enable_channel_irq(int lch);
137
138 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
139 __func__);
140
141 #ifdef CONFIG_ARCH_OMAP15XX
142 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
143 static int omap_dma_in_1510_mode(void)
144 {
145 return enable_1510_mode;
146 }
147 #else
148 #define omap_dma_in_1510_mode() 0
149 #endif
150
151 #ifdef CONFIG_ARCH_OMAP1
152 static inline int get_gdma_dev(int req)
153 {
154 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
155 int shift = ((req - 1) % 5) * 6;
156
157 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
158 }
159
160 static inline void set_gdma_dev(int req, int dev)
161 {
162 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
163 int shift = ((req - 1) % 5) * 6;
164 u32 l;
165
166 l = omap_readl(reg);
167 l &= ~(0x3f << shift);
168 l |= (dev - 1) << shift;
169 omap_writel(l, reg);
170 }
171 #else
172 #define set_gdma_dev(req, dev) do {} while (0)
173 #define omap_readl(reg) 0
174 #define omap_writel(val, reg) do {} while (0)
175 #endif
176
177 #ifdef CONFIG_ARCH_OMAP1
178 void omap_set_dma_priority(int lch, int dst_port, int priority)
179 {
180 unsigned long reg;
181 u32 l;
182
183 if (cpu_class_is_omap1()) {
184 switch (dst_port) {
185 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
186 reg = OMAP_TC_OCPT1_PRIOR;
187 break;
188 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
189 reg = OMAP_TC_OCPT2_PRIOR;
190 break;
191 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
192 reg = OMAP_TC_EMIFF_PRIOR;
193 break;
194 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
195 reg = OMAP_TC_EMIFS_PRIOR;
196 break;
197 default:
198 BUG();
199 return;
200 }
201 l = omap_readl(reg);
202 l &= ~(0xf << 8);
203 l |= (priority & 0xf) << 8;
204 omap_writel(l, reg);
205 }
206 }
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP2PLUS
210 void omap_set_dma_priority(int lch, int dst_port, int priority)
211 {
212 u32 ccr;
213
214 ccr = p->dma_read(CCR, lch);
215 if (priority)
216 ccr |= (1 << 6);
217 else
218 ccr &= ~(1 << 6);
219 p->dma_write(ccr, CCR, lch);
220 }
221 #endif
222 EXPORT_SYMBOL(omap_set_dma_priority);
223
224 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
225 int frame_count, int sync_mode,
226 int dma_trigger, int src_or_dst_synch)
227 {
228 u32 l;
229
230 l = p->dma_read(CSDP, lch);
231 l &= ~0x03;
232 l |= data_type;
233 p->dma_write(l, CSDP, lch);
234
235 if (cpu_class_is_omap1()) {
236 u16 ccr;
237
238 ccr = p->dma_read(CCR, lch);
239 ccr &= ~(1 << 5);
240 if (sync_mode == OMAP_DMA_SYNC_FRAME)
241 ccr |= 1 << 5;
242 p->dma_write(ccr, CCR, lch);
243
244 ccr = p->dma_read(CCR2, lch);
245 ccr &= ~(1 << 2);
246 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
247 ccr |= 1 << 2;
248 p->dma_write(ccr, CCR2, lch);
249 }
250
251 if (cpu_class_is_omap2() && dma_trigger) {
252 u32 val;
253
254 val = p->dma_read(CCR, lch);
255
256 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
257 val &= ~((1 << 23) | (3 << 19) | 0x1f);
258 val |= (dma_trigger & ~0x1f) << 14;
259 val |= dma_trigger & 0x1f;
260
261 if (sync_mode & OMAP_DMA_SYNC_FRAME)
262 val |= 1 << 5;
263 else
264 val &= ~(1 << 5);
265
266 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
267 val |= 1 << 18;
268 else
269 val &= ~(1 << 18);
270
271 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
272 val &= ~(1 << 24); /* dest synch */
273 val |= (1 << 23); /* Prefetch */
274 } else if (src_or_dst_synch) {
275 val |= 1 << 24; /* source synch */
276 } else {
277 val &= ~(1 << 24); /* dest synch */
278 }
279 p->dma_write(val, CCR, lch);
280 }
281
282 p->dma_write(elem_count, CEN, lch);
283 p->dma_write(frame_count, CFN, lch);
284 }
285 EXPORT_SYMBOL(omap_set_dma_transfer_params);
286
287 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
288 {
289 BUG_ON(omap_dma_in_1510_mode());
290
291 if (cpu_class_is_omap1()) {
292 u16 w;
293
294 w = p->dma_read(CCR2, lch);
295 w &= ~0x03;
296
297 switch (mode) {
298 case OMAP_DMA_CONSTANT_FILL:
299 w |= 0x01;
300 break;
301 case OMAP_DMA_TRANSPARENT_COPY:
302 w |= 0x02;
303 break;
304 case OMAP_DMA_COLOR_DIS:
305 break;
306 default:
307 BUG();
308 }
309 p->dma_write(w, CCR2, lch);
310
311 w = p->dma_read(LCH_CTRL, lch);
312 w &= ~0x0f;
313 /* Default is channel type 2D */
314 if (mode) {
315 p->dma_write(color, COLOR, lch);
316 w |= 1; /* Channel type G */
317 }
318 p->dma_write(w, LCH_CTRL, lch);
319 }
320
321 if (cpu_class_is_omap2()) {
322 u32 val;
323
324 val = p->dma_read(CCR, lch);
325 val &= ~((1 << 17) | (1 << 16));
326
327 switch (mode) {
328 case OMAP_DMA_CONSTANT_FILL:
329 val |= 1 << 16;
330 break;
331 case OMAP_DMA_TRANSPARENT_COPY:
332 val |= 1 << 17;
333 break;
334 case OMAP_DMA_COLOR_DIS:
335 break;
336 default:
337 BUG();
338 }
339 p->dma_write(val, CCR, lch);
340
341 color &= 0xffffff;
342 p->dma_write(color, COLOR, lch);
343 }
344 }
345 EXPORT_SYMBOL(omap_set_dma_color_mode);
346
347 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
348 {
349 if (cpu_class_is_omap2()) {
350 u32 csdp;
351
352 csdp = p->dma_read(CSDP, lch);
353 csdp &= ~(0x3 << 16);
354 csdp |= (mode << 16);
355 p->dma_write(csdp, CSDP, lch);
356 }
357 }
358 EXPORT_SYMBOL(omap_set_dma_write_mode);
359
360 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
361 {
362 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
363 u32 l;
364
365 l = p->dma_read(LCH_CTRL, lch);
366 l &= ~0x7;
367 l |= mode;
368 p->dma_write(l, LCH_CTRL, lch);
369 }
370 }
371 EXPORT_SYMBOL(omap_set_dma_channel_mode);
372
373 /* Note that src_port is only for omap1 */
374 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
375 unsigned long src_start,
376 int src_ei, int src_fi)
377 {
378 u32 l;
379
380 if (cpu_class_is_omap1()) {
381 u16 w;
382
383 w = p->dma_read(CSDP, lch);
384 w &= ~(0x1f << 2);
385 w |= src_port << 2;
386 p->dma_write(w, CSDP, lch);
387 }
388
389 l = p->dma_read(CCR, lch);
390 l &= ~(0x03 << 12);
391 l |= src_amode << 12;
392 p->dma_write(l, CCR, lch);
393
394 p->dma_write(src_start, CSSA, lch);
395
396 p->dma_write(src_ei, CSEI, lch);
397 p->dma_write(src_fi, CSFI, lch);
398 }
399 EXPORT_SYMBOL(omap_set_dma_src_params);
400
401 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
402 {
403 omap_set_dma_transfer_params(lch, params->data_type,
404 params->elem_count, params->frame_count,
405 params->sync_mode, params->trigger,
406 params->src_or_dst_synch);
407 omap_set_dma_src_params(lch, params->src_port,
408 params->src_amode, params->src_start,
409 params->src_ei, params->src_fi);
410
411 omap_set_dma_dest_params(lch, params->dst_port,
412 params->dst_amode, params->dst_start,
413 params->dst_ei, params->dst_fi);
414 if (params->read_prio || params->write_prio)
415 omap_dma_set_prio_lch(lch, params->read_prio,
416 params->write_prio);
417 }
418 EXPORT_SYMBOL(omap_set_dma_params);
419
420 void omap_set_dma_src_index(int lch, int eidx, int fidx)
421 {
422 if (cpu_class_is_omap2())
423 return;
424
425 p->dma_write(eidx, CSEI, lch);
426 p->dma_write(fidx, CSFI, lch);
427 }
428 EXPORT_SYMBOL(omap_set_dma_src_index);
429
430 void omap_set_dma_src_data_pack(int lch, int enable)
431 {
432 u32 l;
433
434 l = p->dma_read(CSDP, lch);
435 l &= ~(1 << 6);
436 if (enable)
437 l |= (1 << 6);
438 p->dma_write(l, CSDP, lch);
439 }
440 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
441
442 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
443 {
444 unsigned int burst = 0;
445 u32 l;
446
447 l = p->dma_read(CSDP, lch);
448 l &= ~(0x03 << 7);
449
450 switch (burst_mode) {
451 case OMAP_DMA_DATA_BURST_DIS:
452 break;
453 case OMAP_DMA_DATA_BURST_4:
454 if (cpu_class_is_omap2())
455 burst = 0x1;
456 else
457 burst = 0x2;
458 break;
459 case OMAP_DMA_DATA_BURST_8:
460 if (cpu_class_is_omap2()) {
461 burst = 0x2;
462 break;
463 }
464 /*
465 * not supported by current hardware on OMAP1
466 * w |= (0x03 << 7);
467 * fall through
468 */
469 case OMAP_DMA_DATA_BURST_16:
470 if (cpu_class_is_omap2()) {
471 burst = 0x3;
472 break;
473 }
474 /*
475 * OMAP1 don't support burst 16
476 * fall through
477 */
478 default:
479 BUG();
480 }
481
482 l |= (burst << 7);
483 p->dma_write(l, CSDP, lch);
484 }
485 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
486
487 /* Note that dest_port is only for OMAP1 */
488 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
489 unsigned long dest_start,
490 int dst_ei, int dst_fi)
491 {
492 u32 l;
493
494 if (cpu_class_is_omap1()) {
495 l = p->dma_read(CSDP, lch);
496 l &= ~(0x1f << 9);
497 l |= dest_port << 9;
498 p->dma_write(l, CSDP, lch);
499 }
500
501 l = p->dma_read(CCR, lch);
502 l &= ~(0x03 << 14);
503 l |= dest_amode << 14;
504 p->dma_write(l, CCR, lch);
505
506 p->dma_write(dest_start, CDSA, lch);
507
508 p->dma_write(dst_ei, CDEI, lch);
509 p->dma_write(dst_fi, CDFI, lch);
510 }
511 EXPORT_SYMBOL(omap_set_dma_dest_params);
512
513 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
514 {
515 if (cpu_class_is_omap2())
516 return;
517
518 p->dma_write(eidx, CDEI, lch);
519 p->dma_write(fidx, CDFI, lch);
520 }
521 EXPORT_SYMBOL(omap_set_dma_dest_index);
522
523 void omap_set_dma_dest_data_pack(int lch, int enable)
524 {
525 u32 l;
526
527 l = p->dma_read(CSDP, lch);
528 l &= ~(1 << 13);
529 if (enable)
530 l |= 1 << 13;
531 p->dma_write(l, CSDP, lch);
532 }
533 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
534
535 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
536 {
537 unsigned int burst = 0;
538 u32 l;
539
540 l = p->dma_read(CSDP, lch);
541 l &= ~(0x03 << 14);
542
543 switch (burst_mode) {
544 case OMAP_DMA_DATA_BURST_DIS:
545 break;
546 case OMAP_DMA_DATA_BURST_4:
547 if (cpu_class_is_omap2())
548 burst = 0x1;
549 else
550 burst = 0x2;
551 break;
552 case OMAP_DMA_DATA_BURST_8:
553 if (cpu_class_is_omap2())
554 burst = 0x2;
555 else
556 burst = 0x3;
557 break;
558 case OMAP_DMA_DATA_BURST_16:
559 if (cpu_class_is_omap2()) {
560 burst = 0x3;
561 break;
562 }
563 /*
564 * OMAP1 don't support burst 16
565 * fall through
566 */
567 default:
568 printk(KERN_ERR "Invalid DMA burst mode\n");
569 BUG();
570 return;
571 }
572 l |= (burst << 14);
573 p->dma_write(l, CSDP, lch);
574 }
575 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
576
577 static inline void omap_enable_channel_irq(int lch)
578 {
579 /* Clear CSR */
580 if (cpu_class_is_omap1())
581 p->dma_read(CSR, lch);
582 else
583 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
584
585 /* Enable some nice interrupts. */
586 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
587 }
588
589 static inline void omap_disable_channel_irq(int lch)
590 {
591 /* disable channel interrupts */
592 p->dma_write(0, CICR, lch);
593 /* Clear CSR */
594 if (cpu_class_is_omap1())
595 p->dma_read(CSR, lch);
596 else
597 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
598 }
599
600 void omap_enable_dma_irq(int lch, u16 bits)
601 {
602 dma_chan[lch].enabled_irqs |= bits;
603 }
604 EXPORT_SYMBOL(omap_enable_dma_irq);
605
606 void omap_disable_dma_irq(int lch, u16 bits)
607 {
608 dma_chan[lch].enabled_irqs &= ~bits;
609 }
610 EXPORT_SYMBOL(omap_disable_dma_irq);
611
612 static inline void enable_lnk(int lch)
613 {
614 u32 l;
615
616 l = p->dma_read(CLNK_CTRL, lch);
617
618 if (cpu_class_is_omap1())
619 l &= ~(1 << 14);
620
621 /* Set the ENABLE_LNK bits */
622 if (dma_chan[lch].next_lch != -1)
623 l = dma_chan[lch].next_lch | (1 << 15);
624
625 #ifndef CONFIG_ARCH_OMAP1
626 if (cpu_class_is_omap2())
627 if (dma_chan[lch].next_linked_ch != -1)
628 l = dma_chan[lch].next_linked_ch | (1 << 15);
629 #endif
630
631 p->dma_write(l, CLNK_CTRL, lch);
632 }
633
634 static inline void disable_lnk(int lch)
635 {
636 u32 l;
637
638 l = p->dma_read(CLNK_CTRL, lch);
639
640 /* Disable interrupts */
641 omap_disable_channel_irq(lch);
642
643 if (cpu_class_is_omap1()) {
644 /* Set the STOP_LNK bit */
645 l |= 1 << 14;
646 }
647
648 if (cpu_class_is_omap2()) {
649 /* Clear the ENABLE_LNK bit */
650 l &= ~(1 << 15);
651 }
652
653 p->dma_write(l, CLNK_CTRL, lch);
654 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
655 }
656
657 static inline void omap2_enable_irq_lch(int lch)
658 {
659 u32 val;
660 unsigned long flags;
661
662 if (!cpu_class_is_omap2())
663 return;
664
665 spin_lock_irqsave(&dma_chan_lock, flags);
666 /* clear IRQ STATUS */
667 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
668 /* Enable interrupt */
669 val = p->dma_read(IRQENABLE_L0, lch);
670 val |= 1 << lch;
671 p->dma_write(val, IRQENABLE_L0, lch);
672 spin_unlock_irqrestore(&dma_chan_lock, flags);
673 }
674
675 static inline void omap2_disable_irq_lch(int lch)
676 {
677 u32 val;
678 unsigned long flags;
679
680 if (!cpu_class_is_omap2())
681 return;
682
683 spin_lock_irqsave(&dma_chan_lock, flags);
684 /* Disable interrupt */
685 val = p->dma_read(IRQENABLE_L0, lch);
686 val &= ~(1 << lch);
687 p->dma_write(val, IRQENABLE_L0, lch);
688 /* clear IRQ STATUS */
689 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
690 spin_unlock_irqrestore(&dma_chan_lock, flags);
691 }
692
693 int omap_request_dma(int dev_id, const char *dev_name,
694 void (*callback)(int lch, u16 ch_status, void *data),
695 void *data, int *dma_ch_out)
696 {
697 int ch, free_ch = -1;
698 unsigned long flags;
699 struct omap_dma_lch *chan;
700
701 spin_lock_irqsave(&dma_chan_lock, flags);
702 for (ch = 0; ch < dma_chan_count; ch++) {
703 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
704 free_ch = ch;
705 if (dev_id == 0)
706 break;
707 }
708 }
709 if (free_ch == -1) {
710 spin_unlock_irqrestore(&dma_chan_lock, flags);
711 return -EBUSY;
712 }
713 chan = dma_chan + free_ch;
714 chan->dev_id = dev_id;
715
716 if (p->clear_lch_regs)
717 p->clear_lch_regs(free_ch);
718
719 if (cpu_class_is_omap2())
720 omap_clear_dma(free_ch);
721
722 spin_unlock_irqrestore(&dma_chan_lock, flags);
723
724 chan->dev_name = dev_name;
725 chan->callback = callback;
726 chan->data = data;
727 chan->flags = 0;
728
729 #ifndef CONFIG_ARCH_OMAP1
730 if (cpu_class_is_omap2()) {
731 chan->chain_id = -1;
732 chan->next_linked_ch = -1;
733 }
734 #endif
735
736 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
737
738 if (cpu_class_is_omap1())
739 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
740 else if (cpu_class_is_omap2())
741 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
742 OMAP2_DMA_TRANS_ERR_IRQ;
743
744 if (cpu_is_omap16xx()) {
745 /* If the sync device is set, configure it dynamically. */
746 if (dev_id != 0) {
747 set_gdma_dev(free_ch + 1, dev_id);
748 dev_id = free_ch + 1;
749 }
750 /*
751 * Disable the 1510 compatibility mode and set the sync device
752 * id.
753 */
754 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
755 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
756 p->dma_write(dev_id, CCR, free_ch);
757 }
758
759 if (cpu_class_is_omap2()) {
760 omap_enable_channel_irq(free_ch);
761 omap2_enable_irq_lch(free_ch);
762 }
763
764 *dma_ch_out = free_ch;
765
766 return 0;
767 }
768 EXPORT_SYMBOL(omap_request_dma);
769
770 void omap_free_dma(int lch)
771 {
772 unsigned long flags;
773
774 if (dma_chan[lch].dev_id == -1) {
775 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
776 lch);
777 return;
778 }
779
780 /* Disable interrupt for logical channel */
781 if (cpu_class_is_omap2())
782 omap2_disable_irq_lch(lch);
783
784 /* Disable all DMA interrupts for the channel. */
785 omap_disable_channel_irq(lch);
786
787 /* Make sure the DMA transfer is stopped. */
788 p->dma_write(0, CCR, lch);
789
790 /* Clear registers */
791 if (cpu_class_is_omap2())
792 omap_clear_dma(lch);
793
794 spin_lock_irqsave(&dma_chan_lock, flags);
795 dma_chan[lch].dev_id = -1;
796 dma_chan[lch].next_lch = -1;
797 dma_chan[lch].callback = NULL;
798 spin_unlock_irqrestore(&dma_chan_lock, flags);
799 }
800 EXPORT_SYMBOL(omap_free_dma);
801
802 /**
803 * @brief omap_dma_set_global_params : Set global priority settings for dma
804 *
805 * @param arb_rate
806 * @param max_fifo_depth
807 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
808 * DMA_THREAD_RESERVE_ONET
809 * DMA_THREAD_RESERVE_TWOT
810 * DMA_THREAD_RESERVE_THREET
811 */
812 void
813 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
814 {
815 u32 reg;
816
817 if (!cpu_class_is_omap2()) {
818 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
819 return;
820 }
821
822 if (max_fifo_depth == 0)
823 max_fifo_depth = 1;
824 if (arb_rate == 0)
825 arb_rate = 1;
826
827 reg = 0xff & max_fifo_depth;
828 reg |= (0x3 & tparams) << 12;
829 reg |= (arb_rate & 0xff) << 16;
830
831 p->dma_write(reg, GCR, 0);
832 }
833 EXPORT_SYMBOL(omap_dma_set_global_params);
834
835 /**
836 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
837 *
838 * @param lch
839 * @param read_prio - Read priority
840 * @param write_prio - Write priority
841 * Both of the above can be set with one of the following values :
842 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
843 */
844 int
845 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
846 unsigned char write_prio)
847 {
848 u32 l;
849
850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
851 printk(KERN_ERR "Invalid channel id\n");
852 return -EINVAL;
853 }
854 l = p->dma_read(CCR, lch);
855 l &= ~((1 << 6) | (1 << 26));
856 if (cpu_class_is_omap2() && !cpu_is_omap242x())
857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
858 else
859 l |= ((read_prio & 0x1) << 6);
860
861 p->dma_write(l, CCR, lch);
862
863 return 0;
864 }
865 EXPORT_SYMBOL(omap_dma_set_prio_lch);
866
867 /*
868 * Clears any DMA state so the DMA engine is ready to restart with new buffers
869 * through omap_start_dma(). Any buffers in flight are discarded.
870 */
871 void omap_clear_dma(int lch)
872 {
873 unsigned long flags;
874
875 local_irq_save(flags);
876 p->clear_dma(lch);
877 local_irq_restore(flags);
878 }
879 EXPORT_SYMBOL(omap_clear_dma);
880
881 void omap_start_dma(int lch)
882 {
883 u32 l;
884
885 /*
886 * The CPC/CDAC register needs to be initialized to zero
887 * before starting dma transfer.
888 */
889 if (cpu_is_omap15xx())
890 p->dma_write(0, CPC, lch);
891 else
892 p->dma_write(0, CDAC, lch);
893
894 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
895 int next_lch, cur_lch;
896 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
897
898 dma_chan_link_map[lch] = 1;
899 /* Set the link register of the first channel */
900 enable_lnk(lch);
901
902 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
903 cur_lch = dma_chan[lch].next_lch;
904 do {
905 next_lch = dma_chan[cur_lch].next_lch;
906
907 /* The loop case: we've been here already */
908 if (dma_chan_link_map[cur_lch])
909 break;
910 /* Mark the current channel */
911 dma_chan_link_map[cur_lch] = 1;
912
913 enable_lnk(cur_lch);
914 omap_enable_channel_irq(cur_lch);
915
916 cur_lch = next_lch;
917 } while (next_lch != -1);
918 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
919 p->dma_write(lch, CLNK_CTRL, lch);
920
921 omap_enable_channel_irq(lch);
922
923 l = p->dma_read(CCR, lch);
924
925 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
926 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
927 l |= OMAP_DMA_CCR_EN;
928
929 /*
930 * As dma_write() uses IO accessors which are weakly ordered, there
931 * is no guarantee that data in coherent DMA memory will be visible
932 * to the DMA device. Add a memory barrier here to ensure that any
933 * such data is visible prior to enabling DMA.
934 */
935 mb();
936 p->dma_write(l, CCR, lch);
937
938 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
939 }
940 EXPORT_SYMBOL(omap_start_dma);
941
942 void omap_stop_dma(int lch)
943 {
944 u32 l;
945
946 /* Disable all interrupts on the channel */
947 omap_disable_channel_irq(lch);
948
949 l = p->dma_read(CCR, lch);
950 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
951 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
952 int i = 0;
953 u32 sys_cf;
954
955 /* Configure No-Standby */
956 l = p->dma_read(OCP_SYSCONFIG, lch);
957 sys_cf = l;
958 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
959 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
960 p->dma_write(l , OCP_SYSCONFIG, 0);
961
962 l = p->dma_read(CCR, lch);
963 l &= ~OMAP_DMA_CCR_EN;
964 p->dma_write(l, CCR, lch);
965
966 /* Wait for sDMA FIFO drain */
967 l = p->dma_read(CCR, lch);
968 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
969 OMAP_DMA_CCR_WR_ACTIVE))) {
970 udelay(5);
971 i++;
972 l = p->dma_read(CCR, lch);
973 }
974 if (i >= 100)
975 pr_err("DMA drain did not complete on lch %d\n", lch);
976 /* Restore OCP_SYSCONFIG */
977 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
978 } else {
979 l &= ~OMAP_DMA_CCR_EN;
980 p->dma_write(l, CCR, lch);
981 }
982
983 /*
984 * Ensure that data transferred by DMA is visible to any access
985 * after DMA has been disabled. This is important for coherent
986 * DMA regions.
987 */
988 mb();
989
990 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
991 int next_lch, cur_lch = lch;
992 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
993
994 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
995 do {
996 /* The loop case: we've been here already */
997 if (dma_chan_link_map[cur_lch])
998 break;
999 /* Mark the current channel */
1000 dma_chan_link_map[cur_lch] = 1;
1001
1002 disable_lnk(cur_lch);
1003
1004 next_lch = dma_chan[cur_lch].next_lch;
1005 cur_lch = next_lch;
1006 } while (next_lch != -1);
1007 }
1008
1009 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1010 }
1011 EXPORT_SYMBOL(omap_stop_dma);
1012
1013 /*
1014 * Allows changing the DMA callback function or data. This may be needed if
1015 * the driver shares a single DMA channel for multiple dma triggers.
1016 */
1017 int omap_set_dma_callback(int lch,
1018 void (*callback)(int lch, u16 ch_status, void *data),
1019 void *data)
1020 {
1021 unsigned long flags;
1022
1023 if (lch < 0)
1024 return -ENODEV;
1025
1026 spin_lock_irqsave(&dma_chan_lock, flags);
1027 if (dma_chan[lch].dev_id == -1) {
1028 printk(KERN_ERR "DMA callback for not set for free channel\n");
1029 spin_unlock_irqrestore(&dma_chan_lock, flags);
1030 return -EINVAL;
1031 }
1032 dma_chan[lch].callback = callback;
1033 dma_chan[lch].data = data;
1034 spin_unlock_irqrestore(&dma_chan_lock, flags);
1035
1036 return 0;
1037 }
1038 EXPORT_SYMBOL(omap_set_dma_callback);
1039
1040 /*
1041 * Returns current physical source address for the given DMA channel.
1042 * If the channel is running the caller must disable interrupts prior calling
1043 * this function and process the returned value before re-enabling interrupt to
1044 * prevent races with the interrupt handler. Note that in continuous mode there
1045 * is a chance for CSSA_L register overflow between the two reads resulting
1046 * in incorrect return value.
1047 */
1048 dma_addr_t omap_get_dma_src_pos(int lch)
1049 {
1050 dma_addr_t offset = 0;
1051
1052 if (cpu_is_omap15xx())
1053 offset = p->dma_read(CPC, lch);
1054 else
1055 offset = p->dma_read(CSAC, lch);
1056
1057 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1058 offset = p->dma_read(CSAC, lch);
1059
1060 if (!cpu_is_omap15xx()) {
1061 /*
1062 * CDAC == 0 indicates that the DMA transfer on the channel has
1063 * not been started (no data has been transferred so far).
1064 * Return the programmed source start address in this case.
1065 */
1066 if (likely(p->dma_read(CDAC, lch)))
1067 offset = p->dma_read(CSAC, lch);
1068 else
1069 offset = p->dma_read(CSSA, lch);
1070 }
1071
1072 if (cpu_class_is_omap1())
1073 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1074
1075 return offset;
1076 }
1077 EXPORT_SYMBOL(omap_get_dma_src_pos);
1078
1079 /*
1080 * Returns current physical destination address for the given DMA channel.
1081 * If the channel is running the caller must disable interrupts prior calling
1082 * this function and process the returned value before re-enabling interrupt to
1083 * prevent races with the interrupt handler. Note that in continuous mode there
1084 * is a chance for CDSA_L register overflow between the two reads resulting
1085 * in incorrect return value.
1086 */
1087 dma_addr_t omap_get_dma_dst_pos(int lch)
1088 {
1089 dma_addr_t offset = 0;
1090
1091 if (cpu_is_omap15xx())
1092 offset = p->dma_read(CPC, lch);
1093 else
1094 offset = p->dma_read(CDAC, lch);
1095
1096 /*
1097 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1098 * read before the DMA controller finished disabling the channel.
1099 */
1100 if (!cpu_is_omap15xx() && offset == 0) {
1101 offset = p->dma_read(CDAC, lch);
1102 /*
1103 * CDAC == 0 indicates that the DMA transfer on the channel has
1104 * not been started (no data has been transferred so far).
1105 * Return the programmed destination start address in this case.
1106 */
1107 if (unlikely(!offset))
1108 offset = p->dma_read(CDSA, lch);
1109 }
1110
1111 if (cpu_class_is_omap1())
1112 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1113
1114 return offset;
1115 }
1116 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1117
1118 int omap_get_dma_active_status(int lch)
1119 {
1120 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1121 }
1122 EXPORT_SYMBOL(omap_get_dma_active_status);
1123
1124 int omap_dma_running(void)
1125 {
1126 int lch;
1127
1128 if (cpu_class_is_omap1())
1129 if (omap_lcd_dma_running())
1130 return 1;
1131
1132 for (lch = 0; lch < dma_chan_count; lch++)
1133 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1134 return 1;
1135
1136 return 0;
1137 }
1138
1139 /*
1140 * lch_queue DMA will start right after lch_head one is finished.
1141 * For this DMA link to start, you still need to start (see omap_start_dma)
1142 * the first one. That will fire up the entire queue.
1143 */
1144 void omap_dma_link_lch(int lch_head, int lch_queue)
1145 {
1146 if (omap_dma_in_1510_mode()) {
1147 if (lch_head == lch_queue) {
1148 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1149 CCR, lch_head);
1150 return;
1151 }
1152 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1153 BUG();
1154 return;
1155 }
1156
1157 if ((dma_chan[lch_head].dev_id == -1) ||
1158 (dma_chan[lch_queue].dev_id == -1)) {
1159 pr_err("omap_dma: trying to link non requested channels\n");
1160 dump_stack();
1161 }
1162
1163 dma_chan[lch_head].next_lch = lch_queue;
1164 }
1165 EXPORT_SYMBOL(omap_dma_link_lch);
1166
1167 /*
1168 * Once the DMA queue is stopped, we can destroy it.
1169 */
1170 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1171 {
1172 if (omap_dma_in_1510_mode()) {
1173 if (lch_head == lch_queue) {
1174 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1175 CCR, lch_head);
1176 return;
1177 }
1178 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1179 BUG();
1180 return;
1181 }
1182
1183 if (dma_chan[lch_head].next_lch != lch_queue ||
1184 dma_chan[lch_head].next_lch == -1) {
1185 pr_err("omap_dma: trying to unlink non linked channels\n");
1186 dump_stack();
1187 }
1188
1189 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1190 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1191 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1192 dump_stack();
1193 }
1194
1195 dma_chan[lch_head].next_lch = -1;
1196 }
1197 EXPORT_SYMBOL(omap_dma_unlink_lch);
1198
1199 #ifndef CONFIG_ARCH_OMAP1
1200 /* Create chain of DMA channesls */
1201 static void create_dma_lch_chain(int lch_head, int lch_queue)
1202 {
1203 u32 l;
1204
1205 /* Check if this is the first link in chain */
1206 if (dma_chan[lch_head].next_linked_ch == -1) {
1207 dma_chan[lch_head].next_linked_ch = lch_queue;
1208 dma_chan[lch_head].prev_linked_ch = lch_queue;
1209 dma_chan[lch_queue].next_linked_ch = lch_head;
1210 dma_chan[lch_queue].prev_linked_ch = lch_head;
1211 }
1212
1213 /* a link exists, link the new channel in circular chain */
1214 else {
1215 dma_chan[lch_queue].next_linked_ch =
1216 dma_chan[lch_head].next_linked_ch;
1217 dma_chan[lch_queue].prev_linked_ch = lch_head;
1218 dma_chan[lch_head].next_linked_ch = lch_queue;
1219 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1220 lch_queue;
1221 }
1222
1223 l = p->dma_read(CLNK_CTRL, lch_head);
1224 l &= ~(0x1f);
1225 l |= lch_queue;
1226 p->dma_write(l, CLNK_CTRL, lch_head);
1227
1228 l = p->dma_read(CLNK_CTRL, lch_queue);
1229 l &= ~(0x1f);
1230 l |= (dma_chan[lch_queue].next_linked_ch);
1231 p->dma_write(l, CLNK_CTRL, lch_queue);
1232 }
1233
1234 /**
1235 * @brief omap_request_dma_chain : Request a chain of DMA channels
1236 *
1237 * @param dev_id - Device id using the dma channel
1238 * @param dev_name - Device name
1239 * @param callback - Call back function
1240 * @chain_id -
1241 * @no_of_chans - Number of channels requested
1242 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1243 * OMAP_DMA_DYNAMIC_CHAIN
1244 * @params - Channel parameters
1245 *
1246 * @return - Success : 0
1247 * Failure: -EINVAL/-ENOMEM
1248 */
1249 int omap_request_dma_chain(int dev_id, const char *dev_name,
1250 void (*callback) (int lch, u16 ch_status,
1251 void *data),
1252 int *chain_id, int no_of_chans, int chain_mode,
1253 struct omap_dma_channel_params params)
1254 {
1255 int *channels;
1256 int i, err;
1257
1258 /* Is the chain mode valid ? */
1259 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1260 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1261 printk(KERN_ERR "Invalid chain mode requested\n");
1262 return -EINVAL;
1263 }
1264
1265 if (unlikely((no_of_chans < 1
1266 || no_of_chans > dma_lch_count))) {
1267 printk(KERN_ERR "Invalid Number of channels requested\n");
1268 return -EINVAL;
1269 }
1270
1271 /*
1272 * Allocate a queue to maintain the status of the channels
1273 * in the chain
1274 */
1275 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1276 if (channels == NULL) {
1277 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1278 return -ENOMEM;
1279 }
1280
1281 /* request and reserve DMA channels for the chain */
1282 for (i = 0; i < no_of_chans; i++) {
1283 err = omap_request_dma(dev_id, dev_name,
1284 callback, NULL, &channels[i]);
1285 if (err < 0) {
1286 int j;
1287 for (j = 0; j < i; j++)
1288 omap_free_dma(channels[j]);
1289 kfree(channels);
1290 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1291 return err;
1292 }
1293 dma_chan[channels[i]].prev_linked_ch = -1;
1294 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1295
1296 /*
1297 * Allowing client drivers to set common parameters now,
1298 * so that later only relevant (src_start, dest_start
1299 * and element count) can be set
1300 */
1301 omap_set_dma_params(channels[i], &params);
1302 }
1303
1304 *chain_id = channels[0];
1305 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1306 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1307 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1308 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1309
1310 for (i = 0; i < no_of_chans; i++)
1311 dma_chan[channels[i]].chain_id = *chain_id;
1312
1313 /* Reset the Queue pointers */
1314 OMAP_DMA_CHAIN_QINIT(*chain_id);
1315
1316 /* Set up the chain */
1317 if (no_of_chans == 1)
1318 create_dma_lch_chain(channels[0], channels[0]);
1319 else {
1320 for (i = 0; i < (no_of_chans - 1); i++)
1321 create_dma_lch_chain(channels[i], channels[i + 1]);
1322 }
1323
1324 return 0;
1325 }
1326 EXPORT_SYMBOL(omap_request_dma_chain);
1327
1328 /**
1329 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1330 * params after setting it. Dont do this while dma is running!!
1331 *
1332 * @param chain_id - Chained logical channel id.
1333 * @param params
1334 *
1335 * @return - Success : 0
1336 * Failure : -EINVAL
1337 */
1338 int omap_modify_dma_chain_params(int chain_id,
1339 struct omap_dma_channel_params params)
1340 {
1341 int *channels;
1342 u32 i;
1343
1344 /* Check for input params */
1345 if (unlikely((chain_id < 0
1346 || chain_id >= dma_lch_count))) {
1347 printk(KERN_ERR "Invalid chain id\n");
1348 return -EINVAL;
1349 }
1350
1351 /* Check if the chain exists */
1352 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1353 printk(KERN_ERR "Chain doesn't exists\n");
1354 return -EINVAL;
1355 }
1356 channels = dma_linked_lch[chain_id].linked_dmach_q;
1357
1358 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1359 /*
1360 * Allowing client drivers to set common parameters now,
1361 * so that later only relevant (src_start, dest_start
1362 * and element count) can be set
1363 */
1364 omap_set_dma_params(channels[i], &params);
1365 }
1366
1367 return 0;
1368 }
1369 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1370
1371 /**
1372 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1373 *
1374 * @param chain_id
1375 *
1376 * @return - Success : 0
1377 * Failure : -EINVAL
1378 */
1379 int omap_free_dma_chain(int chain_id)
1380 {
1381 int *channels;
1382 u32 i;
1383
1384 /* Check for input params */
1385 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1386 printk(KERN_ERR "Invalid chain id\n");
1387 return -EINVAL;
1388 }
1389
1390 /* Check if the chain exists */
1391 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1392 printk(KERN_ERR "Chain doesn't exists\n");
1393 return -EINVAL;
1394 }
1395
1396 channels = dma_linked_lch[chain_id].linked_dmach_q;
1397 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1398 dma_chan[channels[i]].next_linked_ch = -1;
1399 dma_chan[channels[i]].prev_linked_ch = -1;
1400 dma_chan[channels[i]].chain_id = -1;
1401 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1402 omap_free_dma(channels[i]);
1403 }
1404
1405 kfree(channels);
1406
1407 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1408 dma_linked_lch[chain_id].chain_mode = -1;
1409 dma_linked_lch[chain_id].chain_state = -1;
1410
1411 return (0);
1412 }
1413 EXPORT_SYMBOL(omap_free_dma_chain);
1414
1415 /**
1416 * @brief omap_dma_chain_status - Check if the chain is in
1417 * active / inactive state.
1418 * @param chain_id
1419 *
1420 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1421 * Failure : -EINVAL
1422 */
1423 int omap_dma_chain_status(int chain_id)
1424 {
1425 /* Check for input params */
1426 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1427 printk(KERN_ERR "Invalid chain id\n");
1428 return -EINVAL;
1429 }
1430
1431 /* Check if the chain exists */
1432 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1433 printk(KERN_ERR "Chain doesn't exists\n");
1434 return -EINVAL;
1435 }
1436 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1437 dma_linked_lch[chain_id].q_count);
1438
1439 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1440 return OMAP_DMA_CHAIN_INACTIVE;
1441
1442 return OMAP_DMA_CHAIN_ACTIVE;
1443 }
1444 EXPORT_SYMBOL(omap_dma_chain_status);
1445
1446 /**
1447 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1448 * set the params and start the transfer.
1449 *
1450 * @param chain_id
1451 * @param src_start - buffer start address
1452 * @param dest_start - Dest address
1453 * @param elem_count
1454 * @param frame_count
1455 * @param callbk_data - channel callback parameter data.
1456 *
1457 * @return - Success : 0
1458 * Failure: -EINVAL/-EBUSY
1459 */
1460 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1461 int elem_count, int frame_count, void *callbk_data)
1462 {
1463 int *channels;
1464 u32 l, lch;
1465 int start_dma = 0;
1466
1467 /*
1468 * if buffer size is less than 1 then there is
1469 * no use of starting the chain
1470 */
1471 if (elem_count < 1) {
1472 printk(KERN_ERR "Invalid buffer size\n");
1473 return -EINVAL;
1474 }
1475
1476 /* Check for input params */
1477 if (unlikely((chain_id < 0
1478 || chain_id >= dma_lch_count))) {
1479 printk(KERN_ERR "Invalid chain id\n");
1480 return -EINVAL;
1481 }
1482
1483 /* Check if the chain exists */
1484 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1485 printk(KERN_ERR "Chain doesn't exist\n");
1486 return -EINVAL;
1487 }
1488
1489 /* Check if all the channels in chain are in use */
1490 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1491 return -EBUSY;
1492
1493 /* Frame count may be negative in case of indexed transfers */
1494 channels = dma_linked_lch[chain_id].linked_dmach_q;
1495
1496 /* Get a free channel */
1497 lch = channels[dma_linked_lch[chain_id].q_tail];
1498
1499 /* Store the callback data */
1500 dma_chan[lch].data = callbk_data;
1501
1502 /* Increment the q_tail */
1503 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1504
1505 /* Set the params to the free channel */
1506 if (src_start != 0)
1507 p->dma_write(src_start, CSSA, lch);
1508 if (dest_start != 0)
1509 p->dma_write(dest_start, CDSA, lch);
1510
1511 /* Write the buffer size */
1512 p->dma_write(elem_count, CEN, lch);
1513 p->dma_write(frame_count, CFN, lch);
1514
1515 /*
1516 * If the chain is dynamically linked,
1517 * then we may have to start the chain if its not active
1518 */
1519 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1520
1521 /*
1522 * In Dynamic chain, if the chain is not started,
1523 * queue the channel
1524 */
1525 if (dma_linked_lch[chain_id].chain_state ==
1526 DMA_CHAIN_NOTSTARTED) {
1527 /* Enable the link in previous channel */
1528 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1529 DMA_CH_QUEUED)
1530 enable_lnk(dma_chan[lch].prev_linked_ch);
1531 dma_chan[lch].state = DMA_CH_QUEUED;
1532 }
1533
1534 /*
1535 * Chain is already started, make sure its active,
1536 * if not then start the chain
1537 */
1538 else {
1539 start_dma = 1;
1540
1541 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1542 DMA_CH_STARTED) {
1543 enable_lnk(dma_chan[lch].prev_linked_ch);
1544 dma_chan[lch].state = DMA_CH_QUEUED;
1545 start_dma = 0;
1546 if (0 == ((1 << 7) & p->dma_read(
1547 CCR, dma_chan[lch].prev_linked_ch))) {
1548 disable_lnk(dma_chan[lch].
1549 prev_linked_ch);
1550 pr_debug("\n prev ch is stopped\n");
1551 start_dma = 1;
1552 }
1553 }
1554
1555 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1556 == DMA_CH_QUEUED) {
1557 enable_lnk(dma_chan[lch].prev_linked_ch);
1558 dma_chan[lch].state = DMA_CH_QUEUED;
1559 start_dma = 0;
1560 }
1561 omap_enable_channel_irq(lch);
1562
1563 l = p->dma_read(CCR, lch);
1564
1565 if ((0 == (l & (1 << 24))))
1566 l &= ~(1 << 25);
1567 else
1568 l |= (1 << 25);
1569 if (start_dma == 1) {
1570 if (0 == (l & (1 << 7))) {
1571 l |= (1 << 7);
1572 dma_chan[lch].state = DMA_CH_STARTED;
1573 pr_debug("starting %d\n", lch);
1574 p->dma_write(l, CCR, lch);
1575 } else
1576 start_dma = 0;
1577 } else {
1578 if (0 == (l & (1 << 7)))
1579 p->dma_write(l, CCR, lch);
1580 }
1581 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1582 }
1583 }
1584
1585 return 0;
1586 }
1587 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1588
1589 /**
1590 * @brief omap_start_dma_chain_transfers - Start the chain
1591 *
1592 * @param chain_id
1593 *
1594 * @return - Success : 0
1595 * Failure : -EINVAL/-EBUSY
1596 */
1597 int omap_start_dma_chain_transfers(int chain_id)
1598 {
1599 int *channels;
1600 u32 l, i;
1601
1602 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1603 printk(KERN_ERR "Invalid chain id\n");
1604 return -EINVAL;
1605 }
1606
1607 channels = dma_linked_lch[chain_id].linked_dmach_q;
1608
1609 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1610 printk(KERN_ERR "Chain is already started\n");
1611 return -EBUSY;
1612 }
1613
1614 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1615 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1616 i++) {
1617 enable_lnk(channels[i]);
1618 omap_enable_channel_irq(channels[i]);
1619 }
1620 } else {
1621 omap_enable_channel_irq(channels[0]);
1622 }
1623
1624 l = p->dma_read(CCR, channels[0]);
1625 l |= (1 << 7);
1626 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1627 dma_chan[channels[0]].state = DMA_CH_STARTED;
1628
1629 if ((0 == (l & (1 << 24))))
1630 l &= ~(1 << 25);
1631 else
1632 l |= (1 << 25);
1633 p->dma_write(l, CCR, channels[0]);
1634
1635 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1636
1637 return 0;
1638 }
1639 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1640
1641 /**
1642 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1643 *
1644 * @param chain_id
1645 *
1646 * @return - Success : 0
1647 * Failure : EINVAL
1648 */
1649 int omap_stop_dma_chain_transfers(int chain_id)
1650 {
1651 int *channels;
1652 u32 l, i;
1653 u32 sys_cf = 0;
1654
1655 /* Check for input params */
1656 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1657 printk(KERN_ERR "Invalid chain id\n");
1658 return -EINVAL;
1659 }
1660
1661 /* Check if the chain exists */
1662 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1663 printk(KERN_ERR "Chain doesn't exists\n");
1664 return -EINVAL;
1665 }
1666 channels = dma_linked_lch[chain_id].linked_dmach_q;
1667
1668 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1669 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1670 l = sys_cf;
1671 /* Middle mode reg set no Standby */
1672 l &= ~((1 << 12)|(1 << 13));
1673 p->dma_write(l, OCP_SYSCONFIG, 0);
1674 }
1675
1676 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1677
1678 /* Stop the Channel transmission */
1679 l = p->dma_read(CCR, channels[i]);
1680 l &= ~(1 << 7);
1681 p->dma_write(l, CCR, channels[i]);
1682
1683 /* Disable the link in all the channels */
1684 disable_lnk(channels[i]);
1685 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1686
1687 }
1688 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1689
1690 /* Reset the Queue pointers */
1691 OMAP_DMA_CHAIN_QINIT(chain_id);
1692
1693 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1694 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1695
1696 return 0;
1697 }
1698 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1699
1700 /* Get the index of the ongoing DMA in chain */
1701 /**
1702 * @brief omap_get_dma_chain_index - Get the element and frame index
1703 * of the ongoing DMA in chain
1704 *
1705 * @param chain_id
1706 * @param ei - Element index
1707 * @param fi - Frame index
1708 *
1709 * @return - Success : 0
1710 * Failure : -EINVAL
1711 */
1712 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1713 {
1714 int lch;
1715 int *channels;
1716
1717 /* Check for input params */
1718 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1719 printk(KERN_ERR "Invalid chain id\n");
1720 return -EINVAL;
1721 }
1722
1723 /* Check if the chain exists */
1724 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1725 printk(KERN_ERR "Chain doesn't exists\n");
1726 return -EINVAL;
1727 }
1728 if ((!ei) || (!fi))
1729 return -EINVAL;
1730
1731 channels = dma_linked_lch[chain_id].linked_dmach_q;
1732
1733 /* Get the current channel */
1734 lch = channels[dma_linked_lch[chain_id].q_head];
1735
1736 *ei = p->dma_read(CCEN, lch);
1737 *fi = p->dma_read(CCFN, lch);
1738
1739 return 0;
1740 }
1741 EXPORT_SYMBOL(omap_get_dma_chain_index);
1742
1743 /**
1744 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1745 * ongoing DMA in chain
1746 *
1747 * @param chain_id
1748 *
1749 * @return - Success : Destination position
1750 * Failure : -EINVAL
1751 */
1752 int omap_get_dma_chain_dst_pos(int chain_id)
1753 {
1754 int lch;
1755 int *channels;
1756
1757 /* Check for input params */
1758 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1759 printk(KERN_ERR "Invalid chain id\n");
1760 return -EINVAL;
1761 }
1762
1763 /* Check if the chain exists */
1764 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1765 printk(KERN_ERR "Chain doesn't exists\n");
1766 return -EINVAL;
1767 }
1768
1769 channels = dma_linked_lch[chain_id].linked_dmach_q;
1770
1771 /* Get the current channel */
1772 lch = channels[dma_linked_lch[chain_id].q_head];
1773
1774 return p->dma_read(CDAC, lch);
1775 }
1776 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1777
1778 /**
1779 * @brief omap_get_dma_chain_src_pos - Get the source position
1780 * of the ongoing DMA in chain
1781 * @param chain_id
1782 *
1783 * @return - Success : Destination position
1784 * Failure : -EINVAL
1785 */
1786 int omap_get_dma_chain_src_pos(int chain_id)
1787 {
1788 int lch;
1789 int *channels;
1790
1791 /* Check for input params */
1792 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1793 printk(KERN_ERR "Invalid chain id\n");
1794 return -EINVAL;
1795 }
1796
1797 /* Check if the chain exists */
1798 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1799 printk(KERN_ERR "Chain doesn't exists\n");
1800 return -EINVAL;
1801 }
1802
1803 channels = dma_linked_lch[chain_id].linked_dmach_q;
1804
1805 /* Get the current channel */
1806 lch = channels[dma_linked_lch[chain_id].q_head];
1807
1808 return p->dma_read(CSAC, lch);
1809 }
1810 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1811 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1812
1813 /*----------------------------------------------------------------------------*/
1814
1815 #ifdef CONFIG_ARCH_OMAP1
1816
1817 static int omap1_dma_handle_ch(int ch)
1818 {
1819 u32 csr;
1820
1821 if (enable_1510_mode && ch >= 6) {
1822 csr = dma_chan[ch].saved_csr;
1823 dma_chan[ch].saved_csr = 0;
1824 } else
1825 csr = p->dma_read(CSR, ch);
1826 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1827 dma_chan[ch + 6].saved_csr = csr >> 7;
1828 csr &= 0x7f;
1829 }
1830 if ((csr & 0x3f) == 0)
1831 return 0;
1832 if (unlikely(dma_chan[ch].dev_id == -1)) {
1833 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1834 ch, csr);
1835 return 0;
1836 }
1837 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1838 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1839 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1840 pr_warn("DMA synchronization event drop occurred with device %d\n",
1841 dma_chan[ch].dev_id);
1842 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1843 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1844 if (likely(dma_chan[ch].callback != NULL))
1845 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1846
1847 return 1;
1848 }
1849
1850 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1851 {
1852 int ch = ((int) dev_id) - 1;
1853 int handled = 0;
1854
1855 for (;;) {
1856 int handled_now = 0;
1857
1858 handled_now += omap1_dma_handle_ch(ch);
1859 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1860 handled_now += omap1_dma_handle_ch(ch + 6);
1861 if (!handled_now)
1862 break;
1863 handled += handled_now;
1864 }
1865
1866 return handled ? IRQ_HANDLED : IRQ_NONE;
1867 }
1868
1869 #else
1870 #define omap1_dma_irq_handler NULL
1871 #endif
1872
1873 #ifdef CONFIG_ARCH_OMAP2PLUS
1874
1875 static int omap2_dma_handle_ch(int ch)
1876 {
1877 u32 status = p->dma_read(CSR, ch);
1878
1879 if (!status) {
1880 if (printk_ratelimit())
1881 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1882 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1883 return 0;
1884 }
1885 if (unlikely(dma_chan[ch].dev_id == -1)) {
1886 if (printk_ratelimit())
1887 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1888 status, ch);
1889 return 0;
1890 }
1891 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1892 pr_info("DMA synchronization event drop occurred with device %d\n",
1893 dma_chan[ch].dev_id);
1894 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1895 printk(KERN_INFO "DMA transaction error with device %d\n",
1896 dma_chan[ch].dev_id);
1897 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1898 u32 ccr;
1899
1900 ccr = p->dma_read(CCR, ch);
1901 ccr &= ~OMAP_DMA_CCR_EN;
1902 p->dma_write(ccr, CCR, ch);
1903 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1904 }
1905 }
1906 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1907 printk(KERN_INFO "DMA secure error with device %d\n",
1908 dma_chan[ch].dev_id);
1909 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1910 printk(KERN_INFO "DMA misaligned error with device %d\n",
1911 dma_chan[ch].dev_id);
1912
1913 p->dma_write(status, CSR, ch);
1914 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1915 /* read back the register to flush the write */
1916 p->dma_read(IRQSTATUS_L0, ch);
1917
1918 /* If the ch is not chained then chain_id will be -1 */
1919 if (dma_chan[ch].chain_id != -1) {
1920 int chain_id = dma_chan[ch].chain_id;
1921 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1922 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1923 dma_chan[dma_chan[ch].next_linked_ch].state =
1924 DMA_CH_STARTED;
1925 if (dma_linked_lch[chain_id].chain_mode ==
1926 OMAP_DMA_DYNAMIC_CHAIN)
1927 disable_lnk(ch);
1928
1929 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1930 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1931
1932 status = p->dma_read(CSR, ch);
1933 p->dma_write(status, CSR, ch);
1934 }
1935
1936 if (likely(dma_chan[ch].callback != NULL))
1937 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1938
1939 return 0;
1940 }
1941
1942 /* STATUS register count is from 1-32 while our is 0-31 */
1943 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1944 {
1945 u32 val, enable_reg;
1946 int i;
1947
1948 val = p->dma_read(IRQSTATUS_L0, 0);
1949 if (val == 0) {
1950 if (printk_ratelimit())
1951 printk(KERN_WARNING "Spurious DMA IRQ\n");
1952 return IRQ_HANDLED;
1953 }
1954 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1955 val &= enable_reg; /* Dispatch only relevant interrupts */
1956 for (i = 0; i < dma_lch_count && val != 0; i++) {
1957 if (val & 1)
1958 omap2_dma_handle_ch(i);
1959 val >>= 1;
1960 }
1961
1962 return IRQ_HANDLED;
1963 }
1964
1965 static struct irqaction omap24xx_dma_irq = {
1966 .name = "DMA",
1967 .handler = omap2_dma_irq_handler,
1968 .flags = IRQF_DISABLED
1969 };
1970
1971 #else
1972 static struct irqaction omap24xx_dma_irq;
1973 #endif
1974
1975 /*----------------------------------------------------------------------------*/
1976
1977 void omap_dma_global_context_save(void)
1978 {
1979 omap_dma_global_context.dma_irqenable_l0 =
1980 p->dma_read(IRQENABLE_L0, 0);
1981 omap_dma_global_context.dma_ocp_sysconfig =
1982 p->dma_read(OCP_SYSCONFIG, 0);
1983 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1984 }
1985
1986 void omap_dma_global_context_restore(void)
1987 {
1988 int ch;
1989
1990 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1991 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1992 OCP_SYSCONFIG, 0);
1993 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1994 IRQENABLE_L0, 0);
1995
1996 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1997 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1998
1999 for (ch = 0; ch < dma_chan_count; ch++)
2000 if (dma_chan[ch].dev_id != -1)
2001 omap_clear_dma(ch);
2002 }
2003
2004 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2005 {
2006 int ch, ret = 0;
2007 int dma_irq;
2008 char irq_name[4];
2009 int irq_rel;
2010
2011 p = pdev->dev.platform_data;
2012 if (!p) {
2013 dev_err(&pdev->dev,
2014 "%s: System DMA initialized without platform data\n",
2015 __func__);
2016 return -EINVAL;
2017 }
2018
2019 d = p->dma_attr;
2020 errata = p->errata;
2021
2022 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2023 && (omap_dma_reserve_channels <= dma_lch_count))
2024 d->lch_count = omap_dma_reserve_channels;
2025
2026 dma_lch_count = d->lch_count;
2027 dma_chan_count = dma_lch_count;
2028 dma_chan = d->chan;
2029 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2030
2031 if (cpu_class_is_omap2()) {
2032 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2033 dma_lch_count, GFP_KERNEL);
2034 if (!dma_linked_lch) {
2035 ret = -ENOMEM;
2036 goto exit_dma_lch_fail;
2037 }
2038 }
2039
2040 spin_lock_init(&dma_chan_lock);
2041 for (ch = 0; ch < dma_chan_count; ch++) {
2042 omap_clear_dma(ch);
2043 if (cpu_class_is_omap2())
2044 omap2_disable_irq_lch(ch);
2045
2046 dma_chan[ch].dev_id = -1;
2047 dma_chan[ch].next_lch = -1;
2048
2049 if (ch >= 6 && enable_1510_mode)
2050 continue;
2051
2052 if (cpu_class_is_omap1()) {
2053 /*
2054 * request_irq() doesn't like dev_id (ie. ch) being
2055 * zero, so we have to kludge around this.
2056 */
2057 sprintf(&irq_name[0], "%d", ch);
2058 dma_irq = platform_get_irq_byname(pdev, irq_name);
2059
2060 if (dma_irq < 0) {
2061 ret = dma_irq;
2062 goto exit_dma_irq_fail;
2063 }
2064
2065 /* INT_DMA_LCD is handled in lcd_dma.c */
2066 if (dma_irq == INT_DMA_LCD)
2067 continue;
2068
2069 ret = request_irq(dma_irq,
2070 omap1_dma_irq_handler, 0, "DMA",
2071 (void *) (ch + 1));
2072 if (ret != 0)
2073 goto exit_dma_irq_fail;
2074 }
2075 }
2076
2077 if (cpu_class_is_omap2() && !cpu_is_omap242x())
2078 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2079 DMA_DEFAULT_FIFO_DEPTH, 0);
2080
2081 if (cpu_class_is_omap2()) {
2082 strcpy(irq_name, "0");
2083 dma_irq = platform_get_irq_byname(pdev, irq_name);
2084 if (dma_irq < 0) {
2085 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2086 goto exit_dma_lch_fail;
2087 }
2088 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2089 if (ret) {
2090 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
2091 dma_irq, ret);
2092 goto exit_dma_lch_fail;
2093 }
2094 }
2095
2096 /* reserve dma channels 0 and 1 in high security devices */
2097 if (cpu_is_omap34xx() &&
2098 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2099 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2100 dma_chan[0].dev_id = 0;
2101 dma_chan[1].dev_id = 1;
2102 }
2103 p->show_dma_caps();
2104 return 0;
2105
2106 exit_dma_irq_fail:
2107 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
2108 dma_irq, ret);
2109 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2110 dma_irq = platform_get_irq(pdev, irq_rel);
2111 free_irq(dma_irq, (void *)(irq_rel + 1));
2112 }
2113
2114 exit_dma_lch_fail:
2115 kfree(p);
2116 kfree(d);
2117 kfree(dma_chan);
2118 return ret;
2119 }
2120
2121 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2122 {
2123 int dma_irq;
2124
2125 if (cpu_class_is_omap2()) {
2126 char irq_name[4];
2127 strcpy(irq_name, "0");
2128 dma_irq = platform_get_irq_byname(pdev, irq_name);
2129 remove_irq(dma_irq, &omap24xx_dma_irq);
2130 } else {
2131 int irq_rel = 0;
2132 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2133 dma_irq = platform_get_irq(pdev, irq_rel);
2134 free_irq(dma_irq, (void *)(irq_rel + 1));
2135 }
2136 }
2137 kfree(p);
2138 kfree(d);
2139 kfree(dma_chan);
2140 return 0;
2141 }
2142
2143 static struct platform_driver omap_system_dma_driver = {
2144 .probe = omap_system_dma_probe,
2145 .remove = __devexit_p(omap_system_dma_remove),
2146 .driver = {
2147 .name = "omap_dma_system"
2148 },
2149 };
2150
2151 static int __init omap_system_dma_init(void)
2152 {
2153 return platform_driver_register(&omap_system_dma_driver);
2154 }
2155 arch_initcall(omap_system_dma_init);
2156
2157 static void __exit omap_system_dma_exit(void)
2158 {
2159 platform_driver_unregister(&omap_system_dma_driver);
2160 }
2161
2162 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2163 MODULE_LICENSE("GPL");
2164 MODULE_ALIAS("platform:" DRIVER_NAME);
2165 MODULE_AUTHOR("Texas Instruments Inc");
2166
2167 /*
2168 * Reserve the omap SDMA channels using cmdline bootarg
2169 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2170 */
2171 static int __init omap_dma_cmdline_reserve_ch(char *str)
2172 {
2173 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2174 omap_dma_reserve_channels = 0;
2175 return 1;
2176 }
2177
2178 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2179
2180
Linux kernel - Deliverables
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