2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
30 #include <asm/system.h>
31 #include <mach/hardware.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
40 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode
;
60 void (*callback
)(int lch
, u16 ch_status
, void *data
);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 struct dma_link_info
{
77 int no_of_lchs_linked
;
88 static struct dma_link_info
*dma_linked_lch
;
90 #ifndef CONFIG_ARCH_OMAP1
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
124 static int dma_lch_count
;
125 static int dma_chan_count
;
126 static int omap_dma_reserve_channels
;
128 static spinlock_t dma_chan_lock
;
129 static struct omap_dma_lch
*dma_chan
;
130 static void __iomem
*omap_dma_base
;
132 static const u8 omap1_dma_irq
[OMAP1_LOGICAL_DMA_CH_COUNT
] = {
133 INT_DMA_CH0_6
, INT_DMA_CH1_7
, INT_DMA_CH2_8
, INT_DMA_CH3
,
134 INT_DMA_CH4
, INT_DMA_CH5
, INT_1610_DMA_CH6
, INT_1610_DMA_CH7
,
135 INT_1610_DMA_CH8
, INT_1610_DMA_CH9
, INT_1610_DMA_CH10
,
136 INT_1610_DMA_CH11
, INT_1610_DMA_CH12
, INT_1610_DMA_CH13
,
137 INT_1610_DMA_CH14
, INT_1610_DMA_CH15
, INT_DMA_LCD
140 static inline void disable_lnk(int lch
);
141 static void omap_disable_channel_irq(int lch
);
142 static inline void omap_enable_channel_irq(int lch
);
144 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
147 #define dma_read(reg) \
150 if (cpu_class_is_omap1()) \
151 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
153 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 #define dma_write(val, reg) \
159 if (cpu_class_is_omap1()) \
160 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
162 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
165 #ifdef CONFIG_ARCH_OMAP15XX
166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
167 int omap_dma_in_1510_mode(void)
169 return enable_1510_mode
;
172 #define omap_dma_in_1510_mode() 0
175 #ifdef CONFIG_ARCH_OMAP1
176 static inline int get_gdma_dev(int req
)
178 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
179 int shift
= ((req
- 1) % 5) * 6;
181 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
184 static inline void set_gdma_dev(int req
, int dev
)
186 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
187 int shift
= ((req
- 1) % 5) * 6;
191 l
&= ~(0x3f << shift
);
192 l
|= (dev
- 1) << shift
;
196 #define set_gdma_dev(req, dev) do {} while (0)
200 static void clear_lch_regs(int lch
)
203 void __iomem
*lch_base
= omap_dma_base
+ OMAP1_DMA_CH_BASE(lch
);
205 for (i
= 0; i
< 0x2c; i
+= 2)
206 __raw_writew(0, lch_base
+ i
);
209 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
214 if (cpu_class_is_omap1()) {
216 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
217 reg
= OMAP_TC_OCPT1_PRIOR
;
219 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
220 reg
= OMAP_TC_OCPT2_PRIOR
;
222 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
223 reg
= OMAP_TC_EMIFF_PRIOR
;
225 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
226 reg
= OMAP_TC_EMIFS_PRIOR
;
234 l
|= (priority
& 0xf) << 8;
238 if (cpu_class_is_omap2()) {
241 ccr
= dma_read(CCR(lch
));
246 dma_write(ccr
, CCR(lch
));
249 EXPORT_SYMBOL(omap_set_dma_priority
);
251 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
252 int frame_count
, int sync_mode
,
253 int dma_trigger
, int src_or_dst_synch
)
257 l
= dma_read(CSDP(lch
));
260 dma_write(l
, CSDP(lch
));
262 if (cpu_class_is_omap1()) {
265 ccr
= dma_read(CCR(lch
));
267 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
269 dma_write(ccr
, CCR(lch
));
271 ccr
= dma_read(CCR2(lch
));
273 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
275 dma_write(ccr
, CCR2(lch
));
278 if (cpu_class_is_omap2() && dma_trigger
) {
281 val
= dma_read(CCR(lch
));
283 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
284 val
&= ~((3 << 19) | 0x1f);
285 val
|= (dma_trigger
& ~0x1f) << 14;
286 val
|= dma_trigger
& 0x1f;
288 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
293 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
298 if (src_or_dst_synch
)
299 val
|= 1 << 24; /* source synch */
301 val
&= ~(1 << 24); /* dest synch */
303 dma_write(val
, CCR(lch
));
306 dma_write(elem_count
, CEN(lch
));
307 dma_write(frame_count
, CFN(lch
));
309 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
311 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
315 BUG_ON(omap_dma_in_1510_mode());
317 if (cpu_class_is_omap2()) {
322 w
= dma_read(CCR2(lch
));
326 case OMAP_DMA_CONSTANT_FILL
:
329 case OMAP_DMA_TRANSPARENT_COPY
:
332 case OMAP_DMA_COLOR_DIS
:
337 dma_write(w
, CCR2(lch
));
339 w
= dma_read(LCH_CTRL(lch
));
341 /* Default is channel type 2D */
343 dma_write((u16
)color
, COLOR_L(lch
));
344 dma_write((u16
)(color
>> 16), COLOR_U(lch
));
345 w
|= 1; /* Channel type G */
347 dma_write(w
, LCH_CTRL(lch
));
349 EXPORT_SYMBOL(omap_set_dma_color_mode
);
351 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
353 if (cpu_class_is_omap2()) {
356 csdp
= dma_read(CSDP(lch
));
357 csdp
&= ~(0x3 << 16);
358 csdp
|= (mode
<< 16);
359 dma_write(csdp
, CSDP(lch
));
362 EXPORT_SYMBOL(omap_set_dma_write_mode
);
364 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
366 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 l
= dma_read(LCH_CTRL(lch
));
372 dma_write(l
, LCH_CTRL(lch
));
375 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
377 /* Note that src_port is only for omap1 */
378 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
379 unsigned long src_start
,
380 int src_ei
, int src_fi
)
384 if (cpu_class_is_omap1()) {
387 w
= dma_read(CSDP(lch
));
390 dma_write(w
, CSDP(lch
));
393 l
= dma_read(CCR(lch
));
395 l
|= src_amode
<< 12;
396 dma_write(l
, CCR(lch
));
398 if (cpu_class_is_omap1()) {
399 dma_write(src_start
>> 16, CSSA_U(lch
));
400 dma_write((u16
)src_start
, CSSA_L(lch
));
403 if (cpu_class_is_omap2())
404 dma_write(src_start
, CSSA(lch
));
406 dma_write(src_ei
, CSEI(lch
));
407 dma_write(src_fi
, CSFI(lch
));
409 EXPORT_SYMBOL(omap_set_dma_src_params
);
411 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
413 omap_set_dma_transfer_params(lch
, params
->data_type
,
414 params
->elem_count
, params
->frame_count
,
415 params
->sync_mode
, params
->trigger
,
416 params
->src_or_dst_synch
);
417 omap_set_dma_src_params(lch
, params
->src_port
,
418 params
->src_amode
, params
->src_start
,
419 params
->src_ei
, params
->src_fi
);
421 omap_set_dma_dest_params(lch
, params
->dst_port
,
422 params
->dst_amode
, params
->dst_start
,
423 params
->dst_ei
, params
->dst_fi
);
424 if (params
->read_prio
|| params
->write_prio
)
425 omap_dma_set_prio_lch(lch
, params
->read_prio
,
428 EXPORT_SYMBOL(omap_set_dma_params
);
430 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
432 if (cpu_class_is_omap2())
435 dma_write(eidx
, CSEI(lch
));
436 dma_write(fidx
, CSFI(lch
));
438 EXPORT_SYMBOL(omap_set_dma_src_index
);
440 void omap_set_dma_src_data_pack(int lch
, int enable
)
444 l
= dma_read(CSDP(lch
));
448 dma_write(l
, CSDP(lch
));
450 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
452 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
454 unsigned int burst
= 0;
457 l
= dma_read(CSDP(lch
));
460 switch (burst_mode
) {
461 case OMAP_DMA_DATA_BURST_DIS
:
463 case OMAP_DMA_DATA_BURST_4
:
464 if (cpu_class_is_omap2())
469 case OMAP_DMA_DATA_BURST_8
:
470 if (cpu_class_is_omap2()) {
474 /* not supported by current hardware on OMAP1
478 case OMAP_DMA_DATA_BURST_16
:
479 if (cpu_class_is_omap2()) {
483 /* OMAP1 don't support burst 16
491 dma_write(l
, CSDP(lch
));
493 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
495 /* Note that dest_port is only for OMAP1 */
496 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
497 unsigned long dest_start
,
498 int dst_ei
, int dst_fi
)
502 if (cpu_class_is_omap1()) {
503 l
= dma_read(CSDP(lch
));
506 dma_write(l
, CSDP(lch
));
509 l
= dma_read(CCR(lch
));
511 l
|= dest_amode
<< 14;
512 dma_write(l
, CCR(lch
));
514 if (cpu_class_is_omap1()) {
515 dma_write(dest_start
>> 16, CDSA_U(lch
));
516 dma_write(dest_start
, CDSA_L(lch
));
519 if (cpu_class_is_omap2())
520 dma_write(dest_start
, CDSA(lch
));
522 dma_write(dst_ei
, CDEI(lch
));
523 dma_write(dst_fi
, CDFI(lch
));
525 EXPORT_SYMBOL(omap_set_dma_dest_params
);
527 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
529 if (cpu_class_is_omap2())
532 dma_write(eidx
, CDEI(lch
));
533 dma_write(fidx
, CDFI(lch
));
535 EXPORT_SYMBOL(omap_set_dma_dest_index
);
537 void omap_set_dma_dest_data_pack(int lch
, int enable
)
541 l
= dma_read(CSDP(lch
));
545 dma_write(l
, CSDP(lch
));
547 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
549 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
551 unsigned int burst
= 0;
554 l
= dma_read(CSDP(lch
));
557 switch (burst_mode
) {
558 case OMAP_DMA_DATA_BURST_DIS
:
560 case OMAP_DMA_DATA_BURST_4
:
561 if (cpu_class_is_omap2())
566 case OMAP_DMA_DATA_BURST_8
:
567 if (cpu_class_is_omap2())
572 case OMAP_DMA_DATA_BURST_16
:
573 if (cpu_class_is_omap2()) {
577 /* OMAP1 don't support burst 16
581 printk(KERN_ERR
"Invalid DMA burst mode\n");
586 dma_write(l
, CSDP(lch
));
588 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
590 static inline void omap_enable_channel_irq(int lch
)
595 if (cpu_class_is_omap1())
596 status
= dma_read(CSR(lch
));
597 else if (cpu_class_is_omap2())
598 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(lch
));
600 /* Enable some nice interrupts. */
601 dma_write(dma_chan
[lch
].enabled_irqs
, CICR(lch
));
604 static void omap_disable_channel_irq(int lch
)
606 if (cpu_class_is_omap2())
607 dma_write(0, CICR(lch
));
610 void omap_enable_dma_irq(int lch
, u16 bits
)
612 dma_chan
[lch
].enabled_irqs
|= bits
;
614 EXPORT_SYMBOL(omap_enable_dma_irq
);
616 void omap_disable_dma_irq(int lch
, u16 bits
)
618 dma_chan
[lch
].enabled_irqs
&= ~bits
;
620 EXPORT_SYMBOL(omap_disable_dma_irq
);
622 static inline void enable_lnk(int lch
)
626 l
= dma_read(CLNK_CTRL(lch
));
628 if (cpu_class_is_omap1())
631 /* Set the ENABLE_LNK bits */
632 if (dma_chan
[lch
].next_lch
!= -1)
633 l
= dma_chan
[lch
].next_lch
| (1 << 15);
635 #ifndef CONFIG_ARCH_OMAP1
636 if (cpu_class_is_omap2())
637 if (dma_chan
[lch
].next_linked_ch
!= -1)
638 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
641 dma_write(l
, CLNK_CTRL(lch
));
644 static inline void disable_lnk(int lch
)
648 l
= dma_read(CLNK_CTRL(lch
));
650 /* Disable interrupts */
651 if (cpu_class_is_omap1()) {
652 dma_write(0, CICR(lch
));
653 /* Set the STOP_LNK bit */
657 if (cpu_class_is_omap2()) {
658 omap_disable_channel_irq(lch
);
659 /* Clear the ENABLE_LNK bit */
663 dma_write(l
, CLNK_CTRL(lch
));
664 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
667 static inline void omap2_enable_irq_lch(int lch
)
671 if (!cpu_class_is_omap2())
674 val
= dma_read(IRQENABLE_L0
);
676 dma_write(val
, IRQENABLE_L0
);
679 int omap_request_dma(int dev_id
, const char *dev_name
,
680 void (*callback
)(int lch
, u16 ch_status
, void *data
),
681 void *data
, int *dma_ch_out
)
683 int ch
, free_ch
= -1;
685 struct omap_dma_lch
*chan
;
687 spin_lock_irqsave(&dma_chan_lock
, flags
);
688 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
689 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
696 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
699 chan
= dma_chan
+ free_ch
;
700 chan
->dev_id
= dev_id
;
702 if (cpu_class_is_omap1())
703 clear_lch_regs(free_ch
);
705 if (cpu_class_is_omap2())
706 omap_clear_dma(free_ch
);
708 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
710 chan
->dev_name
= dev_name
;
711 chan
->callback
= callback
;
715 #ifndef CONFIG_ARCH_OMAP1
716 if (cpu_class_is_omap2()) {
718 chan
->next_linked_ch
= -1;
722 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
724 if (cpu_class_is_omap1())
725 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
726 else if (cpu_class_is_omap2())
727 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
728 OMAP2_DMA_TRANS_ERR_IRQ
;
730 if (cpu_is_omap16xx()) {
731 /* If the sync device is set, configure it dynamically. */
733 set_gdma_dev(free_ch
+ 1, dev_id
);
734 dev_id
= free_ch
+ 1;
737 * Disable the 1510 compatibility mode and set the sync device
740 dma_write(dev_id
| (1 << 10), CCR(free_ch
));
741 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
742 dma_write(dev_id
, CCR(free_ch
));
745 if (cpu_class_is_omap2()) {
746 omap2_enable_irq_lch(free_ch
);
747 omap_enable_channel_irq(free_ch
);
748 /* Clear the CSR register and IRQ status register */
749 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(free_ch
));
750 dma_write(1 << free_ch
, IRQSTATUS_L0
);
753 *dma_ch_out
= free_ch
;
757 EXPORT_SYMBOL(omap_request_dma
);
759 void omap_free_dma(int lch
)
763 if (dma_chan
[lch
].dev_id
== -1) {
764 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
769 if (cpu_class_is_omap1()) {
770 /* Disable all DMA interrupts for the channel. */
771 dma_write(0, CICR(lch
));
772 /* Make sure the DMA transfer is stopped. */
773 dma_write(0, CCR(lch
));
776 if (cpu_class_is_omap2()) {
778 /* Disable interrupts */
779 val
= dma_read(IRQENABLE_L0
);
781 dma_write(val
, IRQENABLE_L0
);
783 /* Clear the CSR register and IRQ status register */
784 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(lch
));
785 dma_write(1 << lch
, IRQSTATUS_L0
);
787 /* Disable all DMA interrupts for the channel. */
788 dma_write(0, CICR(lch
));
790 /* Make sure the DMA transfer is stopped. */
791 dma_write(0, CCR(lch
));
795 spin_lock_irqsave(&dma_chan_lock
, flags
);
796 dma_chan
[lch
].dev_id
= -1;
797 dma_chan
[lch
].next_lch
= -1;
798 dma_chan
[lch
].callback
= NULL
;
799 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
801 EXPORT_SYMBOL(omap_free_dma
);
804 * @brief omap_dma_set_global_params : Set global priority settings for dma
807 * @param max_fifo_depth
808 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
809 * DMA_THREAD_RESERVE_ONET
810 * DMA_THREAD_RESERVE_TWOT
811 * DMA_THREAD_RESERVE_THREET
814 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
818 if (!cpu_class_is_omap2()) {
819 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
826 reg
= (arb_rate
& 0xff) << 16;
827 reg
|= (0xff & max_fifo_depth
);
831 EXPORT_SYMBOL(omap_dma_set_global_params
);
834 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
837 * @param read_prio - Read priority
838 * @param write_prio - Write priority
839 * Both of the above can be set with one of the following values :
840 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
843 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
844 unsigned char write_prio
)
848 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
849 printk(KERN_ERR
"Invalid channel id\n");
852 l
= dma_read(CCR(lch
));
853 l
&= ~((1 << 6) | (1 << 26));
854 if (cpu_is_omap2430() || cpu_is_omap34xx())
855 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
857 l
|= ((read_prio
& 0x1) << 6);
859 dma_write(l
, CCR(lch
));
863 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
866 * Clears any DMA state so the DMA engine is ready to restart with new buffers
867 * through omap_start_dma(). Any buffers in flight are discarded.
869 void omap_clear_dma(int lch
)
873 local_irq_save(flags
);
875 if (cpu_class_is_omap1()) {
878 l
= dma_read(CCR(lch
));
879 l
&= ~OMAP_DMA_CCR_EN
;
880 dma_write(l
, CCR(lch
));
882 /* Clear pending interrupts */
883 l
= dma_read(CSR(lch
));
886 if (cpu_class_is_omap2()) {
888 void __iomem
*lch_base
= omap_dma_base
+ OMAP_DMA4_CH_BASE(lch
);
889 for (i
= 0; i
< 0x44; i
+= 4)
890 __raw_writel(0, lch_base
+ i
);
893 local_irq_restore(flags
);
895 EXPORT_SYMBOL(omap_clear_dma
);
897 void omap_start_dma(int lch
)
901 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
902 int next_lch
, cur_lch
;
903 char dma_chan_link_map
[OMAP_DMA4_LOGICAL_DMA_CH_COUNT
];
905 dma_chan_link_map
[lch
] = 1;
906 /* Set the link register of the first channel */
909 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
910 cur_lch
= dma_chan
[lch
].next_lch
;
912 next_lch
= dma_chan
[cur_lch
].next_lch
;
914 /* The loop case: we've been here already */
915 if (dma_chan_link_map
[cur_lch
])
917 /* Mark the current channel */
918 dma_chan_link_map
[cur_lch
] = 1;
921 omap_enable_channel_irq(cur_lch
);
924 } while (next_lch
!= -1);
925 } else if (cpu_class_is_omap2()) {
926 /* Errata: Need to write lch even if not using chaining */
927 dma_write(lch
, CLNK_CTRL(lch
));
930 omap_enable_channel_irq(lch
);
932 l
= dma_read(CCR(lch
));
935 * Errata: On ES2.0 BUFFERING disable must be set.
936 * This will always fail on ES1.0
938 if (cpu_is_omap24xx())
939 l
|= OMAP_DMA_CCR_EN
;
941 l
|= OMAP_DMA_CCR_EN
;
942 dma_write(l
, CCR(lch
));
944 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
946 EXPORT_SYMBOL(omap_start_dma
);
948 void omap_stop_dma(int lch
)
952 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
953 int next_lch
, cur_lch
= lch
;
954 char dma_chan_link_map
[OMAP_DMA4_LOGICAL_DMA_CH_COUNT
];
956 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
958 /* The loop case: we've been here already */
959 if (dma_chan_link_map
[cur_lch
])
961 /* Mark the current channel */
962 dma_chan_link_map
[cur_lch
] = 1;
964 disable_lnk(cur_lch
);
966 next_lch
= dma_chan
[cur_lch
].next_lch
;
968 } while (next_lch
!= -1);
973 /* Disable all interrupts on the channel */
974 if (cpu_class_is_omap1())
975 dma_write(0, CICR(lch
));
977 l
= dma_read(CCR(lch
));
978 l
&= ~OMAP_DMA_CCR_EN
;
979 dma_write(l
, CCR(lch
));
981 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
983 EXPORT_SYMBOL(omap_stop_dma
);
986 * Allows changing the DMA callback function or data. This may be needed if
987 * the driver shares a single DMA channel for multiple dma triggers.
989 int omap_set_dma_callback(int lch
,
990 void (*callback
)(int lch
, u16 ch_status
, void *data
),
998 spin_lock_irqsave(&dma_chan_lock
, flags
);
999 if (dma_chan
[lch
].dev_id
== -1) {
1000 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1001 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1004 dma_chan
[lch
].callback
= callback
;
1005 dma_chan
[lch
].data
= data
;
1006 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1010 EXPORT_SYMBOL(omap_set_dma_callback
);
1013 * Returns current physical source address for the given DMA channel.
1014 * If the channel is running the caller must disable interrupts prior calling
1015 * this function and process the returned value before re-enabling interrupt to
1016 * prevent races with the interrupt handler. Note that in continuous mode there
1017 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1018 * in incorrect return value.
1020 dma_addr_t
omap_get_dma_src_pos(int lch
)
1022 dma_addr_t offset
= 0;
1024 if (cpu_is_omap15xx())
1025 offset
= dma_read(CPC(lch
));
1027 offset
= dma_read(CSAC(lch
));
1030 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1031 * read before the DMA controller finished disabling the channel.
1033 if (!cpu_is_omap15xx() && offset
== 0)
1034 offset
= dma_read(CSAC(lch
));
1036 if (cpu_class_is_omap1())
1037 offset
|= (dma_read(CSSA_U(lch
)) << 16);
1041 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1044 * Returns current physical destination address for the given DMA channel.
1045 * If the channel is running the caller must disable interrupts prior calling
1046 * this function and process the returned value before re-enabling interrupt to
1047 * prevent races with the interrupt handler. Note that in continuous mode there
1048 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1049 * in incorrect return value.
1051 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1053 dma_addr_t offset
= 0;
1055 if (cpu_is_omap15xx())
1056 offset
= dma_read(CPC(lch
));
1058 offset
= dma_read(CDAC(lch
));
1061 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1062 * read before the DMA controller finished disabling the channel.
1064 if (!cpu_is_omap15xx() && offset
== 0)
1065 offset
= dma_read(CDAC(lch
));
1067 if (cpu_class_is_omap1())
1068 offset
|= (dma_read(CDSA_U(lch
)) << 16);
1072 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1074 int omap_get_dma_active_status(int lch
)
1076 return (dma_read(CCR(lch
)) & OMAP_DMA_CCR_EN
) != 0;
1078 EXPORT_SYMBOL(omap_get_dma_active_status
);
1080 int omap_dma_running(void)
1084 /* Check if LCD DMA is running */
1085 if (cpu_is_omap16xx())
1086 if (omap_readw(OMAP1610_DMA_LCD_CCR
) & OMAP_DMA_CCR_EN
)
1089 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1090 if (dma_read(CCR(lch
)) & OMAP_DMA_CCR_EN
)
1097 * lch_queue DMA will start right after lch_head one is finished.
1098 * For this DMA link to start, you still need to start (see omap_start_dma)
1099 * the first one. That will fire up the entire queue.
1101 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1103 if (omap_dma_in_1510_mode()) {
1104 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1109 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1110 (dma_chan
[lch_queue
].dev_id
== -1)) {
1111 printk(KERN_ERR
"omap_dma: trying to link "
1112 "non requested channels\n");
1116 dma_chan
[lch_head
].next_lch
= lch_queue
;
1118 EXPORT_SYMBOL(omap_dma_link_lch
);
1121 * Once the DMA queue is stopped, we can destroy it.
1123 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1125 if (omap_dma_in_1510_mode()) {
1126 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1131 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1132 dma_chan
[lch_head
].next_lch
== -1) {
1133 printk(KERN_ERR
"omap_dma: trying to unlink "
1134 "non linked channels\n");
1138 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1139 (dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
)) {
1140 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
1141 "before unlinking\n");
1145 dma_chan
[lch_head
].next_lch
= -1;
1147 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1149 /*----------------------------------------------------------------------------*/
1151 #ifndef CONFIG_ARCH_OMAP1
1152 /* Create chain of DMA channesls */
1153 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1157 /* Check if this is the first link in chain */
1158 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1159 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1160 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1161 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1162 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1165 /* a link exists, link the new channel in circular chain */
1167 dma_chan
[lch_queue
].next_linked_ch
=
1168 dma_chan
[lch_head
].next_linked_ch
;
1169 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1170 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1171 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1175 l
= dma_read(CLNK_CTRL(lch_head
));
1178 dma_write(l
, CLNK_CTRL(lch_head
));
1180 l
= dma_read(CLNK_CTRL(lch_queue
));
1182 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1183 dma_write(l
, CLNK_CTRL(lch_queue
));
1187 * @brief omap_request_dma_chain : Request a chain of DMA channels
1189 * @param dev_id - Device id using the dma channel
1190 * @param dev_name - Device name
1191 * @param callback - Call back function
1193 * @no_of_chans - Number of channels requested
1194 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1195 * OMAP_DMA_DYNAMIC_CHAIN
1196 * @params - Channel parameters
1198 * @return - Succes : 0
1199 * Failure: -EINVAL/-ENOMEM
1201 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1202 void (*callback
) (int chain_id
, u16 ch_status
,
1204 int *chain_id
, int no_of_chans
, int chain_mode
,
1205 struct omap_dma_channel_params params
)
1210 /* Is the chain mode valid ? */
1211 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1212 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1213 printk(KERN_ERR
"Invalid chain mode requested\n");
1217 if (unlikely((no_of_chans
< 1
1218 || no_of_chans
> dma_lch_count
))) {
1219 printk(KERN_ERR
"Invalid Number of channels requested\n");
1223 /* Allocate a queue to maintain the status of the channels
1225 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1226 if (channels
== NULL
) {
1227 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1231 /* request and reserve DMA channels for the chain */
1232 for (i
= 0; i
< no_of_chans
; i
++) {
1233 err
= omap_request_dma(dev_id
, dev_name
,
1234 callback
, NULL
, &channels
[i
]);
1237 for (j
= 0; j
< i
; j
++)
1238 omap_free_dma(channels
[j
]);
1240 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1243 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1244 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1247 * Allowing client drivers to set common parameters now,
1248 * so that later only relevant (src_start, dest_start
1249 * and element count) can be set
1251 omap_set_dma_params(channels
[i
], ¶ms
);
1254 *chain_id
= channels
[0];
1255 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1256 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1257 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1258 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1260 for (i
= 0; i
< no_of_chans
; i
++)
1261 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1263 /* Reset the Queue pointers */
1264 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1266 /* Set up the chain */
1267 if (no_of_chans
== 1)
1268 create_dma_lch_chain(channels
[0], channels
[0]);
1270 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1271 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1276 EXPORT_SYMBOL(omap_request_dma_chain
);
1279 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1280 * params after setting it. Dont do this while dma is running!!
1282 * @param chain_id - Chained logical channel id.
1285 * @return - Success : 0
1288 int omap_modify_dma_chain_params(int chain_id
,
1289 struct omap_dma_channel_params params
)
1294 /* Check for input params */
1295 if (unlikely((chain_id
< 0
1296 || chain_id
>= dma_lch_count
))) {
1297 printk(KERN_ERR
"Invalid chain id\n");
1301 /* Check if the chain exists */
1302 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1303 printk(KERN_ERR
"Chain doesn't exists\n");
1306 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1308 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1310 * Allowing client drivers to set common parameters now,
1311 * so that later only relevant (src_start, dest_start
1312 * and element count) can be set
1314 omap_set_dma_params(channels
[i
], ¶ms
);
1319 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1322 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1326 * @return - Success : 0
1329 int omap_free_dma_chain(int chain_id
)
1334 /* Check for input params */
1335 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1336 printk(KERN_ERR
"Invalid chain id\n");
1340 /* Check if the chain exists */
1341 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1342 printk(KERN_ERR
"Chain doesn't exists\n");
1346 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1347 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1348 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1349 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1350 dma_chan
[channels
[i
]].chain_id
= -1;
1351 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1352 omap_free_dma(channels
[i
]);
1357 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1358 dma_linked_lch
[chain_id
].chain_mode
= -1;
1359 dma_linked_lch
[chain_id
].chain_state
= -1;
1363 EXPORT_SYMBOL(omap_free_dma_chain
);
1366 * @brief omap_dma_chain_status - Check if the chain is in
1367 * active / inactive state.
1370 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1373 int omap_dma_chain_status(int chain_id
)
1375 /* Check for input params */
1376 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1377 printk(KERN_ERR
"Invalid chain id\n");
1381 /* Check if the chain exists */
1382 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1383 printk(KERN_ERR
"Chain doesn't exists\n");
1386 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1387 dma_linked_lch
[chain_id
].q_count
);
1389 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1390 return OMAP_DMA_CHAIN_INACTIVE
;
1392 return OMAP_DMA_CHAIN_ACTIVE
;
1394 EXPORT_SYMBOL(omap_dma_chain_status
);
1397 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1398 * set the params and start the transfer.
1401 * @param src_start - buffer start address
1402 * @param dest_start - Dest address
1404 * @param frame_count
1405 * @param callbk_data - channel callback parameter data.
1407 * @return - Success : 0
1408 * Failure: -EINVAL/-EBUSY
1410 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1411 int elem_count
, int frame_count
, void *callbk_data
)
1418 * if buffer size is less than 1 then there is
1419 * no use of starting the chain
1421 if (elem_count
< 1) {
1422 printk(KERN_ERR
"Invalid buffer size\n");
1426 /* Check for input params */
1427 if (unlikely((chain_id
< 0
1428 || chain_id
>= dma_lch_count
))) {
1429 printk(KERN_ERR
"Invalid chain id\n");
1433 /* Check if the chain exists */
1434 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1435 printk(KERN_ERR
"Chain doesn't exist\n");
1439 /* Check if all the channels in chain are in use */
1440 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1443 /* Frame count may be negative in case of indexed transfers */
1444 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1446 /* Get a free channel */
1447 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1449 /* Store the callback data */
1450 dma_chan
[lch
].data
= callbk_data
;
1452 /* Increment the q_tail */
1453 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1455 /* Set the params to the free channel */
1457 dma_write(src_start
, CSSA(lch
));
1458 if (dest_start
!= 0)
1459 dma_write(dest_start
, CDSA(lch
));
1461 /* Write the buffer size */
1462 dma_write(elem_count
, CEN(lch
));
1463 dma_write(frame_count
, CFN(lch
));
1466 * If the chain is dynamically linked,
1467 * then we may have to start the chain if its not active
1469 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1472 * In Dynamic chain, if the chain is not started,
1475 if (dma_linked_lch
[chain_id
].chain_state
==
1476 DMA_CHAIN_NOTSTARTED
) {
1477 /* Enable the link in previous channel */
1478 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1480 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1481 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1485 * Chain is already started, make sure its active,
1486 * if not then start the chain
1491 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1493 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1494 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1496 if (0 == ((1 << 7) & dma_read(
1497 CCR(dma_chan
[lch
].prev_linked_ch
)))) {
1498 disable_lnk(dma_chan
[lch
].
1500 pr_debug("\n prev ch is stopped\n");
1505 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1507 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1508 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1511 omap_enable_channel_irq(lch
);
1513 l
= dma_read(CCR(lch
));
1515 if ((0 == (l
& (1 << 24))))
1519 if (start_dma
== 1) {
1520 if (0 == (l
& (1 << 7))) {
1522 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1523 pr_debug("starting %d\n", lch
);
1524 dma_write(l
, CCR(lch
));
1528 if (0 == (l
& (1 << 7)))
1529 dma_write(l
, CCR(lch
));
1531 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1537 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1540 * @brief omap_start_dma_chain_transfers - Start the chain
1544 * @return - Success : 0
1545 * Failure : -EINVAL/-EBUSY
1547 int omap_start_dma_chain_transfers(int chain_id
)
1552 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1553 printk(KERN_ERR
"Invalid chain id\n");
1557 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1559 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1560 printk(KERN_ERR
"Chain is already started\n");
1564 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1565 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1567 enable_lnk(channels
[i
]);
1568 omap_enable_channel_irq(channels
[i
]);
1571 omap_enable_channel_irq(channels
[0]);
1574 l
= dma_read(CCR(channels
[0]));
1576 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1577 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1579 if ((0 == (l
& (1 << 24))))
1583 dma_write(l
, CCR(channels
[0]));
1585 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1589 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1592 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1596 * @return - Success : 0
1599 int omap_stop_dma_chain_transfers(int chain_id
)
1605 /* Check for input params */
1606 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1607 printk(KERN_ERR
"Invalid chain id\n");
1611 /* Check if the chain exists */
1612 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1613 printk(KERN_ERR
"Chain doesn't exists\n");
1616 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1620 * Special programming model needed to disable DMA before end of block
1622 sys_cf
= dma_read(OCP_SYSCONFIG
);
1624 /* Middle mode reg set no Standby */
1625 l
&= ~((1 << 12)|(1 << 13));
1626 dma_write(l
, OCP_SYSCONFIG
);
1628 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1630 /* Stop the Channel transmission */
1631 l
= dma_read(CCR(channels
[i
]));
1633 dma_write(l
, CCR(channels
[i
]));
1635 /* Disable the link in all the channels */
1636 disable_lnk(channels
[i
]);
1637 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1640 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1642 /* Reset the Queue pointers */
1643 OMAP_DMA_CHAIN_QINIT(chain_id
);
1645 /* Errata - put in the old value */
1646 dma_write(sys_cf
, OCP_SYSCONFIG
);
1650 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1652 /* Get the index of the ongoing DMA in chain */
1654 * @brief omap_get_dma_chain_index - Get the element and frame index
1655 * of the ongoing DMA in chain
1658 * @param ei - Element index
1659 * @param fi - Frame index
1661 * @return - Success : 0
1664 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1669 /* Check for input params */
1670 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1671 printk(KERN_ERR
"Invalid chain id\n");
1675 /* Check if the chain exists */
1676 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1677 printk(KERN_ERR
"Chain doesn't exists\n");
1683 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1685 /* Get the current channel */
1686 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1688 *ei
= dma_read(CCEN(lch
));
1689 *fi
= dma_read(CCFN(lch
));
1693 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1696 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1697 * ongoing DMA in chain
1701 * @return - Success : Destination position
1704 int omap_get_dma_chain_dst_pos(int chain_id
)
1709 /* Check for input params */
1710 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1711 printk(KERN_ERR
"Invalid chain id\n");
1715 /* Check if the chain exists */
1716 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1717 printk(KERN_ERR
"Chain doesn't exists\n");
1721 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1723 /* Get the current channel */
1724 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1726 return dma_read(CDAC(lch
));
1728 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1731 * @brief omap_get_dma_chain_src_pos - Get the source position
1732 * of the ongoing DMA in chain
1735 * @return - Success : Destination position
1738 int omap_get_dma_chain_src_pos(int chain_id
)
1743 /* Check for input params */
1744 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1745 printk(KERN_ERR
"Invalid chain id\n");
1749 /* Check if the chain exists */
1750 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1751 printk(KERN_ERR
"Chain doesn't exists\n");
1755 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1757 /* Get the current channel */
1758 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1760 return dma_read(CSAC(lch
));
1762 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1763 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1765 /*----------------------------------------------------------------------------*/
1767 #ifdef CONFIG_ARCH_OMAP1
1769 static int omap1_dma_handle_ch(int ch
)
1773 if (enable_1510_mode
&& ch
>= 6) {
1774 csr
= dma_chan
[ch
].saved_csr
;
1775 dma_chan
[ch
].saved_csr
= 0;
1777 csr
= dma_read(CSR(ch
));
1778 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1779 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1782 if ((csr
& 0x3f) == 0)
1784 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1785 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
1786 "%d (CSR %04x)\n", ch
, csr
);
1789 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1790 printk(KERN_WARNING
"DMA timeout with device %d\n",
1791 dma_chan
[ch
].dev_id
);
1792 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1793 printk(KERN_WARNING
"DMA synchronization event drop occurred "
1794 "with device %d\n", dma_chan
[ch
].dev_id
);
1795 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1796 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1797 if (likely(dma_chan
[ch
].callback
!= NULL
))
1798 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1803 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1805 int ch
= ((int) dev_id
) - 1;
1809 int handled_now
= 0;
1811 handled_now
+= omap1_dma_handle_ch(ch
);
1812 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1813 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1816 handled
+= handled_now
;
1819 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1823 #define omap1_dma_irq_handler NULL
1826 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1828 static int omap2_dma_handle_ch(int ch
)
1830 u32 status
= dma_read(CSR(ch
));
1833 if (printk_ratelimit())
1834 printk(KERN_WARNING
"Spurious DMA IRQ for lch %d\n",
1836 dma_write(1 << ch
, IRQSTATUS_L0
);
1839 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1840 if (printk_ratelimit())
1841 printk(KERN_WARNING
"IRQ %04x for non-allocated DMA"
1842 "channel %d\n", status
, ch
);
1845 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1847 "DMA synchronization event drop occurred with device "
1848 "%d\n", dma_chan
[ch
].dev_id
);
1849 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
)) {
1850 printk(KERN_INFO
"DMA transaction error with device %d\n",
1851 dma_chan
[ch
].dev_id
);
1852 if (cpu_class_is_omap2()) {
1853 /* Errata: sDMA Channel is not disabled
1854 * after a transaction error. So we explicitely
1855 * disable the channel
1859 ccr
= dma_read(CCR(ch
));
1860 ccr
&= ~OMAP_DMA_CCR_EN
;
1861 dma_write(ccr
, CCR(ch
));
1862 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1865 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1866 printk(KERN_INFO
"DMA secure error with device %d\n",
1867 dma_chan
[ch
].dev_id
);
1868 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1869 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1870 dma_chan
[ch
].dev_id
);
1872 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(ch
));
1873 dma_write(1 << ch
, IRQSTATUS_L0
);
1875 /* If the ch is not chained then chain_id will be -1 */
1876 if (dma_chan
[ch
].chain_id
!= -1) {
1877 int chain_id
= dma_chan
[ch
].chain_id
;
1878 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1879 if (dma_read(CLNK_CTRL(ch
)) & (1 << 15))
1880 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1882 if (dma_linked_lch
[chain_id
].chain_mode
==
1883 OMAP_DMA_DYNAMIC_CHAIN
)
1886 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1887 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1889 status
= dma_read(CSR(ch
));
1892 dma_write(status
, CSR(ch
));
1894 if (likely(dma_chan
[ch
].callback
!= NULL
))
1895 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1900 /* STATUS register count is from 1-32 while our is 0-31 */
1901 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1903 u32 val
, enable_reg
;
1906 val
= dma_read(IRQSTATUS_L0
);
1908 if (printk_ratelimit())
1909 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1912 enable_reg
= dma_read(IRQENABLE_L0
);
1913 val
&= enable_reg
; /* Dispatch only relevant interrupts */
1914 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1916 omap2_dma_handle_ch(i
);
1923 static struct irqaction omap24xx_dma_irq
= {
1925 .handler
= omap2_dma_irq_handler
,
1926 .flags
= IRQF_DISABLED
1930 static struct irqaction omap24xx_dma_irq
;
1933 /*----------------------------------------------------------------------------*/
1935 static struct lcd_dma_info
{
1938 void (*callback
)(u16 status
, void *data
);
1942 unsigned long addr
, size
;
1943 int rotate
, data_type
, xres
, yres
;
1949 int single_transfer
;
1952 void omap_set_lcd_dma_b1(unsigned long addr
, u16 fb_xres
, u16 fb_yres
,
1955 lcd_dma
.addr
= addr
;
1956 lcd_dma
.data_type
= data_type
;
1957 lcd_dma
.xres
= fb_xres
;
1958 lcd_dma
.yres
= fb_yres
;
1960 EXPORT_SYMBOL(omap_set_lcd_dma_b1
);
1962 void omap_set_lcd_dma_src_port(int port
)
1964 lcd_dma
.src_port
= port
;
1967 void omap_set_lcd_dma_ext_controller(int external
)
1969 lcd_dma
.ext_ctrl
= external
;
1971 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller
);
1973 void omap_set_lcd_dma_single_transfer(int single
)
1975 lcd_dma
.single_transfer
= single
;
1977 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer
);
1979 void omap_set_lcd_dma_b1_rotation(int rotate
)
1981 if (omap_dma_in_1510_mode()) {
1982 printk(KERN_ERR
"DMA rotation is not supported in 1510 mode\n");
1986 lcd_dma
.rotate
= rotate
;
1988 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation
);
1990 void omap_set_lcd_dma_b1_mirror(int mirror
)
1992 if (omap_dma_in_1510_mode()) {
1993 printk(KERN_ERR
"DMA mirror is not supported in 1510 mode\n");
1996 lcd_dma
.mirror
= mirror
;
1998 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror
);
2000 void omap_set_lcd_dma_b1_vxres(unsigned long vxres
)
2002 if (omap_dma_in_1510_mode()) {
2003 printk(KERN_ERR
"DMA virtual resulotion is not supported "
2007 lcd_dma
.vxres
= vxres
;
2009 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres
);
2011 void omap_set_lcd_dma_b1_scale(unsigned int xscale
, unsigned int yscale
)
2013 if (omap_dma_in_1510_mode()) {
2014 printk(KERN_ERR
"DMA scale is not supported in 1510 mode\n");
2017 lcd_dma
.xscale
= xscale
;
2018 lcd_dma
.yscale
= yscale
;
2020 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale
);
2022 static void set_b1_regs(void)
2024 unsigned long top
, bottom
;
2027 unsigned long en
, fn
;
2029 unsigned long vxres
;
2030 unsigned int xscale
, yscale
;
2032 switch (lcd_dma
.data_type
) {
2033 case OMAP_DMA_DATA_TYPE_S8
:
2036 case OMAP_DMA_DATA_TYPE_S16
:
2039 case OMAP_DMA_DATA_TYPE_S32
:
2047 vxres
= lcd_dma
.vxres
? lcd_dma
.vxres
: lcd_dma
.xres
;
2048 xscale
= lcd_dma
.xscale
? lcd_dma
.xscale
: 1;
2049 yscale
= lcd_dma
.yscale
? lcd_dma
.yscale
: 1;
2050 BUG_ON(vxres
< lcd_dma
.xres
);
2052 #define PIXADDR(x, y) (lcd_dma.addr + \
2053 ((y) * vxres * yscale + (x) * xscale) * es)
2054 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2056 switch (lcd_dma
.rotate
) {
2058 if (!lcd_dma
.mirror
) {
2059 top
= PIXADDR(0, 0);
2060 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2061 /* 1510 DMA requires the bottom address to be 2 more
2062 * than the actual last memory access location. */
2063 if (omap_dma_in_1510_mode() &&
2064 lcd_dma
.data_type
== OMAP_DMA_DATA_TYPE_S32
)
2066 ei
= PIXSTEP(0, 0, 1, 0);
2067 fi
= PIXSTEP(lcd_dma
.xres
- 1, 0, 0, 1);
2069 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
2070 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
2071 ei
= PIXSTEP(1, 0, 0, 0);
2072 fi
= PIXSTEP(0, 0, lcd_dma
.xres
- 1, 1);
2078 if (!lcd_dma
.mirror
) {
2079 top
= PIXADDR(0, lcd_dma
.yres
- 1);
2080 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
2081 ei
= PIXSTEP(0, 1, 0, 0);
2082 fi
= PIXSTEP(0, 0, 1, lcd_dma
.yres
- 1);
2084 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2085 bottom
= PIXADDR(0, 0);
2086 ei
= PIXSTEP(0, 1, 0, 0);
2087 fi
= PIXSTEP(1, 0, 0, lcd_dma
.yres
- 1);
2093 if (!lcd_dma
.mirror
) {
2094 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2095 bottom
= PIXADDR(0, 0);
2096 ei
= PIXSTEP(1, 0, 0, 0);
2097 fi
= PIXSTEP(0, 1, lcd_dma
.xres
- 1, 0);
2099 top
= PIXADDR(0, lcd_dma
.yres
- 1);
2100 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
2101 ei
= PIXSTEP(0, 0, 1, 0);
2102 fi
= PIXSTEP(lcd_dma
.xres
- 1, 1, 0, 0);
2108 if (!lcd_dma
.mirror
) {
2109 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
2110 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
2111 ei
= PIXSTEP(0, 0, 0, 1);
2112 fi
= PIXSTEP(1, lcd_dma
.yres
- 1, 0, 0);
2114 top
= PIXADDR(0, 0);
2115 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2116 ei
= PIXSTEP(0, 0, 0, 1);
2117 fi
= PIXSTEP(0, lcd_dma
.yres
- 1, 1, 0);
2124 return; /* Suppress warning about uninitialized vars */
2127 if (omap_dma_in_1510_mode()) {
2128 omap_writew(top
>> 16, OMAP1510_DMA_LCD_TOP_F1_U
);
2129 omap_writew(top
, OMAP1510_DMA_LCD_TOP_F1_L
);
2130 omap_writew(bottom
>> 16, OMAP1510_DMA_LCD_BOT_F1_U
);
2131 omap_writew(bottom
, OMAP1510_DMA_LCD_BOT_F1_L
);
2137 omap_writew(top
>> 16, OMAP1610_DMA_LCD_TOP_B1_U
);
2138 omap_writew(top
, OMAP1610_DMA_LCD_TOP_B1_L
);
2139 omap_writew(bottom
>> 16, OMAP1610_DMA_LCD_BOT_B1_U
);
2140 omap_writew(bottom
, OMAP1610_DMA_LCD_BOT_B1_L
);
2142 omap_writew(en
, OMAP1610_DMA_LCD_SRC_EN_B1
);
2143 omap_writew(fn
, OMAP1610_DMA_LCD_SRC_FN_B1
);
2145 w
= omap_readw(OMAP1610_DMA_LCD_CSDP
);
2147 w
|= lcd_dma
.data_type
;
2148 omap_writew(w
, OMAP1610_DMA_LCD_CSDP
);
2150 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2151 /* Always set the source port as SDRAM for now*/
2153 if (lcd_dma
.callback
!= NULL
)
2154 w
|= 1 << 1; /* Block interrupt enable */
2157 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2159 if (!(lcd_dma
.rotate
|| lcd_dma
.mirror
||
2160 lcd_dma
.vxres
|| lcd_dma
.xscale
|| lcd_dma
.yscale
))
2163 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2164 /* Set the double-indexed addressing mode */
2166 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2168 omap_writew(ei
, OMAP1610_DMA_LCD_SRC_EI_B1
);
2169 omap_writew(fi
>> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U
);
2170 omap_writew(fi
, OMAP1610_DMA_LCD_SRC_FI_B1_L
);
2173 static irqreturn_t
lcd_dma_irq_handler(int irq
, void *dev_id
)
2177 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2178 if (unlikely(!(w
& (1 << 3)))) {
2179 printk(KERN_WARNING
"Spurious LCD DMA IRQ\n");
2184 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2186 if (lcd_dma
.callback
!= NULL
)
2187 lcd_dma
.callback(w
, lcd_dma
.cb_data
);
2192 int omap_request_lcd_dma(void (*callback
)(u16 status
, void *data
),
2195 spin_lock_irq(&lcd_dma
.lock
);
2196 if (lcd_dma
.reserved
) {
2197 spin_unlock_irq(&lcd_dma
.lock
);
2198 printk(KERN_ERR
"LCD DMA channel already reserved\n");
2202 lcd_dma
.reserved
= 1;
2203 spin_unlock_irq(&lcd_dma
.lock
);
2204 lcd_dma
.callback
= callback
;
2205 lcd_dma
.cb_data
= data
;
2207 lcd_dma
.single_transfer
= 0;
2213 lcd_dma
.ext_ctrl
= 0;
2214 lcd_dma
.src_port
= 0;
2218 EXPORT_SYMBOL(omap_request_lcd_dma
);
2220 void omap_free_lcd_dma(void)
2222 spin_lock(&lcd_dma
.lock
);
2223 if (!lcd_dma
.reserved
) {
2224 spin_unlock(&lcd_dma
.lock
);
2225 printk(KERN_ERR
"LCD DMA is not reserved\n");
2229 if (!enable_1510_mode
)
2230 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR
) & ~1,
2231 OMAP1610_DMA_LCD_CCR
);
2232 lcd_dma
.reserved
= 0;
2233 spin_unlock(&lcd_dma
.lock
);
2235 EXPORT_SYMBOL(omap_free_lcd_dma
);
2237 void omap_enable_lcd_dma(void)
2242 * Set the Enable bit only if an external controller is
2243 * connected. Otherwise the OMAP internal controller will
2244 * start the transfer when it gets enabled.
2246 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2249 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2251 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2255 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2257 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2259 EXPORT_SYMBOL(omap_enable_lcd_dma
);
2261 void omap_setup_lcd_dma(void)
2263 BUG_ON(lcd_dma
.active
);
2264 if (!enable_1510_mode
) {
2265 /* Set some reasonable defaults */
2266 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR
);
2267 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP
);
2268 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL
);
2271 if (!enable_1510_mode
) {
2274 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2276 * If DMA was already active set the end_prog bit to have
2277 * the programmed register set loaded into the active
2280 w
|= 1 << 11; /* End_prog */
2281 if (!lcd_dma
.single_transfer
)
2282 w
|= (3 << 8); /* Auto_init, repeat */
2283 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2286 EXPORT_SYMBOL(omap_setup_lcd_dma
);
2288 void omap_stop_lcd_dma(void)
2293 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2296 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2298 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2300 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2302 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2304 EXPORT_SYMBOL(omap_stop_lcd_dma
);
2306 /*----------------------------------------------------------------------------*/
2308 static int __init
omap_init_dma(void)
2312 if (cpu_class_is_omap1()) {
2313 omap_dma_base
= IO_ADDRESS(OMAP1_DMA_BASE
);
2314 dma_lch_count
= OMAP1_LOGICAL_DMA_CH_COUNT
;
2315 } else if (cpu_is_omap24xx()) {
2316 omap_dma_base
= IO_ADDRESS(OMAP24XX_DMA4_BASE
);
2317 dma_lch_count
= OMAP_DMA4_LOGICAL_DMA_CH_COUNT
;
2318 } else if (cpu_is_omap34xx()) {
2319 omap_dma_base
= IO_ADDRESS(OMAP34XX_DMA4_BASE
);
2320 dma_lch_count
= OMAP_DMA4_LOGICAL_DMA_CH_COUNT
;
2322 pr_err("DMA init failed for unsupported omap\n");
2326 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2327 && (omap_dma_reserve_channels
<= dma_lch_count
))
2328 dma_lch_count
= omap_dma_reserve_channels
;
2330 dma_chan
= kzalloc(sizeof(struct omap_dma_lch
) * dma_lch_count
,
2335 if (cpu_class_is_omap2()) {
2336 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2337 dma_lch_count
, GFP_KERNEL
);
2338 if (!dma_linked_lch
) {
2344 if (cpu_is_omap15xx()) {
2345 printk(KERN_INFO
"DMA support for OMAP15xx initialized\n");
2347 enable_1510_mode
= 1;
2348 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2349 printk(KERN_INFO
"OMAP DMA hardware version %d\n",
2351 printk(KERN_INFO
"DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2352 (dma_read(CAPS_0_U
) << 16) |
2354 (dma_read(CAPS_1_U
) << 16) |
2356 dma_read(CAPS_2
), dma_read(CAPS_3
),
2358 if (!enable_1510_mode
) {
2361 /* Disable OMAP 3.0/3.1 compatibility mode. */
2365 dma_chan_count
= 16;
2368 if (cpu_is_omap16xx()) {
2371 /* this would prevent OMAP sleep */
2372 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2374 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2376 } else if (cpu_class_is_omap2()) {
2377 u8 revision
= dma_read(REVISION
) & 0xff;
2378 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
2379 revision
>> 4, revision
& 0xf);
2380 dma_chan_count
= dma_lch_count
;
2386 spin_lock_init(&lcd_dma
.lock
);
2387 spin_lock_init(&dma_chan_lock
);
2389 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2391 dma_chan
[ch
].dev_id
= -1;
2392 dma_chan
[ch
].next_lch
= -1;
2394 if (ch
>= 6 && enable_1510_mode
)
2397 if (cpu_class_is_omap1()) {
2399 * request_irq() doesn't like dev_id (ie. ch) being
2400 * zero, so we have to kludge around this.
2402 r
= request_irq(omap1_dma_irq
[ch
],
2403 omap1_dma_irq_handler
, 0, "DMA",
2408 printk(KERN_ERR
"unable to request IRQ %d "
2409 "for DMA (error %d)\n",
2410 omap1_dma_irq
[ch
], r
);
2411 for (i
= 0; i
< ch
; i
++)
2412 free_irq(omap1_dma_irq
[i
],
2419 if (cpu_is_omap2430() || cpu_is_omap34xx())
2420 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2421 DMA_DEFAULT_FIFO_DEPTH
, 0);
2423 if (cpu_class_is_omap2())
2424 setup_irq(INT_24XX_SDMA_IRQ0
, &omap24xx_dma_irq
);
2426 /* FIXME: Update LCD DMA to work on 24xx */
2427 if (cpu_class_is_omap1()) {
2428 r
= request_irq(INT_DMA_LCD
, lcd_dma_irq_handler
, 0,
2433 printk(KERN_ERR
"unable to request IRQ for LCD DMA "
2435 for (i
= 0; i
< dma_chan_count
; i
++)
2436 free_irq(omap1_dma_irq
[i
], (void *) (i
+ 1));
2444 arch_initcall(omap_init_dma
);
2447 * Reserve the omap SDMA channels using cmdline bootarg
2448 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2450 static int __init
omap_dma_cmdline_reserve_ch(char *str
)
2452 if (get_option(&str
, &omap_dma_reserve_channels
) != 1)
2453 omap_dma_reserve_channels
= 0;
2457 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch
);