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Merge branch 'fix/hda' into for-linus
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/io.h>
29
30 #include <asm/system.h>
31 #include <mach/hardware.h>
32 #include <mach/dma.h>
33
34 #include <mach/tc.h>
35
36 #undef DEBUG
37
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41 };
42
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44 #endif
45
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51
52 static int enable_1510_mode;
53
54 struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data;
62
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71 #endif
72 long flags;
73 };
74
75 struct dma_link_info {
76 int *linked_dmach_q;
77 int no_of_lchs_linked;
78
79 int q_count;
80 int q_tail;
81 int q_head;
82
83 int chain_state;
84 int chain_mode;
85
86 };
87
88 static struct dma_link_info *dma_linked_lch;
89
90 #ifndef CONFIG_ARCH_OMAP1
91
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 do { \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
98 } while (0)
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 do { \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
106 } while (0)
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 do { \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
115 } while (0)
116
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 do { \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
121 } while (0)
122 #endif
123
124 static int dma_lch_count;
125 static int dma_chan_count;
126 static int omap_dma_reserve_channels;
127
128 static spinlock_t dma_chan_lock;
129 static struct omap_dma_lch *dma_chan;
130 static void __iomem *omap_dma_base;
131
132 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
133 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
134 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
135 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
136 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
137 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
138 };
139
140 static inline void disable_lnk(int lch);
141 static void omap_disable_channel_irq(int lch);
142 static inline void omap_enable_channel_irq(int lch);
143
144 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
145 __func__);
146
147 #define dma_read(reg) \
148 ({ \
149 u32 __val; \
150 if (cpu_class_is_omap1()) \
151 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
152 else \
153 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
154 __val; \
155 })
156
157 #define dma_write(val, reg) \
158 ({ \
159 if (cpu_class_is_omap1()) \
160 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
161 else \
162 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
163 })
164
165 #ifdef CONFIG_ARCH_OMAP15XX
166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
167 int omap_dma_in_1510_mode(void)
168 {
169 return enable_1510_mode;
170 }
171 #else
172 #define omap_dma_in_1510_mode() 0
173 #endif
174
175 #ifdef CONFIG_ARCH_OMAP1
176 static inline int get_gdma_dev(int req)
177 {
178 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
179 int shift = ((req - 1) % 5) * 6;
180
181 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
182 }
183
184 static inline void set_gdma_dev(int req, int dev)
185 {
186 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
187 int shift = ((req - 1) % 5) * 6;
188 u32 l;
189
190 l = omap_readl(reg);
191 l &= ~(0x3f << shift);
192 l |= (dev - 1) << shift;
193 omap_writel(l, reg);
194 }
195 #else
196 #define set_gdma_dev(req, dev) do {} while (0)
197 #endif
198
199 /* Omap1 only */
200 static void clear_lch_regs(int lch)
201 {
202 int i;
203 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
204
205 for (i = 0; i < 0x2c; i += 2)
206 __raw_writew(0, lch_base + i);
207 }
208
209 void omap_set_dma_priority(int lch, int dst_port, int priority)
210 {
211 unsigned long reg;
212 u32 l;
213
214 if (cpu_class_is_omap1()) {
215 switch (dst_port) {
216 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
217 reg = OMAP_TC_OCPT1_PRIOR;
218 break;
219 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
220 reg = OMAP_TC_OCPT2_PRIOR;
221 break;
222 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
223 reg = OMAP_TC_EMIFF_PRIOR;
224 break;
225 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
226 reg = OMAP_TC_EMIFS_PRIOR;
227 break;
228 default:
229 BUG();
230 return;
231 }
232 l = omap_readl(reg);
233 l &= ~(0xf << 8);
234 l |= (priority & 0xf) << 8;
235 omap_writel(l, reg);
236 }
237
238 if (cpu_class_is_omap2()) {
239 u32 ccr;
240
241 ccr = dma_read(CCR(lch));
242 if (priority)
243 ccr |= (1 << 6);
244 else
245 ccr &= ~(1 << 6);
246 dma_write(ccr, CCR(lch));
247 }
248 }
249 EXPORT_SYMBOL(omap_set_dma_priority);
250
251 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
252 int frame_count, int sync_mode,
253 int dma_trigger, int src_or_dst_synch)
254 {
255 u32 l;
256
257 l = dma_read(CSDP(lch));
258 l &= ~0x03;
259 l |= data_type;
260 dma_write(l, CSDP(lch));
261
262 if (cpu_class_is_omap1()) {
263 u16 ccr;
264
265 ccr = dma_read(CCR(lch));
266 ccr &= ~(1 << 5);
267 if (sync_mode == OMAP_DMA_SYNC_FRAME)
268 ccr |= 1 << 5;
269 dma_write(ccr, CCR(lch));
270
271 ccr = dma_read(CCR2(lch));
272 ccr &= ~(1 << 2);
273 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
274 ccr |= 1 << 2;
275 dma_write(ccr, CCR2(lch));
276 }
277
278 if (cpu_class_is_omap2() && dma_trigger) {
279 u32 val;
280
281 val = dma_read(CCR(lch));
282
283 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
284 val &= ~((3 << 19) | 0x1f);
285 val |= (dma_trigger & ~0x1f) << 14;
286 val |= dma_trigger & 0x1f;
287
288 if (sync_mode & OMAP_DMA_SYNC_FRAME)
289 val |= 1 << 5;
290 else
291 val &= ~(1 << 5);
292
293 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
294 val |= 1 << 18;
295 else
296 val &= ~(1 << 18);
297
298 if (src_or_dst_synch)
299 val |= 1 << 24; /* source synch */
300 else
301 val &= ~(1 << 24); /* dest synch */
302
303 dma_write(val, CCR(lch));
304 }
305
306 dma_write(elem_count, CEN(lch));
307 dma_write(frame_count, CFN(lch));
308 }
309 EXPORT_SYMBOL(omap_set_dma_transfer_params);
310
311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
312 {
313 u16 w;
314
315 BUG_ON(omap_dma_in_1510_mode());
316
317 if (cpu_class_is_omap2()) {
318 REVISIT_24XX();
319 return;
320 }
321
322 w = dma_read(CCR2(lch));
323 w &= ~0x03;
324
325 switch (mode) {
326 case OMAP_DMA_CONSTANT_FILL:
327 w |= 0x01;
328 break;
329 case OMAP_DMA_TRANSPARENT_COPY:
330 w |= 0x02;
331 break;
332 case OMAP_DMA_COLOR_DIS:
333 break;
334 default:
335 BUG();
336 }
337 dma_write(w, CCR2(lch));
338
339 w = dma_read(LCH_CTRL(lch));
340 w &= ~0x0f;
341 /* Default is channel type 2D */
342 if (mode) {
343 dma_write((u16)color, COLOR_L(lch));
344 dma_write((u16)(color >> 16), COLOR_U(lch));
345 w |= 1; /* Channel type G */
346 }
347 dma_write(w, LCH_CTRL(lch));
348 }
349 EXPORT_SYMBOL(omap_set_dma_color_mode);
350
351 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
352 {
353 if (cpu_class_is_omap2()) {
354 u32 csdp;
355
356 csdp = dma_read(CSDP(lch));
357 csdp &= ~(0x3 << 16);
358 csdp |= (mode << 16);
359 dma_write(csdp, CSDP(lch));
360 }
361 }
362 EXPORT_SYMBOL(omap_set_dma_write_mode);
363
364 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
365 {
366 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
367 u32 l;
368
369 l = dma_read(LCH_CTRL(lch));
370 l &= ~0x7;
371 l |= mode;
372 dma_write(l, LCH_CTRL(lch));
373 }
374 }
375 EXPORT_SYMBOL(omap_set_dma_channel_mode);
376
377 /* Note that src_port is only for omap1 */
378 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
379 unsigned long src_start,
380 int src_ei, int src_fi)
381 {
382 u32 l;
383
384 if (cpu_class_is_omap1()) {
385 u16 w;
386
387 w = dma_read(CSDP(lch));
388 w &= ~(0x1f << 2);
389 w |= src_port << 2;
390 dma_write(w, CSDP(lch));
391 }
392
393 l = dma_read(CCR(lch));
394 l &= ~(0x03 << 12);
395 l |= src_amode << 12;
396 dma_write(l, CCR(lch));
397
398 if (cpu_class_is_omap1()) {
399 dma_write(src_start >> 16, CSSA_U(lch));
400 dma_write((u16)src_start, CSSA_L(lch));
401 }
402
403 if (cpu_class_is_omap2())
404 dma_write(src_start, CSSA(lch));
405
406 dma_write(src_ei, CSEI(lch));
407 dma_write(src_fi, CSFI(lch));
408 }
409 EXPORT_SYMBOL(omap_set_dma_src_params);
410
411 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
412 {
413 omap_set_dma_transfer_params(lch, params->data_type,
414 params->elem_count, params->frame_count,
415 params->sync_mode, params->trigger,
416 params->src_or_dst_synch);
417 omap_set_dma_src_params(lch, params->src_port,
418 params->src_amode, params->src_start,
419 params->src_ei, params->src_fi);
420
421 omap_set_dma_dest_params(lch, params->dst_port,
422 params->dst_amode, params->dst_start,
423 params->dst_ei, params->dst_fi);
424 if (params->read_prio || params->write_prio)
425 omap_dma_set_prio_lch(lch, params->read_prio,
426 params->write_prio);
427 }
428 EXPORT_SYMBOL(omap_set_dma_params);
429
430 void omap_set_dma_src_index(int lch, int eidx, int fidx)
431 {
432 if (cpu_class_is_omap2())
433 return;
434
435 dma_write(eidx, CSEI(lch));
436 dma_write(fidx, CSFI(lch));
437 }
438 EXPORT_SYMBOL(omap_set_dma_src_index);
439
440 void omap_set_dma_src_data_pack(int lch, int enable)
441 {
442 u32 l;
443
444 l = dma_read(CSDP(lch));
445 l &= ~(1 << 6);
446 if (enable)
447 l |= (1 << 6);
448 dma_write(l, CSDP(lch));
449 }
450 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
451
452 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
453 {
454 unsigned int burst = 0;
455 u32 l;
456
457 l = dma_read(CSDP(lch));
458 l &= ~(0x03 << 7);
459
460 switch (burst_mode) {
461 case OMAP_DMA_DATA_BURST_DIS:
462 break;
463 case OMAP_DMA_DATA_BURST_4:
464 if (cpu_class_is_omap2())
465 burst = 0x1;
466 else
467 burst = 0x2;
468 break;
469 case OMAP_DMA_DATA_BURST_8:
470 if (cpu_class_is_omap2()) {
471 burst = 0x2;
472 break;
473 }
474 /* not supported by current hardware on OMAP1
475 * w |= (0x03 << 7);
476 * fall through
477 */
478 case OMAP_DMA_DATA_BURST_16:
479 if (cpu_class_is_omap2()) {
480 burst = 0x3;
481 break;
482 }
483 /* OMAP1 don't support burst 16
484 * fall through
485 */
486 default:
487 BUG();
488 }
489
490 l |= (burst << 7);
491 dma_write(l, CSDP(lch));
492 }
493 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
494
495 /* Note that dest_port is only for OMAP1 */
496 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
497 unsigned long dest_start,
498 int dst_ei, int dst_fi)
499 {
500 u32 l;
501
502 if (cpu_class_is_omap1()) {
503 l = dma_read(CSDP(lch));
504 l &= ~(0x1f << 9);
505 l |= dest_port << 9;
506 dma_write(l, CSDP(lch));
507 }
508
509 l = dma_read(CCR(lch));
510 l &= ~(0x03 << 14);
511 l |= dest_amode << 14;
512 dma_write(l, CCR(lch));
513
514 if (cpu_class_is_omap1()) {
515 dma_write(dest_start >> 16, CDSA_U(lch));
516 dma_write(dest_start, CDSA_L(lch));
517 }
518
519 if (cpu_class_is_omap2())
520 dma_write(dest_start, CDSA(lch));
521
522 dma_write(dst_ei, CDEI(lch));
523 dma_write(dst_fi, CDFI(lch));
524 }
525 EXPORT_SYMBOL(omap_set_dma_dest_params);
526
527 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
528 {
529 if (cpu_class_is_omap2())
530 return;
531
532 dma_write(eidx, CDEI(lch));
533 dma_write(fidx, CDFI(lch));
534 }
535 EXPORT_SYMBOL(omap_set_dma_dest_index);
536
537 void omap_set_dma_dest_data_pack(int lch, int enable)
538 {
539 u32 l;
540
541 l = dma_read(CSDP(lch));
542 l &= ~(1 << 13);
543 if (enable)
544 l |= 1 << 13;
545 dma_write(l, CSDP(lch));
546 }
547 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
548
549 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
550 {
551 unsigned int burst = 0;
552 u32 l;
553
554 l = dma_read(CSDP(lch));
555 l &= ~(0x03 << 14);
556
557 switch (burst_mode) {
558 case OMAP_DMA_DATA_BURST_DIS:
559 break;
560 case OMAP_DMA_DATA_BURST_4:
561 if (cpu_class_is_omap2())
562 burst = 0x1;
563 else
564 burst = 0x2;
565 break;
566 case OMAP_DMA_DATA_BURST_8:
567 if (cpu_class_is_omap2())
568 burst = 0x2;
569 else
570 burst = 0x3;
571 break;
572 case OMAP_DMA_DATA_BURST_16:
573 if (cpu_class_is_omap2()) {
574 burst = 0x3;
575 break;
576 }
577 /* OMAP1 don't support burst 16
578 * fall through
579 */
580 default:
581 printk(KERN_ERR "Invalid DMA burst mode\n");
582 BUG();
583 return;
584 }
585 l |= (burst << 14);
586 dma_write(l, CSDP(lch));
587 }
588 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
589
590 static inline void omap_enable_channel_irq(int lch)
591 {
592 u32 status;
593
594 /* Clear CSR */
595 if (cpu_class_is_omap1())
596 status = dma_read(CSR(lch));
597 else if (cpu_class_is_omap2())
598 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
599
600 /* Enable some nice interrupts. */
601 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
602 }
603
604 static void omap_disable_channel_irq(int lch)
605 {
606 if (cpu_class_is_omap2())
607 dma_write(0, CICR(lch));
608 }
609
610 void omap_enable_dma_irq(int lch, u16 bits)
611 {
612 dma_chan[lch].enabled_irqs |= bits;
613 }
614 EXPORT_SYMBOL(omap_enable_dma_irq);
615
616 void omap_disable_dma_irq(int lch, u16 bits)
617 {
618 dma_chan[lch].enabled_irqs &= ~bits;
619 }
620 EXPORT_SYMBOL(omap_disable_dma_irq);
621
622 static inline void enable_lnk(int lch)
623 {
624 u32 l;
625
626 l = dma_read(CLNK_CTRL(lch));
627
628 if (cpu_class_is_omap1())
629 l &= ~(1 << 14);
630
631 /* Set the ENABLE_LNK bits */
632 if (dma_chan[lch].next_lch != -1)
633 l = dma_chan[lch].next_lch | (1 << 15);
634
635 #ifndef CONFIG_ARCH_OMAP1
636 if (cpu_class_is_omap2())
637 if (dma_chan[lch].next_linked_ch != -1)
638 l = dma_chan[lch].next_linked_ch | (1 << 15);
639 #endif
640
641 dma_write(l, CLNK_CTRL(lch));
642 }
643
644 static inline void disable_lnk(int lch)
645 {
646 u32 l;
647
648 l = dma_read(CLNK_CTRL(lch));
649
650 /* Disable interrupts */
651 if (cpu_class_is_omap1()) {
652 dma_write(0, CICR(lch));
653 /* Set the STOP_LNK bit */
654 l |= 1 << 14;
655 }
656
657 if (cpu_class_is_omap2()) {
658 omap_disable_channel_irq(lch);
659 /* Clear the ENABLE_LNK bit */
660 l &= ~(1 << 15);
661 }
662
663 dma_write(l, CLNK_CTRL(lch));
664 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
665 }
666
667 static inline void omap2_enable_irq_lch(int lch)
668 {
669 u32 val;
670
671 if (!cpu_class_is_omap2())
672 return;
673
674 val = dma_read(IRQENABLE_L0);
675 val |= 1 << lch;
676 dma_write(val, IRQENABLE_L0);
677 }
678
679 int omap_request_dma(int dev_id, const char *dev_name,
680 void (*callback)(int lch, u16 ch_status, void *data),
681 void *data, int *dma_ch_out)
682 {
683 int ch, free_ch = -1;
684 unsigned long flags;
685 struct omap_dma_lch *chan;
686
687 spin_lock_irqsave(&dma_chan_lock, flags);
688 for (ch = 0; ch < dma_chan_count; ch++) {
689 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
690 free_ch = ch;
691 if (dev_id == 0)
692 break;
693 }
694 }
695 if (free_ch == -1) {
696 spin_unlock_irqrestore(&dma_chan_lock, flags);
697 return -EBUSY;
698 }
699 chan = dma_chan + free_ch;
700 chan->dev_id = dev_id;
701
702 if (cpu_class_is_omap1())
703 clear_lch_regs(free_ch);
704
705 if (cpu_class_is_omap2())
706 omap_clear_dma(free_ch);
707
708 spin_unlock_irqrestore(&dma_chan_lock, flags);
709
710 chan->dev_name = dev_name;
711 chan->callback = callback;
712 chan->data = data;
713 chan->flags = 0;
714
715 #ifndef CONFIG_ARCH_OMAP1
716 if (cpu_class_is_omap2()) {
717 chan->chain_id = -1;
718 chan->next_linked_ch = -1;
719 }
720 #endif
721
722 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
723
724 if (cpu_class_is_omap1())
725 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
726 else if (cpu_class_is_omap2())
727 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
728 OMAP2_DMA_TRANS_ERR_IRQ;
729
730 if (cpu_is_omap16xx()) {
731 /* If the sync device is set, configure it dynamically. */
732 if (dev_id != 0) {
733 set_gdma_dev(free_ch + 1, dev_id);
734 dev_id = free_ch + 1;
735 }
736 /*
737 * Disable the 1510 compatibility mode and set the sync device
738 * id.
739 */
740 dma_write(dev_id | (1 << 10), CCR(free_ch));
741 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
742 dma_write(dev_id, CCR(free_ch));
743 }
744
745 if (cpu_class_is_omap2()) {
746 omap2_enable_irq_lch(free_ch);
747 omap_enable_channel_irq(free_ch);
748 /* Clear the CSR register and IRQ status register */
749 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
750 dma_write(1 << free_ch, IRQSTATUS_L0);
751 }
752
753 *dma_ch_out = free_ch;
754
755 return 0;
756 }
757 EXPORT_SYMBOL(omap_request_dma);
758
759 void omap_free_dma(int lch)
760 {
761 unsigned long flags;
762
763 if (dma_chan[lch].dev_id == -1) {
764 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
765 lch);
766 return;
767 }
768
769 if (cpu_class_is_omap1()) {
770 /* Disable all DMA interrupts for the channel. */
771 dma_write(0, CICR(lch));
772 /* Make sure the DMA transfer is stopped. */
773 dma_write(0, CCR(lch));
774 }
775
776 if (cpu_class_is_omap2()) {
777 u32 val;
778 /* Disable interrupts */
779 val = dma_read(IRQENABLE_L0);
780 val &= ~(1 << lch);
781 dma_write(val, IRQENABLE_L0);
782
783 /* Clear the CSR register and IRQ status register */
784 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
785 dma_write(1 << lch, IRQSTATUS_L0);
786
787 /* Disable all DMA interrupts for the channel. */
788 dma_write(0, CICR(lch));
789
790 /* Make sure the DMA transfer is stopped. */
791 dma_write(0, CCR(lch));
792 omap_clear_dma(lch);
793 }
794
795 spin_lock_irqsave(&dma_chan_lock, flags);
796 dma_chan[lch].dev_id = -1;
797 dma_chan[lch].next_lch = -1;
798 dma_chan[lch].callback = NULL;
799 spin_unlock_irqrestore(&dma_chan_lock, flags);
800 }
801 EXPORT_SYMBOL(omap_free_dma);
802
803 /**
804 * @brief omap_dma_set_global_params : Set global priority settings for dma
805 *
806 * @param arb_rate
807 * @param max_fifo_depth
808 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
809 * DMA_THREAD_RESERVE_ONET
810 * DMA_THREAD_RESERVE_TWOT
811 * DMA_THREAD_RESERVE_THREET
812 */
813 void
814 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
815 {
816 u32 reg;
817
818 if (!cpu_class_is_omap2()) {
819 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
820 return;
821 }
822
823 if (arb_rate == 0)
824 arb_rate = 1;
825
826 reg = (arb_rate & 0xff) << 16;
827 reg |= (0xff & max_fifo_depth);
828
829 dma_write(reg, GCR);
830 }
831 EXPORT_SYMBOL(omap_dma_set_global_params);
832
833 /**
834 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
835 *
836 * @param lch
837 * @param read_prio - Read priority
838 * @param write_prio - Write priority
839 * Both of the above can be set with one of the following values :
840 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
841 */
842 int
843 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
844 unsigned char write_prio)
845 {
846 u32 l;
847
848 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
849 printk(KERN_ERR "Invalid channel id\n");
850 return -EINVAL;
851 }
852 l = dma_read(CCR(lch));
853 l &= ~((1 << 6) | (1 << 26));
854 if (cpu_is_omap2430() || cpu_is_omap34xx())
855 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
856 else
857 l |= ((read_prio & 0x1) << 6);
858
859 dma_write(l, CCR(lch));
860
861 return 0;
862 }
863 EXPORT_SYMBOL(omap_dma_set_prio_lch);
864
865 /*
866 * Clears any DMA state so the DMA engine is ready to restart with new buffers
867 * through omap_start_dma(). Any buffers in flight are discarded.
868 */
869 void omap_clear_dma(int lch)
870 {
871 unsigned long flags;
872
873 local_irq_save(flags);
874
875 if (cpu_class_is_omap1()) {
876 u32 l;
877
878 l = dma_read(CCR(lch));
879 l &= ~OMAP_DMA_CCR_EN;
880 dma_write(l, CCR(lch));
881
882 /* Clear pending interrupts */
883 l = dma_read(CSR(lch));
884 }
885
886 if (cpu_class_is_omap2()) {
887 int i;
888 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
889 for (i = 0; i < 0x44; i += 4)
890 __raw_writel(0, lch_base + i);
891 }
892
893 local_irq_restore(flags);
894 }
895 EXPORT_SYMBOL(omap_clear_dma);
896
897 void omap_start_dma(int lch)
898 {
899 u32 l;
900
901 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
902 int next_lch, cur_lch;
903 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
904
905 dma_chan_link_map[lch] = 1;
906 /* Set the link register of the first channel */
907 enable_lnk(lch);
908
909 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
910 cur_lch = dma_chan[lch].next_lch;
911 do {
912 next_lch = dma_chan[cur_lch].next_lch;
913
914 /* The loop case: we've been here already */
915 if (dma_chan_link_map[cur_lch])
916 break;
917 /* Mark the current channel */
918 dma_chan_link_map[cur_lch] = 1;
919
920 enable_lnk(cur_lch);
921 omap_enable_channel_irq(cur_lch);
922
923 cur_lch = next_lch;
924 } while (next_lch != -1);
925 } else if (cpu_class_is_omap2()) {
926 /* Errata: Need to write lch even if not using chaining */
927 dma_write(lch, CLNK_CTRL(lch));
928 }
929
930 omap_enable_channel_irq(lch);
931
932 l = dma_read(CCR(lch));
933
934 /*
935 * Errata: On ES2.0 BUFFERING disable must be set.
936 * This will always fail on ES1.0
937 */
938 if (cpu_is_omap24xx())
939 l |= OMAP_DMA_CCR_EN;
940
941 l |= OMAP_DMA_CCR_EN;
942 dma_write(l, CCR(lch));
943
944 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
945 }
946 EXPORT_SYMBOL(omap_start_dma);
947
948 void omap_stop_dma(int lch)
949 {
950 u32 l;
951
952 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
953 int next_lch, cur_lch = lch;
954 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
955
956 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
957 do {
958 /* The loop case: we've been here already */
959 if (dma_chan_link_map[cur_lch])
960 break;
961 /* Mark the current channel */
962 dma_chan_link_map[cur_lch] = 1;
963
964 disable_lnk(cur_lch);
965
966 next_lch = dma_chan[cur_lch].next_lch;
967 cur_lch = next_lch;
968 } while (next_lch != -1);
969
970 return;
971 }
972
973 /* Disable all interrupts on the channel */
974 if (cpu_class_is_omap1())
975 dma_write(0, CICR(lch));
976
977 l = dma_read(CCR(lch));
978 l &= ~OMAP_DMA_CCR_EN;
979 dma_write(l, CCR(lch));
980
981 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
982 }
983 EXPORT_SYMBOL(omap_stop_dma);
984
985 /*
986 * Allows changing the DMA callback function or data. This may be needed if
987 * the driver shares a single DMA channel for multiple dma triggers.
988 */
989 int omap_set_dma_callback(int lch,
990 void (*callback)(int lch, u16 ch_status, void *data),
991 void *data)
992 {
993 unsigned long flags;
994
995 if (lch < 0)
996 return -ENODEV;
997
998 spin_lock_irqsave(&dma_chan_lock, flags);
999 if (dma_chan[lch].dev_id == -1) {
1000 printk(KERN_ERR "DMA callback for not set for free channel\n");
1001 spin_unlock_irqrestore(&dma_chan_lock, flags);
1002 return -EINVAL;
1003 }
1004 dma_chan[lch].callback = callback;
1005 dma_chan[lch].data = data;
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1007
1008 return 0;
1009 }
1010 EXPORT_SYMBOL(omap_set_dma_callback);
1011
1012 /*
1013 * Returns current physical source address for the given DMA channel.
1014 * If the channel is running the caller must disable interrupts prior calling
1015 * this function and process the returned value before re-enabling interrupt to
1016 * prevent races with the interrupt handler. Note that in continuous mode there
1017 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1018 * in incorrect return value.
1019 */
1020 dma_addr_t omap_get_dma_src_pos(int lch)
1021 {
1022 dma_addr_t offset = 0;
1023
1024 if (cpu_is_omap15xx())
1025 offset = dma_read(CPC(lch));
1026 else
1027 offset = dma_read(CSAC(lch));
1028
1029 /*
1030 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1031 * read before the DMA controller finished disabling the channel.
1032 */
1033 if (!cpu_is_omap15xx() && offset == 0)
1034 offset = dma_read(CSAC(lch));
1035
1036 if (cpu_class_is_omap1())
1037 offset |= (dma_read(CSSA_U(lch)) << 16);
1038
1039 return offset;
1040 }
1041 EXPORT_SYMBOL(omap_get_dma_src_pos);
1042
1043 /*
1044 * Returns current physical destination address for the given DMA channel.
1045 * If the channel is running the caller must disable interrupts prior calling
1046 * this function and process the returned value before re-enabling interrupt to
1047 * prevent races with the interrupt handler. Note that in continuous mode there
1048 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1049 * in incorrect return value.
1050 */
1051 dma_addr_t omap_get_dma_dst_pos(int lch)
1052 {
1053 dma_addr_t offset = 0;
1054
1055 if (cpu_is_omap15xx())
1056 offset = dma_read(CPC(lch));
1057 else
1058 offset = dma_read(CDAC(lch));
1059
1060 /*
1061 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1062 * read before the DMA controller finished disabling the channel.
1063 */
1064 if (!cpu_is_omap15xx() && offset == 0)
1065 offset = dma_read(CDAC(lch));
1066
1067 if (cpu_class_is_omap1())
1068 offset |= (dma_read(CDSA_U(lch)) << 16);
1069
1070 return offset;
1071 }
1072 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1073
1074 int omap_get_dma_active_status(int lch)
1075 {
1076 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1077 }
1078 EXPORT_SYMBOL(omap_get_dma_active_status);
1079
1080 int omap_dma_running(void)
1081 {
1082 int lch;
1083
1084 /* Check if LCD DMA is running */
1085 if (cpu_is_omap16xx())
1086 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1087 return 1;
1088
1089 for (lch = 0; lch < dma_chan_count; lch++)
1090 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1091 return 1;
1092
1093 return 0;
1094 }
1095
1096 /*
1097 * lch_queue DMA will start right after lch_head one is finished.
1098 * For this DMA link to start, you still need to start (see omap_start_dma)
1099 * the first one. That will fire up the entire queue.
1100 */
1101 void omap_dma_link_lch(int lch_head, int lch_queue)
1102 {
1103 if (omap_dma_in_1510_mode()) {
1104 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1105 BUG();
1106 return;
1107 }
1108
1109 if ((dma_chan[lch_head].dev_id == -1) ||
1110 (dma_chan[lch_queue].dev_id == -1)) {
1111 printk(KERN_ERR "omap_dma: trying to link "
1112 "non requested channels\n");
1113 dump_stack();
1114 }
1115
1116 dma_chan[lch_head].next_lch = lch_queue;
1117 }
1118 EXPORT_SYMBOL(omap_dma_link_lch);
1119
1120 /*
1121 * Once the DMA queue is stopped, we can destroy it.
1122 */
1123 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1124 {
1125 if (omap_dma_in_1510_mode()) {
1126 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1127 BUG();
1128 return;
1129 }
1130
1131 if (dma_chan[lch_head].next_lch != lch_queue ||
1132 dma_chan[lch_head].next_lch == -1) {
1133 printk(KERN_ERR "omap_dma: trying to unlink "
1134 "non linked channels\n");
1135 dump_stack();
1136 }
1137
1138 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1139 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1140 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1141 "before unlinking\n");
1142 dump_stack();
1143 }
1144
1145 dma_chan[lch_head].next_lch = -1;
1146 }
1147 EXPORT_SYMBOL(omap_dma_unlink_lch);
1148
1149 /*----------------------------------------------------------------------------*/
1150
1151 #ifndef CONFIG_ARCH_OMAP1
1152 /* Create chain of DMA channesls */
1153 static void create_dma_lch_chain(int lch_head, int lch_queue)
1154 {
1155 u32 l;
1156
1157 /* Check if this is the first link in chain */
1158 if (dma_chan[lch_head].next_linked_ch == -1) {
1159 dma_chan[lch_head].next_linked_ch = lch_queue;
1160 dma_chan[lch_head].prev_linked_ch = lch_queue;
1161 dma_chan[lch_queue].next_linked_ch = lch_head;
1162 dma_chan[lch_queue].prev_linked_ch = lch_head;
1163 }
1164
1165 /* a link exists, link the new channel in circular chain */
1166 else {
1167 dma_chan[lch_queue].next_linked_ch =
1168 dma_chan[lch_head].next_linked_ch;
1169 dma_chan[lch_queue].prev_linked_ch = lch_head;
1170 dma_chan[lch_head].next_linked_ch = lch_queue;
1171 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1172 lch_queue;
1173 }
1174
1175 l = dma_read(CLNK_CTRL(lch_head));
1176 l &= ~(0x1f);
1177 l |= lch_queue;
1178 dma_write(l, CLNK_CTRL(lch_head));
1179
1180 l = dma_read(CLNK_CTRL(lch_queue));
1181 l &= ~(0x1f);
1182 l |= (dma_chan[lch_queue].next_linked_ch);
1183 dma_write(l, CLNK_CTRL(lch_queue));
1184 }
1185
1186 /**
1187 * @brief omap_request_dma_chain : Request a chain of DMA channels
1188 *
1189 * @param dev_id - Device id using the dma channel
1190 * @param dev_name - Device name
1191 * @param callback - Call back function
1192 * @chain_id -
1193 * @no_of_chans - Number of channels requested
1194 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1195 * OMAP_DMA_DYNAMIC_CHAIN
1196 * @params - Channel parameters
1197 *
1198 * @return - Succes : 0
1199 * Failure: -EINVAL/-ENOMEM
1200 */
1201 int omap_request_dma_chain(int dev_id, const char *dev_name,
1202 void (*callback) (int chain_id, u16 ch_status,
1203 void *data),
1204 int *chain_id, int no_of_chans, int chain_mode,
1205 struct omap_dma_channel_params params)
1206 {
1207 int *channels;
1208 int i, err;
1209
1210 /* Is the chain mode valid ? */
1211 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1212 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1213 printk(KERN_ERR "Invalid chain mode requested\n");
1214 return -EINVAL;
1215 }
1216
1217 if (unlikely((no_of_chans < 1
1218 || no_of_chans > dma_lch_count))) {
1219 printk(KERN_ERR "Invalid Number of channels requested\n");
1220 return -EINVAL;
1221 }
1222
1223 /* Allocate a queue to maintain the status of the channels
1224 * in the chain */
1225 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1226 if (channels == NULL) {
1227 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1228 return -ENOMEM;
1229 }
1230
1231 /* request and reserve DMA channels for the chain */
1232 for (i = 0; i < no_of_chans; i++) {
1233 err = omap_request_dma(dev_id, dev_name,
1234 callback, NULL, &channels[i]);
1235 if (err < 0) {
1236 int j;
1237 for (j = 0; j < i; j++)
1238 omap_free_dma(channels[j]);
1239 kfree(channels);
1240 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1241 return err;
1242 }
1243 dma_chan[channels[i]].prev_linked_ch = -1;
1244 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1245
1246 /*
1247 * Allowing client drivers to set common parameters now,
1248 * so that later only relevant (src_start, dest_start
1249 * and element count) can be set
1250 */
1251 omap_set_dma_params(channels[i], &params);
1252 }
1253
1254 *chain_id = channels[0];
1255 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1256 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1257 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1258 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1259
1260 for (i = 0; i < no_of_chans; i++)
1261 dma_chan[channels[i]].chain_id = *chain_id;
1262
1263 /* Reset the Queue pointers */
1264 OMAP_DMA_CHAIN_QINIT(*chain_id);
1265
1266 /* Set up the chain */
1267 if (no_of_chans == 1)
1268 create_dma_lch_chain(channels[0], channels[0]);
1269 else {
1270 for (i = 0; i < (no_of_chans - 1); i++)
1271 create_dma_lch_chain(channels[i], channels[i + 1]);
1272 }
1273
1274 return 0;
1275 }
1276 EXPORT_SYMBOL(omap_request_dma_chain);
1277
1278 /**
1279 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1280 * params after setting it. Dont do this while dma is running!!
1281 *
1282 * @param chain_id - Chained logical channel id.
1283 * @param params
1284 *
1285 * @return - Success : 0
1286 * Failure : -EINVAL
1287 */
1288 int omap_modify_dma_chain_params(int chain_id,
1289 struct omap_dma_channel_params params)
1290 {
1291 int *channels;
1292 u32 i;
1293
1294 /* Check for input params */
1295 if (unlikely((chain_id < 0
1296 || chain_id >= dma_lch_count))) {
1297 printk(KERN_ERR "Invalid chain id\n");
1298 return -EINVAL;
1299 }
1300
1301 /* Check if the chain exists */
1302 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1303 printk(KERN_ERR "Chain doesn't exists\n");
1304 return -EINVAL;
1305 }
1306 channels = dma_linked_lch[chain_id].linked_dmach_q;
1307
1308 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1309 /*
1310 * Allowing client drivers to set common parameters now,
1311 * so that later only relevant (src_start, dest_start
1312 * and element count) can be set
1313 */
1314 omap_set_dma_params(channels[i], &params);
1315 }
1316
1317 return 0;
1318 }
1319 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1320
1321 /**
1322 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1323 *
1324 * @param chain_id
1325 *
1326 * @return - Success : 0
1327 * Failure : -EINVAL
1328 */
1329 int omap_free_dma_chain(int chain_id)
1330 {
1331 int *channels;
1332 u32 i;
1333
1334 /* Check for input params */
1335 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1336 printk(KERN_ERR "Invalid chain id\n");
1337 return -EINVAL;
1338 }
1339
1340 /* Check if the chain exists */
1341 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1342 printk(KERN_ERR "Chain doesn't exists\n");
1343 return -EINVAL;
1344 }
1345
1346 channels = dma_linked_lch[chain_id].linked_dmach_q;
1347 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1348 dma_chan[channels[i]].next_linked_ch = -1;
1349 dma_chan[channels[i]].prev_linked_ch = -1;
1350 dma_chan[channels[i]].chain_id = -1;
1351 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1352 omap_free_dma(channels[i]);
1353 }
1354
1355 kfree(channels);
1356
1357 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1358 dma_linked_lch[chain_id].chain_mode = -1;
1359 dma_linked_lch[chain_id].chain_state = -1;
1360
1361 return (0);
1362 }
1363 EXPORT_SYMBOL(omap_free_dma_chain);
1364
1365 /**
1366 * @brief omap_dma_chain_status - Check if the chain is in
1367 * active / inactive state.
1368 * @param chain_id
1369 *
1370 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1371 * Failure : -EINVAL
1372 */
1373 int omap_dma_chain_status(int chain_id)
1374 {
1375 /* Check for input params */
1376 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1377 printk(KERN_ERR "Invalid chain id\n");
1378 return -EINVAL;
1379 }
1380
1381 /* Check if the chain exists */
1382 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383 printk(KERN_ERR "Chain doesn't exists\n");
1384 return -EINVAL;
1385 }
1386 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1387 dma_linked_lch[chain_id].q_count);
1388
1389 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1390 return OMAP_DMA_CHAIN_INACTIVE;
1391
1392 return OMAP_DMA_CHAIN_ACTIVE;
1393 }
1394 EXPORT_SYMBOL(omap_dma_chain_status);
1395
1396 /**
1397 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1398 * set the params and start the transfer.
1399 *
1400 * @param chain_id
1401 * @param src_start - buffer start address
1402 * @param dest_start - Dest address
1403 * @param elem_count
1404 * @param frame_count
1405 * @param callbk_data - channel callback parameter data.
1406 *
1407 * @return - Success : 0
1408 * Failure: -EINVAL/-EBUSY
1409 */
1410 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1411 int elem_count, int frame_count, void *callbk_data)
1412 {
1413 int *channels;
1414 u32 l, lch;
1415 int start_dma = 0;
1416
1417 /*
1418 * if buffer size is less than 1 then there is
1419 * no use of starting the chain
1420 */
1421 if (elem_count < 1) {
1422 printk(KERN_ERR "Invalid buffer size\n");
1423 return -EINVAL;
1424 }
1425
1426 /* Check for input params */
1427 if (unlikely((chain_id < 0
1428 || chain_id >= dma_lch_count))) {
1429 printk(KERN_ERR "Invalid chain id\n");
1430 return -EINVAL;
1431 }
1432
1433 /* Check if the chain exists */
1434 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1435 printk(KERN_ERR "Chain doesn't exist\n");
1436 return -EINVAL;
1437 }
1438
1439 /* Check if all the channels in chain are in use */
1440 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1441 return -EBUSY;
1442
1443 /* Frame count may be negative in case of indexed transfers */
1444 channels = dma_linked_lch[chain_id].linked_dmach_q;
1445
1446 /* Get a free channel */
1447 lch = channels[dma_linked_lch[chain_id].q_tail];
1448
1449 /* Store the callback data */
1450 dma_chan[lch].data = callbk_data;
1451
1452 /* Increment the q_tail */
1453 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1454
1455 /* Set the params to the free channel */
1456 if (src_start != 0)
1457 dma_write(src_start, CSSA(lch));
1458 if (dest_start != 0)
1459 dma_write(dest_start, CDSA(lch));
1460
1461 /* Write the buffer size */
1462 dma_write(elem_count, CEN(lch));
1463 dma_write(frame_count, CFN(lch));
1464
1465 /*
1466 * If the chain is dynamically linked,
1467 * then we may have to start the chain if its not active
1468 */
1469 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1470
1471 /*
1472 * In Dynamic chain, if the chain is not started,
1473 * queue the channel
1474 */
1475 if (dma_linked_lch[chain_id].chain_state ==
1476 DMA_CHAIN_NOTSTARTED) {
1477 /* Enable the link in previous channel */
1478 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1479 DMA_CH_QUEUED)
1480 enable_lnk(dma_chan[lch].prev_linked_ch);
1481 dma_chan[lch].state = DMA_CH_QUEUED;
1482 }
1483
1484 /*
1485 * Chain is already started, make sure its active,
1486 * if not then start the chain
1487 */
1488 else {
1489 start_dma = 1;
1490
1491 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1492 DMA_CH_STARTED) {
1493 enable_lnk(dma_chan[lch].prev_linked_ch);
1494 dma_chan[lch].state = DMA_CH_QUEUED;
1495 start_dma = 0;
1496 if (0 == ((1 << 7) & dma_read(
1497 CCR(dma_chan[lch].prev_linked_ch)))) {
1498 disable_lnk(dma_chan[lch].
1499 prev_linked_ch);
1500 pr_debug("\n prev ch is stopped\n");
1501 start_dma = 1;
1502 }
1503 }
1504
1505 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1506 == DMA_CH_QUEUED) {
1507 enable_lnk(dma_chan[lch].prev_linked_ch);
1508 dma_chan[lch].state = DMA_CH_QUEUED;
1509 start_dma = 0;
1510 }
1511 omap_enable_channel_irq(lch);
1512
1513 l = dma_read(CCR(lch));
1514
1515 if ((0 == (l & (1 << 24))))
1516 l &= ~(1 << 25);
1517 else
1518 l |= (1 << 25);
1519 if (start_dma == 1) {
1520 if (0 == (l & (1 << 7))) {
1521 l |= (1 << 7);
1522 dma_chan[lch].state = DMA_CH_STARTED;
1523 pr_debug("starting %d\n", lch);
1524 dma_write(l, CCR(lch));
1525 } else
1526 start_dma = 0;
1527 } else {
1528 if (0 == (l & (1 << 7)))
1529 dma_write(l, CCR(lch));
1530 }
1531 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1532 }
1533 }
1534
1535 return 0;
1536 }
1537 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1538
1539 /**
1540 * @brief omap_start_dma_chain_transfers - Start the chain
1541 *
1542 * @param chain_id
1543 *
1544 * @return - Success : 0
1545 * Failure : -EINVAL/-EBUSY
1546 */
1547 int omap_start_dma_chain_transfers(int chain_id)
1548 {
1549 int *channels;
1550 u32 l, i;
1551
1552 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1553 printk(KERN_ERR "Invalid chain id\n");
1554 return -EINVAL;
1555 }
1556
1557 channels = dma_linked_lch[chain_id].linked_dmach_q;
1558
1559 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1560 printk(KERN_ERR "Chain is already started\n");
1561 return -EBUSY;
1562 }
1563
1564 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1565 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1566 i++) {
1567 enable_lnk(channels[i]);
1568 omap_enable_channel_irq(channels[i]);
1569 }
1570 } else {
1571 omap_enable_channel_irq(channels[0]);
1572 }
1573
1574 l = dma_read(CCR(channels[0]));
1575 l |= (1 << 7);
1576 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1577 dma_chan[channels[0]].state = DMA_CH_STARTED;
1578
1579 if ((0 == (l & (1 << 24))))
1580 l &= ~(1 << 25);
1581 else
1582 l |= (1 << 25);
1583 dma_write(l, CCR(channels[0]));
1584
1585 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1586
1587 return 0;
1588 }
1589 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1590
1591 /**
1592 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1593 *
1594 * @param chain_id
1595 *
1596 * @return - Success : 0
1597 * Failure : EINVAL
1598 */
1599 int omap_stop_dma_chain_transfers(int chain_id)
1600 {
1601 int *channels;
1602 u32 l, i;
1603 u32 sys_cf;
1604
1605 /* Check for input params */
1606 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1607 printk(KERN_ERR "Invalid chain id\n");
1608 return -EINVAL;
1609 }
1610
1611 /* Check if the chain exists */
1612 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1613 printk(KERN_ERR "Chain doesn't exists\n");
1614 return -EINVAL;
1615 }
1616 channels = dma_linked_lch[chain_id].linked_dmach_q;
1617
1618 /*
1619 * DMA Errata:
1620 * Special programming model needed to disable DMA before end of block
1621 */
1622 sys_cf = dma_read(OCP_SYSCONFIG);
1623 l = sys_cf;
1624 /* Middle mode reg set no Standby */
1625 l &= ~((1 << 12)|(1 << 13));
1626 dma_write(l, OCP_SYSCONFIG);
1627
1628 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1629
1630 /* Stop the Channel transmission */
1631 l = dma_read(CCR(channels[i]));
1632 l &= ~(1 << 7);
1633 dma_write(l, CCR(channels[i]));
1634
1635 /* Disable the link in all the channels */
1636 disable_lnk(channels[i]);
1637 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1638
1639 }
1640 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1641
1642 /* Reset the Queue pointers */
1643 OMAP_DMA_CHAIN_QINIT(chain_id);
1644
1645 /* Errata - put in the old value */
1646 dma_write(sys_cf, OCP_SYSCONFIG);
1647
1648 return 0;
1649 }
1650 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1651
1652 /* Get the index of the ongoing DMA in chain */
1653 /**
1654 * @brief omap_get_dma_chain_index - Get the element and frame index
1655 * of the ongoing DMA in chain
1656 *
1657 * @param chain_id
1658 * @param ei - Element index
1659 * @param fi - Frame index
1660 *
1661 * @return - Success : 0
1662 * Failure : -EINVAL
1663 */
1664 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1665 {
1666 int lch;
1667 int *channels;
1668
1669 /* Check for input params */
1670 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1671 printk(KERN_ERR "Invalid chain id\n");
1672 return -EINVAL;
1673 }
1674
1675 /* Check if the chain exists */
1676 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1677 printk(KERN_ERR "Chain doesn't exists\n");
1678 return -EINVAL;
1679 }
1680 if ((!ei) || (!fi))
1681 return -EINVAL;
1682
1683 channels = dma_linked_lch[chain_id].linked_dmach_q;
1684
1685 /* Get the current channel */
1686 lch = channels[dma_linked_lch[chain_id].q_head];
1687
1688 *ei = dma_read(CCEN(lch));
1689 *fi = dma_read(CCFN(lch));
1690
1691 return 0;
1692 }
1693 EXPORT_SYMBOL(omap_get_dma_chain_index);
1694
1695 /**
1696 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1697 * ongoing DMA in chain
1698 *
1699 * @param chain_id
1700 *
1701 * @return - Success : Destination position
1702 * Failure : -EINVAL
1703 */
1704 int omap_get_dma_chain_dst_pos(int chain_id)
1705 {
1706 int lch;
1707 int *channels;
1708
1709 /* Check for input params */
1710 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1711 printk(KERN_ERR "Invalid chain id\n");
1712 return -EINVAL;
1713 }
1714
1715 /* Check if the chain exists */
1716 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1717 printk(KERN_ERR "Chain doesn't exists\n");
1718 return -EINVAL;
1719 }
1720
1721 channels = dma_linked_lch[chain_id].linked_dmach_q;
1722
1723 /* Get the current channel */
1724 lch = channels[dma_linked_lch[chain_id].q_head];
1725
1726 return dma_read(CDAC(lch));
1727 }
1728 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1729
1730 /**
1731 * @brief omap_get_dma_chain_src_pos - Get the source position
1732 * of the ongoing DMA in chain
1733 * @param chain_id
1734 *
1735 * @return - Success : Destination position
1736 * Failure : -EINVAL
1737 */
1738 int omap_get_dma_chain_src_pos(int chain_id)
1739 {
1740 int lch;
1741 int *channels;
1742
1743 /* Check for input params */
1744 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1745 printk(KERN_ERR "Invalid chain id\n");
1746 return -EINVAL;
1747 }
1748
1749 /* Check if the chain exists */
1750 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1751 printk(KERN_ERR "Chain doesn't exists\n");
1752 return -EINVAL;
1753 }
1754
1755 channels = dma_linked_lch[chain_id].linked_dmach_q;
1756
1757 /* Get the current channel */
1758 lch = channels[dma_linked_lch[chain_id].q_head];
1759
1760 return dma_read(CSAC(lch));
1761 }
1762 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1763 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1764
1765 /*----------------------------------------------------------------------------*/
1766
1767 #ifdef CONFIG_ARCH_OMAP1
1768
1769 static int omap1_dma_handle_ch(int ch)
1770 {
1771 u32 csr;
1772
1773 if (enable_1510_mode && ch >= 6) {
1774 csr = dma_chan[ch].saved_csr;
1775 dma_chan[ch].saved_csr = 0;
1776 } else
1777 csr = dma_read(CSR(ch));
1778 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1779 dma_chan[ch + 6].saved_csr = csr >> 7;
1780 csr &= 0x7f;
1781 }
1782 if ((csr & 0x3f) == 0)
1783 return 0;
1784 if (unlikely(dma_chan[ch].dev_id == -1)) {
1785 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1786 "%d (CSR %04x)\n", ch, csr);
1787 return 0;
1788 }
1789 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1790 printk(KERN_WARNING "DMA timeout with device %d\n",
1791 dma_chan[ch].dev_id);
1792 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1793 printk(KERN_WARNING "DMA synchronization event drop occurred "
1794 "with device %d\n", dma_chan[ch].dev_id);
1795 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1796 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1797 if (likely(dma_chan[ch].callback != NULL))
1798 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1799
1800 return 1;
1801 }
1802
1803 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1804 {
1805 int ch = ((int) dev_id) - 1;
1806 int handled = 0;
1807
1808 for (;;) {
1809 int handled_now = 0;
1810
1811 handled_now += omap1_dma_handle_ch(ch);
1812 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1813 handled_now += omap1_dma_handle_ch(ch + 6);
1814 if (!handled_now)
1815 break;
1816 handled += handled_now;
1817 }
1818
1819 return handled ? IRQ_HANDLED : IRQ_NONE;
1820 }
1821
1822 #else
1823 #define omap1_dma_irq_handler NULL
1824 #endif
1825
1826 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1827
1828 static int omap2_dma_handle_ch(int ch)
1829 {
1830 u32 status = dma_read(CSR(ch));
1831
1832 if (!status) {
1833 if (printk_ratelimit())
1834 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1835 ch);
1836 dma_write(1 << ch, IRQSTATUS_L0);
1837 return 0;
1838 }
1839 if (unlikely(dma_chan[ch].dev_id == -1)) {
1840 if (printk_ratelimit())
1841 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1842 "channel %d\n", status, ch);
1843 return 0;
1844 }
1845 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1846 printk(KERN_INFO
1847 "DMA synchronization event drop occurred with device "
1848 "%d\n", dma_chan[ch].dev_id);
1849 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1850 printk(KERN_INFO "DMA transaction error with device %d\n",
1851 dma_chan[ch].dev_id);
1852 if (cpu_class_is_omap2()) {
1853 /* Errata: sDMA Channel is not disabled
1854 * after a transaction error. So we explicitely
1855 * disable the channel
1856 */
1857 u32 ccr;
1858
1859 ccr = dma_read(CCR(ch));
1860 ccr &= ~OMAP_DMA_CCR_EN;
1861 dma_write(ccr, CCR(ch));
1862 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1863 }
1864 }
1865 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1866 printk(KERN_INFO "DMA secure error with device %d\n",
1867 dma_chan[ch].dev_id);
1868 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1869 printk(KERN_INFO "DMA misaligned error with device %d\n",
1870 dma_chan[ch].dev_id);
1871
1872 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1873 dma_write(1 << ch, IRQSTATUS_L0);
1874
1875 /* If the ch is not chained then chain_id will be -1 */
1876 if (dma_chan[ch].chain_id != -1) {
1877 int chain_id = dma_chan[ch].chain_id;
1878 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1879 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1880 dma_chan[dma_chan[ch].next_linked_ch].state =
1881 DMA_CH_STARTED;
1882 if (dma_linked_lch[chain_id].chain_mode ==
1883 OMAP_DMA_DYNAMIC_CHAIN)
1884 disable_lnk(ch);
1885
1886 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1887 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1888
1889 status = dma_read(CSR(ch));
1890 }
1891
1892 dma_write(status, CSR(ch));
1893
1894 if (likely(dma_chan[ch].callback != NULL))
1895 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1896
1897 return 0;
1898 }
1899
1900 /* STATUS register count is from 1-32 while our is 0-31 */
1901 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1902 {
1903 u32 val, enable_reg;
1904 int i;
1905
1906 val = dma_read(IRQSTATUS_L0);
1907 if (val == 0) {
1908 if (printk_ratelimit())
1909 printk(KERN_WARNING "Spurious DMA IRQ\n");
1910 return IRQ_HANDLED;
1911 }
1912 enable_reg = dma_read(IRQENABLE_L0);
1913 val &= enable_reg; /* Dispatch only relevant interrupts */
1914 for (i = 0; i < dma_lch_count && val != 0; i++) {
1915 if (val & 1)
1916 omap2_dma_handle_ch(i);
1917 val >>= 1;
1918 }
1919
1920 return IRQ_HANDLED;
1921 }
1922
1923 static struct irqaction omap24xx_dma_irq = {
1924 .name = "DMA",
1925 .handler = omap2_dma_irq_handler,
1926 .flags = IRQF_DISABLED
1927 };
1928
1929 #else
1930 static struct irqaction omap24xx_dma_irq;
1931 #endif
1932
1933 /*----------------------------------------------------------------------------*/
1934
1935 static struct lcd_dma_info {
1936 spinlock_t lock;
1937 int reserved;
1938 void (*callback)(u16 status, void *data);
1939 void *cb_data;
1940
1941 int active;
1942 unsigned long addr, size;
1943 int rotate, data_type, xres, yres;
1944 int vxres;
1945 int mirror;
1946 int xscale, yscale;
1947 int ext_ctrl;
1948 int src_port;
1949 int single_transfer;
1950 } lcd_dma;
1951
1952 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1953 int data_type)
1954 {
1955 lcd_dma.addr = addr;
1956 lcd_dma.data_type = data_type;
1957 lcd_dma.xres = fb_xres;
1958 lcd_dma.yres = fb_yres;
1959 }
1960 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1961
1962 void omap_set_lcd_dma_src_port(int port)
1963 {
1964 lcd_dma.src_port = port;
1965 }
1966
1967 void omap_set_lcd_dma_ext_controller(int external)
1968 {
1969 lcd_dma.ext_ctrl = external;
1970 }
1971 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1972
1973 void omap_set_lcd_dma_single_transfer(int single)
1974 {
1975 lcd_dma.single_transfer = single;
1976 }
1977 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1978
1979 void omap_set_lcd_dma_b1_rotation(int rotate)
1980 {
1981 if (omap_dma_in_1510_mode()) {
1982 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1983 BUG();
1984 return;
1985 }
1986 lcd_dma.rotate = rotate;
1987 }
1988 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1989
1990 void omap_set_lcd_dma_b1_mirror(int mirror)
1991 {
1992 if (omap_dma_in_1510_mode()) {
1993 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1994 BUG();
1995 }
1996 lcd_dma.mirror = mirror;
1997 }
1998 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1999
2000 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2001 {
2002 if (omap_dma_in_1510_mode()) {
2003 printk(KERN_ERR "DMA virtual resulotion is not supported "
2004 "in 1510 mode\n");
2005 BUG();
2006 }
2007 lcd_dma.vxres = vxres;
2008 }
2009 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2010
2011 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2012 {
2013 if (omap_dma_in_1510_mode()) {
2014 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2015 BUG();
2016 }
2017 lcd_dma.xscale = xscale;
2018 lcd_dma.yscale = yscale;
2019 }
2020 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2021
2022 static void set_b1_regs(void)
2023 {
2024 unsigned long top, bottom;
2025 int es;
2026 u16 w;
2027 unsigned long en, fn;
2028 long ei, fi;
2029 unsigned long vxres;
2030 unsigned int xscale, yscale;
2031
2032 switch (lcd_dma.data_type) {
2033 case OMAP_DMA_DATA_TYPE_S8:
2034 es = 1;
2035 break;
2036 case OMAP_DMA_DATA_TYPE_S16:
2037 es = 2;
2038 break;
2039 case OMAP_DMA_DATA_TYPE_S32:
2040 es = 4;
2041 break;
2042 default:
2043 BUG();
2044 return;
2045 }
2046
2047 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2048 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2049 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2050 BUG_ON(vxres < lcd_dma.xres);
2051
2052 #define PIXADDR(x, y) (lcd_dma.addr + \
2053 ((y) * vxres * yscale + (x) * xscale) * es)
2054 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2055
2056 switch (lcd_dma.rotate) {
2057 case 0:
2058 if (!lcd_dma.mirror) {
2059 top = PIXADDR(0, 0);
2060 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2061 /* 1510 DMA requires the bottom address to be 2 more
2062 * than the actual last memory access location. */
2063 if (omap_dma_in_1510_mode() &&
2064 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2065 bottom += 2;
2066 ei = PIXSTEP(0, 0, 1, 0);
2067 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2068 } else {
2069 top = PIXADDR(lcd_dma.xres - 1, 0);
2070 bottom = PIXADDR(0, lcd_dma.yres - 1);
2071 ei = PIXSTEP(1, 0, 0, 0);
2072 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2073 }
2074 en = lcd_dma.xres;
2075 fn = lcd_dma.yres;
2076 break;
2077 case 90:
2078 if (!lcd_dma.mirror) {
2079 top = PIXADDR(0, lcd_dma.yres - 1);
2080 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2081 ei = PIXSTEP(0, 1, 0, 0);
2082 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2083 } else {
2084 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2085 bottom = PIXADDR(0, 0);
2086 ei = PIXSTEP(0, 1, 0, 0);
2087 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2088 }
2089 en = lcd_dma.yres;
2090 fn = lcd_dma.xres;
2091 break;
2092 case 180:
2093 if (!lcd_dma.mirror) {
2094 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2095 bottom = PIXADDR(0, 0);
2096 ei = PIXSTEP(1, 0, 0, 0);
2097 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2098 } else {
2099 top = PIXADDR(0, lcd_dma.yres - 1);
2100 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2101 ei = PIXSTEP(0, 0, 1, 0);
2102 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2103 }
2104 en = lcd_dma.xres;
2105 fn = lcd_dma.yres;
2106 break;
2107 case 270:
2108 if (!lcd_dma.mirror) {
2109 top = PIXADDR(lcd_dma.xres - 1, 0);
2110 bottom = PIXADDR(0, lcd_dma.yres - 1);
2111 ei = PIXSTEP(0, 0, 0, 1);
2112 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2113 } else {
2114 top = PIXADDR(0, 0);
2115 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2116 ei = PIXSTEP(0, 0, 0, 1);
2117 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2118 }
2119 en = lcd_dma.yres;
2120 fn = lcd_dma.xres;
2121 break;
2122 default:
2123 BUG();
2124 return; /* Suppress warning about uninitialized vars */
2125 }
2126
2127 if (omap_dma_in_1510_mode()) {
2128 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2129 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2130 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2131 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2132
2133 return;
2134 }
2135
2136 /* 1610 regs */
2137 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2138 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2139 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2140 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2141
2142 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2143 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2144
2145 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2146 w &= ~0x03;
2147 w |= lcd_dma.data_type;
2148 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2149
2150 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2151 /* Always set the source port as SDRAM for now*/
2152 w &= ~(0x03 << 6);
2153 if (lcd_dma.callback != NULL)
2154 w |= 1 << 1; /* Block interrupt enable */
2155 else
2156 w &= ~(1 << 1);
2157 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2158
2159 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2160 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2161 return;
2162
2163 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2164 /* Set the double-indexed addressing mode */
2165 w |= (0x03 << 12);
2166 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2167
2168 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2169 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2170 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2171 }
2172
2173 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2174 {
2175 u16 w;
2176
2177 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2178 if (unlikely(!(w & (1 << 3)))) {
2179 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2180 return IRQ_NONE;
2181 }
2182 /* Ack the IRQ */
2183 w |= (1 << 3);
2184 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2185 lcd_dma.active = 0;
2186 if (lcd_dma.callback != NULL)
2187 lcd_dma.callback(w, lcd_dma.cb_data);
2188
2189 return IRQ_HANDLED;
2190 }
2191
2192 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2193 void *data)
2194 {
2195 spin_lock_irq(&lcd_dma.lock);
2196 if (lcd_dma.reserved) {
2197 spin_unlock_irq(&lcd_dma.lock);
2198 printk(KERN_ERR "LCD DMA channel already reserved\n");
2199 BUG();
2200 return -EBUSY;
2201 }
2202 lcd_dma.reserved = 1;
2203 spin_unlock_irq(&lcd_dma.lock);
2204 lcd_dma.callback = callback;
2205 lcd_dma.cb_data = data;
2206 lcd_dma.active = 0;
2207 lcd_dma.single_transfer = 0;
2208 lcd_dma.rotate = 0;
2209 lcd_dma.vxres = 0;
2210 lcd_dma.mirror = 0;
2211 lcd_dma.xscale = 0;
2212 lcd_dma.yscale = 0;
2213 lcd_dma.ext_ctrl = 0;
2214 lcd_dma.src_port = 0;
2215
2216 return 0;
2217 }
2218 EXPORT_SYMBOL(omap_request_lcd_dma);
2219
2220 void omap_free_lcd_dma(void)
2221 {
2222 spin_lock(&lcd_dma.lock);
2223 if (!lcd_dma.reserved) {
2224 spin_unlock(&lcd_dma.lock);
2225 printk(KERN_ERR "LCD DMA is not reserved\n");
2226 BUG();
2227 return;
2228 }
2229 if (!enable_1510_mode)
2230 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2231 OMAP1610_DMA_LCD_CCR);
2232 lcd_dma.reserved = 0;
2233 spin_unlock(&lcd_dma.lock);
2234 }
2235 EXPORT_SYMBOL(omap_free_lcd_dma);
2236
2237 void omap_enable_lcd_dma(void)
2238 {
2239 u16 w;
2240
2241 /*
2242 * Set the Enable bit only if an external controller is
2243 * connected. Otherwise the OMAP internal controller will
2244 * start the transfer when it gets enabled.
2245 */
2246 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2247 return;
2248
2249 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2250 w |= 1 << 8;
2251 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2252
2253 lcd_dma.active = 1;
2254
2255 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2256 w |= 1 << 7;
2257 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2258 }
2259 EXPORT_SYMBOL(omap_enable_lcd_dma);
2260
2261 void omap_setup_lcd_dma(void)
2262 {
2263 BUG_ON(lcd_dma.active);
2264 if (!enable_1510_mode) {
2265 /* Set some reasonable defaults */
2266 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2267 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2268 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2269 }
2270 set_b1_regs();
2271 if (!enable_1510_mode) {
2272 u16 w;
2273
2274 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2275 /*
2276 * If DMA was already active set the end_prog bit to have
2277 * the programmed register set loaded into the active
2278 * register set.
2279 */
2280 w |= 1 << 11; /* End_prog */
2281 if (!lcd_dma.single_transfer)
2282 w |= (3 << 8); /* Auto_init, repeat */
2283 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2284 }
2285 }
2286 EXPORT_SYMBOL(omap_setup_lcd_dma);
2287
2288 void omap_stop_lcd_dma(void)
2289 {
2290 u16 w;
2291
2292 lcd_dma.active = 0;
2293 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2294 return;
2295
2296 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2297 w &= ~(1 << 7);
2298 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2299
2300 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2301 w &= ~(1 << 8);
2302 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2303 }
2304 EXPORT_SYMBOL(omap_stop_lcd_dma);
2305
2306 /*----------------------------------------------------------------------------*/
2307
2308 static int __init omap_init_dma(void)
2309 {
2310 int ch, r;
2311
2312 if (cpu_class_is_omap1()) {
2313 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2314 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2315 } else if (cpu_is_omap24xx()) {
2316 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2317 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2318 } else if (cpu_is_omap34xx()) {
2319 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2320 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2321 } else {
2322 pr_err("DMA init failed for unsupported omap\n");
2323 return -ENODEV;
2324 }
2325
2326 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2327 && (omap_dma_reserve_channels <= dma_lch_count))
2328 dma_lch_count = omap_dma_reserve_channels;
2329
2330 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2331 GFP_KERNEL);
2332 if (!dma_chan)
2333 return -ENOMEM;
2334
2335 if (cpu_class_is_omap2()) {
2336 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2337 dma_lch_count, GFP_KERNEL);
2338 if (!dma_linked_lch) {
2339 kfree(dma_chan);
2340 return -ENOMEM;
2341 }
2342 }
2343
2344 if (cpu_is_omap15xx()) {
2345 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2346 dma_chan_count = 9;
2347 enable_1510_mode = 1;
2348 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2349 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2350 dma_read(HW_ID));
2351 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2352 (dma_read(CAPS_0_U) << 16) |
2353 dma_read(CAPS_0_L),
2354 (dma_read(CAPS_1_U) << 16) |
2355 dma_read(CAPS_1_L),
2356 dma_read(CAPS_2), dma_read(CAPS_3),
2357 dma_read(CAPS_4));
2358 if (!enable_1510_mode) {
2359 u16 w;
2360
2361 /* Disable OMAP 3.0/3.1 compatibility mode. */
2362 w = dma_read(GSCR);
2363 w |= 1 << 3;
2364 dma_write(w, GSCR);
2365 dma_chan_count = 16;
2366 } else
2367 dma_chan_count = 9;
2368 if (cpu_is_omap16xx()) {
2369 u16 w;
2370
2371 /* this would prevent OMAP sleep */
2372 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2373 w &= ~(1 << 8);
2374 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2375 }
2376 } else if (cpu_class_is_omap2()) {
2377 u8 revision = dma_read(REVISION) & 0xff;
2378 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2379 revision >> 4, revision & 0xf);
2380 dma_chan_count = dma_lch_count;
2381 } else {
2382 dma_chan_count = 0;
2383 return 0;
2384 }
2385
2386 spin_lock_init(&lcd_dma.lock);
2387 spin_lock_init(&dma_chan_lock);
2388
2389 for (ch = 0; ch < dma_chan_count; ch++) {
2390 omap_clear_dma(ch);
2391 dma_chan[ch].dev_id = -1;
2392 dma_chan[ch].next_lch = -1;
2393
2394 if (ch >= 6 && enable_1510_mode)
2395 continue;
2396
2397 if (cpu_class_is_omap1()) {
2398 /*
2399 * request_irq() doesn't like dev_id (ie. ch) being
2400 * zero, so we have to kludge around this.
2401 */
2402 r = request_irq(omap1_dma_irq[ch],
2403 omap1_dma_irq_handler, 0, "DMA",
2404 (void *) (ch + 1));
2405 if (r != 0) {
2406 int i;
2407
2408 printk(KERN_ERR "unable to request IRQ %d "
2409 "for DMA (error %d)\n",
2410 omap1_dma_irq[ch], r);
2411 for (i = 0; i < ch; i++)
2412 free_irq(omap1_dma_irq[i],
2413 (void *) (i + 1));
2414 return r;
2415 }
2416 }
2417 }
2418
2419 if (cpu_is_omap2430() || cpu_is_omap34xx())
2420 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2421 DMA_DEFAULT_FIFO_DEPTH, 0);
2422
2423 if (cpu_class_is_omap2())
2424 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2425
2426 /* FIXME: Update LCD DMA to work on 24xx */
2427 if (cpu_class_is_omap1()) {
2428 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2429 "LCD DMA", NULL);
2430 if (r != 0) {
2431 int i;
2432
2433 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2434 "(error %d)\n", r);
2435 for (i = 0; i < dma_chan_count; i++)
2436 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2437 return r;
2438 }
2439 }
2440
2441 return 0;
2442 }
2443
2444 arch_initcall(omap_init_dma);
2445
2446 /*
2447 * Reserve the omap SDMA channels using cmdline bootarg
2448 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2449 */
2450 static int __init omap_dma_cmdline_reserve_ch(char *str)
2451 {
2452 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2453 omap_dma_reserve_channels = 0;
2454 return 1;
2455 }
2456
2457 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2458
2459
Linux kernel - Deliverables
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