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[ARM] replace remaining __FUNCTION__ occurrences
[deliverable/linux.git] / arch / arm / plat-omap / dmtimer.c
1 /*
2 * linux/arch/arm/plat-omap/dmtimer.c
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/errno.h>
32 #include <linux/list.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <asm/hardware.h>
36 #include <asm/arch/dmtimer.h>
37 #include <asm/io.h>
38 #include <asm/arch/irqs.h>
39
40 /* register offsets */
41 #define OMAP_TIMER_ID_REG 0x00
42 #define OMAP_TIMER_OCP_CFG_REG 0x10
43 #define OMAP_TIMER_SYS_STAT_REG 0x14
44 #define OMAP_TIMER_STAT_REG 0x18
45 #define OMAP_TIMER_INT_EN_REG 0x1c
46 #define OMAP_TIMER_WAKEUP_EN_REG 0x20
47 #define OMAP_TIMER_CTRL_REG 0x24
48 #define OMAP_TIMER_COUNTER_REG 0x28
49 #define OMAP_TIMER_LOAD_REG 0x2c
50 #define OMAP_TIMER_TRIGGER_REG 0x30
51 #define OMAP_TIMER_WRITE_PEND_REG 0x34
52 #define OMAP_TIMER_MATCH_REG 0x38
53 #define OMAP_TIMER_CAPTURE_REG 0x3c
54 #define OMAP_TIMER_IF_CTRL_REG 0x40
55
56 /* timer control reg bits */
57 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
58 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
59 #define OMAP_TIMER_CTRL_PT (1 << 12)
60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
63 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
64 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
65 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
66 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
67 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
68 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
69
70 struct omap_dm_timer {
71 unsigned long phys_base;
72 int irq;
73 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
74 struct clk *iclk, *fclk;
75 #endif
76 void __iomem *io_base;
77 unsigned reserved:1;
78 unsigned enabled:1;
79 };
80
81 #ifdef CONFIG_ARCH_OMAP1
82
83 #define omap_dm_clk_enable(x)
84 #define omap_dm_clk_disable(x)
85 #define omap2_dm_timers NULL
86 #define omap2_dm_source_names NULL
87 #define omap2_dm_source_clocks NULL
88 #define omap3_dm_timers NULL
89 #define omap3_dm_source_names NULL
90 #define omap3_dm_source_clocks NULL
91
92 static struct omap_dm_timer omap1_dm_timers[] = {
93 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
94 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
95 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
96 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
97 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
98 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
99 { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
100 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
101 };
102
103 static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
104
105 #elif defined(CONFIG_ARCH_OMAP2)
106
107 #define omap_dm_clk_enable(x) clk_enable(x)
108 #define omap_dm_clk_disable(x) clk_disable(x)
109 #define omap1_dm_timers NULL
110 #define omap3_dm_timers NULL
111 #define omap3_dm_source_names NULL
112 #define omap3_dm_source_clocks NULL
113
114 static struct omap_dm_timer omap2_dm_timers[] = {
115 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
116 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
117 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
118 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
119 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
120 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
121 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
122 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
123 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
124 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
125 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
126 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
127 };
128
129 static const char *omap2_dm_source_names[] __initdata = {
130 "sys_ck",
131 "func_32k_ck",
132 "alt_ck",
133 NULL
134 };
135
136 static struct clk **omap2_dm_source_clocks[3];
137 static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
138
139 #elif defined(CONFIG_ARCH_OMAP3)
140
141 #define omap_dm_clk_enable(x) clk_enable(x)
142 #define omap_dm_clk_disable(x) clk_disable(x)
143 #define omap1_dm_timers NULL
144 #define omap2_dm_timers NULL
145 #define omap2_dm_source_names NULL
146 #define omap2_dm_source_clocks NULL
147
148 static struct omap_dm_timer omap3_dm_timers[] = {
149 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
150 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
151 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
152 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
153 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
154 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
155 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
156 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
157 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
158 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
159 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
160 { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
161 };
162
163 static const char *omap3_dm_source_names[] __initdata = {
164 "sys_ck",
165 "omap_32k_fck",
166 NULL
167 };
168
169 static struct clk **omap3_dm_source_clocks[2];
170 static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
171
172 #else
173
174 #error OMAP architecture not supported!
175
176 #endif
177
178 static struct omap_dm_timer *dm_timers;
179 static char **dm_source_names;
180 static struct clk **dm_source_clocks;
181
182 static spinlock_t dm_timer_lock;
183
184 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
185 {
186 return readl(timer->io_base + reg);
187 }
188
189 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
190 {
191 writel(value, timer->io_base + reg);
192 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
193 ;
194 }
195
196 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
197 {
198 int c;
199
200 c = 0;
201 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
202 c++;
203 if (c > 100000) {
204 printk(KERN_ERR "Timer failed to reset\n");
205 return;
206 }
207 }
208 }
209
210 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
211 {
212 u32 l;
213
214 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
215 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
216 omap_dm_timer_wait_for_reset(timer);
217 }
218 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
219
220 /* Set to smart-idle mode */
221 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
222 l |= 0x02 << 3;
223
224 if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
225 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
226 l |= 1 << 2;
227 /* Non-posted mode */
228 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
229 }
230 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
231 }
232
233 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
234 {
235 omap_dm_timer_enable(timer);
236 omap_dm_timer_reset(timer);
237 }
238
239 struct omap_dm_timer *omap_dm_timer_request(void)
240 {
241 struct omap_dm_timer *timer = NULL;
242 unsigned long flags;
243 int i;
244
245 spin_lock_irqsave(&dm_timer_lock, flags);
246 for (i = 0; i < dm_timer_count; i++) {
247 if (dm_timers[i].reserved)
248 continue;
249
250 timer = &dm_timers[i];
251 timer->reserved = 1;
252 break;
253 }
254 spin_unlock_irqrestore(&dm_timer_lock, flags);
255
256 if (timer != NULL)
257 omap_dm_timer_prepare(timer);
258
259 return timer;
260 }
261
262 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
263 {
264 struct omap_dm_timer *timer;
265 unsigned long flags;
266
267 spin_lock_irqsave(&dm_timer_lock, flags);
268 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
269 spin_unlock_irqrestore(&dm_timer_lock, flags);
270 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
271 __FILE__, __LINE__, __func__, id);
272 dump_stack();
273 return NULL;
274 }
275
276 timer = &dm_timers[id-1];
277 timer->reserved = 1;
278 spin_unlock_irqrestore(&dm_timer_lock, flags);
279
280 omap_dm_timer_prepare(timer);
281
282 return timer;
283 }
284
285 void omap_dm_timer_free(struct omap_dm_timer *timer)
286 {
287 omap_dm_timer_enable(timer);
288 omap_dm_timer_reset(timer);
289 omap_dm_timer_disable(timer);
290
291 WARN_ON(!timer->reserved);
292 timer->reserved = 0;
293 }
294
295 void omap_dm_timer_enable(struct omap_dm_timer *timer)
296 {
297 if (timer->enabled)
298 return;
299
300 omap_dm_clk_enable(timer->fclk);
301 omap_dm_clk_enable(timer->iclk);
302
303 timer->enabled = 1;
304 }
305
306 void omap_dm_timer_disable(struct omap_dm_timer *timer)
307 {
308 if (!timer->enabled)
309 return;
310
311 omap_dm_clk_disable(timer->iclk);
312 omap_dm_clk_disable(timer->fclk);
313
314 timer->enabled = 0;
315 }
316
317 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
318 {
319 return timer->irq;
320 }
321
322 #if defined(CONFIG_ARCH_OMAP1)
323
324 /**
325 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
326 * @inputmask: current value of idlect mask
327 */
328 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
329 {
330 int i;
331
332 /* If ARMXOR cannot be idled this function call is unnecessary */
333 if (!(inputmask & (1 << 1)))
334 return inputmask;
335
336 /* If any active timer is using ARMXOR return modified mask */
337 for (i = 0; i < dm_timer_count; i++) {
338 u32 l;
339
340 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
341 if (l & OMAP_TIMER_CTRL_ST) {
342 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
343 inputmask &= ~(1 << 1);
344 else
345 inputmask &= ~(1 << 2);
346 }
347 }
348
349 return inputmask;
350 }
351
352 #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
353
354 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
355 {
356 return timer->fclk;
357 }
358
359 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
360 {
361 BUG();
362
363 return 0;
364 }
365
366 #endif
367
368 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
369 {
370 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
371 }
372
373 void omap_dm_timer_start(struct omap_dm_timer *timer)
374 {
375 u32 l;
376
377 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
378 if (!(l & OMAP_TIMER_CTRL_ST)) {
379 l |= OMAP_TIMER_CTRL_ST;
380 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
381 }
382 }
383
384 void omap_dm_timer_stop(struct omap_dm_timer *timer)
385 {
386 u32 l;
387
388 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
389 if (l & OMAP_TIMER_CTRL_ST) {
390 l &= ~0x1;
391 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
392 }
393 }
394
395 #ifdef CONFIG_ARCH_OMAP1
396
397 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
398 {
399 int n = (timer - dm_timers) << 1;
400 u32 l;
401
402 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
403 l |= source << n;
404 omap_writel(l, MOD_CONF_CTRL_1);
405 }
406
407 #else
408
409 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
410 {
411 if (source < 0 || source >= 3)
412 return;
413
414 clk_disable(timer->fclk);
415 clk_set_parent(timer->fclk, dm_source_clocks[source]);
416 clk_enable(timer->fclk);
417
418 /* When the functional clock disappears, too quick writes seem to
419 * cause an abort. */
420 __delay(150000);
421 }
422
423 #endif
424
425 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
426 unsigned int load)
427 {
428 u32 l;
429
430 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
431 if (autoreload)
432 l |= OMAP_TIMER_CTRL_AR;
433 else
434 l &= ~OMAP_TIMER_CTRL_AR;
435 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
436 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
437 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
438 }
439
440 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
441 unsigned int match)
442 {
443 u32 l;
444
445 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
446 if (enable)
447 l |= OMAP_TIMER_CTRL_CE;
448 else
449 l &= ~OMAP_TIMER_CTRL_CE;
450 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
451 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
452 }
453
454
455 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
456 int toggle, int trigger)
457 {
458 u32 l;
459
460 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
461 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
462 OMAP_TIMER_CTRL_PT | (0x03 << 10));
463 if (def_on)
464 l |= OMAP_TIMER_CTRL_SCPWM;
465 if (toggle)
466 l |= OMAP_TIMER_CTRL_PT;
467 l |= trigger << 10;
468 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
469 }
470
471 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
472 {
473 u32 l;
474
475 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
476 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
477 if (prescaler >= 0x00 && prescaler <= 0x07) {
478 l |= OMAP_TIMER_CTRL_PRE;
479 l |= prescaler << 2;
480 }
481 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
482 }
483
484 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
485 unsigned int value)
486 {
487 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
488 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
489 }
490
491 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
492 {
493 unsigned int l;
494
495 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
496
497 return l;
498 }
499
500 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
501 {
502 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
503 }
504
505 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
506 {
507 unsigned int l;
508
509 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
510
511 return l;
512 }
513
514 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
515 {
516 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
517 }
518
519 int omap_dm_timers_active(void)
520 {
521 int i;
522
523 for (i = 0; i < dm_timer_count; i++) {
524 struct omap_dm_timer *timer;
525
526 timer = &dm_timers[i];
527
528 if (!timer->enabled)
529 continue;
530
531 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
532 OMAP_TIMER_CTRL_ST) {
533 return 1;
534 }
535 }
536 return 0;
537 }
538
539 int __init omap_dm_timer_init(void)
540 {
541 struct omap_dm_timer *timer;
542 int i;
543
544 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
545 return -ENODEV;
546
547 spin_lock_init(&dm_timer_lock);
548
549 if (cpu_class_is_omap1())
550 dm_timers = omap1_dm_timers;
551 else if (cpu_is_omap24xx()) {
552 dm_timers = omap2_dm_timers;
553 dm_source_names = (char **)omap2_dm_source_names;
554 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
555 } else if (cpu_is_omap34xx()) {
556 dm_timers = omap3_dm_timers;
557 dm_source_names = (char **)omap3_dm_source_names;
558 dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
559 }
560
561 if (cpu_class_is_omap2())
562 for (i = 0; dm_source_names[i] != NULL; i++)
563 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
564
565 if (cpu_is_omap243x())
566 dm_timers[0].phys_base = 0x49018000;
567
568 for (i = 0; i < dm_timer_count; i++) {
569 timer = &dm_timers[i];
570 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
571 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
572 if (cpu_class_is_omap2()) {
573 char clk_name[16];
574 sprintf(clk_name, "gpt%d_ick", i + 1);
575 timer->iclk = clk_get(NULL, clk_name);
576 sprintf(clk_name, "gpt%d_fck", i + 1);
577 timer->fclk = clk_get(NULL, clk_name);
578 }
579 #endif
580 }
581
582 return 0;
583 }
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