arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * dmtimer adaptation to platform_driver.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * OMAP2 support by Juha Yrjola
  14  * API improvements and OMAP2 clock framework support by Timo Teras
  15  *
  16  * Copyright (C) 2009 Texas Instruments
  17  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  18  *
  19  * This program is free software; you can redistribute it and/or modify it
  20  * under the terms of the GNU General Public License as published by the
  21  * Free Software Foundation; either version 2 of the License, or (at your
  22  * option) any later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  27  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the  GNU General Public License along
  34  * with this program; if not, write  to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/clk.h>
  39 #include <linux/module.h>
  40 #include <linux/io.h>
  41 #include <linux/device.h>
  42 #include <linux/err.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/of.h>
  45 #include <linux/of_device.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/platform_data/dmtimer-omap.h>
  48
  49 #include <plat/dmtimer.h>
  50
  51 static u32 omap_reserved_systimers;
  52 static LIST_HEAD(omap_timer_list);
  53 static DEFINE_SPINLOCK(dm_timer_lock);
  54
  55 /**
  56  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
  57  * @timer:      timer pointer over which read operation to perform
  58  * @reg:        lowest byte holds the register offset
  59  *
  60  * The posted mode bit is encoded in reg. Note that in posted mode write
  61  * pending bit must be checked. Otherwise a read of a non completed write
  62  * will produce an error.
  63  */
  64 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
  65 {
  66         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  67         return __omap_dm_timer_read(timer, reg, timer->posted);
  68 }
  69
  70 /**
  71  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
  72  * @timer:      timer pointer over which write operation is to perform
  73  * @reg:        lowest byte holds the register offset
  74  * @value:      data to write into the register
  75  *
  76  * The posted mode bit is encoded in reg. Note that in posted mode the write
  77  * pending bit must be checked. Otherwise a write on a register which has a
  78  * pending write will be lost.
  79  */
  80 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
  81                                                 u32 value)
  82 {
  83         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  84         __omap_dm_timer_write(timer, reg, value, timer->posted);
  85 }
  86
  87 static void omap_timer_restore_context(struct omap_dm_timer *timer)
  88 {
  89         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
  90                                 timer->context.twer);
  91         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
  92                                 timer->context.tcrr);
  93         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
  94                                 timer->context.tldr);
  95         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
  96                                 timer->context.tmar);
  97         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
  98                                 timer->context.tsicr);
  99         __raw_writel(timer->context.tier, timer->irq_ena);
 100         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
 101                                 timer->context.tclr);
 102 }
 103
 104 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
 105 {
 106         u32 l, timeout = 100000;
 107
 108         if (timer->revision != 1)
 109                 return -EINVAL;
 110
 111         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 112
 113         do {
 114                 l = __omap_dm_timer_read(timer,
 115                                          OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
 116         } while (!l && timeout--);
 117
 118         if (!timeout) {
 119                 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 120                 return -ETIMEDOUT;
 121         }
 122
 123         /* Configure timer for smart-idle mode */
 124         l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
 125         l |= 0x2 << 0x3;
 126         __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
 127
 128         timer->posted = 0;
 129
 130         return 0;
 131 }
 132
 133 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 134 {
 135         int rc;
 136
 137         /*
 138          * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
 139          * do not call clk_get() for these devices.
 140          */
 141         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 142                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
 143                 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
 144                         timer->fclk = NULL;
 145                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
 146                         return -EINVAL;
 147                 }
 148         }
 149
 150         omap_dm_timer_enable(timer);
 151
 152         if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 153                 rc = omap_dm_timer_reset(timer);
 154                 if (rc) {
 155                         omap_dm_timer_disable(timer);
 156                         return rc;
 157                 }
 158         }
 159
 160         __omap_dm_timer_enable_posted(timer);
 161         omap_dm_timer_disable(timer);
 162
 163         return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 164 }
 165
 166 static inline u32 omap_dm_timer_reserved_systimer(int id)
 167 {
 168         return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 169 }
 170
 171 int omap_dm_timer_reserve_systimer(int id)
 172 {
 173         if (omap_dm_timer_reserved_systimer(id))
 174                 return -ENODEV;
 175
 176         omap_reserved_systimers |= (1 << (id - 1));
 177
 178         return 0;
 179 }
 180
 181 struct omap_dm_timer *omap_dm_timer_request(void)
 182 {
 183         struct omap_dm_timer *timer = NULL, *t;
 184         unsigned long flags;
 185         int ret = 0;
 186
 187         spin_lock_irqsave(&dm_timer_lock, flags);
 188         list_for_each_entry(t, &omap_timer_list, node) {
 189                 if (t->reserved)
 190                         continue;
 191
 192                 timer = t;
 193                 timer->reserved = 1;
 194                 break;
 195         }
 196         spin_unlock_irqrestore(&dm_timer_lock, flags);
 197
 198         if (timer) {
 199                 ret = omap_dm_timer_prepare(timer);
 200                 if (ret) {
 201                         timer->reserved = 0;
 202                         timer = NULL;
 203                 }
 204         }
 205
 206         if (!timer)
 207                 pr_debug("%s: timer request failed!\n", __func__);
 208
 209         return timer;
 210 }
 211 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 212
 213 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 214 {
 215         struct omap_dm_timer *timer = NULL, *t;
 216         unsigned long flags;
 217         int ret = 0;
 218
 219         /* Requesting timer by ID is not supported when device tree is used */
 220         if (of_have_populated_dt()) {
 221                 pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
 222                         __func__);
 223                 return NULL;
 224         }
 225
 226         spin_lock_irqsave(&dm_timer_lock, flags);
 227         list_for_each_entry(t, &omap_timer_list, node) {
 228                 if (t->pdev->id == id && !t->reserved) {
 229                         timer = t;
 230                         timer->reserved = 1;
 231                         break;
 232                 }
 233         }
 234         spin_unlock_irqrestore(&dm_timer_lock, flags);
 235
 236         if (timer) {
 237                 ret = omap_dm_timer_prepare(timer);
 238                 if (ret) {
 239                         timer->reserved = 0;
 240                         timer = NULL;
 241                 }
 242         }
 243
 244         if (!timer)
 245                 pr_debug("%s: timer%d request failed!\n", __func__, id);
 246
 247         return timer;
 248 }
 249 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
 250
 251 /**
 252  * omap_dm_timer_request_by_cap - Request a timer by capability
 253  * @cap:        Bit mask of capabilities to match
 254  *
 255  * Find a timer based upon capabilities bit mask. Callers of this function
 256  * should use the definitions found in the plat/dmtimer.h file under the
 257  * comment "timer capabilities used in hwmod database". Returns pointer to
 258  * timer handle on success and a NULL pointer on failure.
 259  */
 260 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
 261 {
 262         struct omap_dm_timer *timer = NULL, *t;
 263         unsigned long flags;
 264
 265         if (!cap)
 266                 return NULL;
 267
 268         spin_lock_irqsave(&dm_timer_lock, flags);
 269         list_for_each_entry(t, &omap_timer_list, node) {
 270                 if ((!t->reserved) && ((t->capability & cap) == cap)) {
 271                         /*
 272                          * If timer is not NULL, we have already found one timer
 273                          * but it was not an exact match because it had more
 274                          * capabilites that what was required. Therefore,
 275                          * unreserve the last timer found and see if this one
 276                          * is a better match.
 277                          */
 278                         if (timer)
 279                                 timer->reserved = 0;
 280
 281                         timer = t;
 282                         timer->reserved = 1;
 283
 284                         /* Exit loop early if we find an exact match */
 285                         if (t->capability == cap)
 286                                 break;
 287                 }
 288         }
 289         spin_unlock_irqrestore(&dm_timer_lock, flags);
 290
 291         if (timer && omap_dm_timer_prepare(timer)) {
 292                 timer->reserved = 0;
 293                 timer = NULL;
 294         }
 295
 296         if (!timer)
 297                 pr_debug("%s: timer request failed!\n", __func__);
 298
 299         return timer;
 300 }
 301 EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
 302
 303 int omap_dm_timer_free(struct omap_dm_timer *timer)
 304 {
 305         if (unlikely(!timer))
 306                 return -EINVAL;
 307
 308         clk_put(timer->fclk);
 309
 310         WARN_ON(!timer->reserved);
 311         timer->reserved = 0;
 312         return 0;
 313 }
 314 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 315
 316 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 317 {
 318         int c;
 319
 320         pm_runtime_get_sync(&timer->pdev->dev);
 321
 322         if (!(timer->capability & OMAP_TIMER_ALWON)) {
 323                 if (timer->get_context_loss_count) {
 324                         c = timer->get_context_loss_count(&timer->pdev->dev);
 325                         if (c != timer->ctx_loss_count) {
 326                                 omap_timer_restore_context(timer);
 327                                 timer->ctx_loss_count = c;
 328                         }
 329                 }
 330         }
 331 }
 332 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 333
 334 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 335 {
 336         pm_runtime_put_sync(&timer->pdev->dev);
 337 }
 338 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 339
 340 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 341 {
 342         if (timer)
 343                 return timer->irq;
 344         return -EINVAL;
 345 }
 346 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 347
 348 #if defined(CONFIG_ARCH_OMAP1)
 349 #include <mach/hardware.h>
 350 /**
 351  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 352  * @inputmask: current value of idlect mask
 353  */
 354 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 355 {
 356         int i = 0;
 357         struct omap_dm_timer *timer = NULL;
 358         unsigned long flags;
 359
 360         /* If ARMXOR cannot be idled this function call is unnecessary */
 361         if (!(inputmask & (1 << 1)))
 362                 return inputmask;
 363
 364         /* If any active timer is using ARMXOR return modified mask */
 365         spin_lock_irqsave(&dm_timer_lock, flags);
 366         list_for_each_entry(timer, &omap_timer_list, node) {
 367                 u32 l;
 368
 369                 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 370                 if (l & OMAP_TIMER_CTRL_ST) {
 371                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 372                                 inputmask &= ~(1 << 1);
 373                         else
 374                                 inputmask &= ~(1 << 2);
 375                 }
 376                 i++;
 377         }
 378         spin_unlock_irqrestore(&dm_timer_lock, flags);
 379
 380         return inputmask;
 381 }
 382 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 383
 384 #else
 385
 386 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 387 {
 388         if (timer)
 389                 return timer->fclk;
 390         return NULL;
 391 }
 392 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
 393
 394 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 395 {
 396         BUG();
 397
 398         return 0;
 399 }
 400 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 401
 402 #endif
 403
 404 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 405 {
 406         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 407                 pr_err("%s: timer not available or enabled.\n", __func__);
 408                 return -EINVAL;
 409         }
 410
 411         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 412         return 0;
 413 }
 414 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
 415
 416 int omap_dm_timer_start(struct omap_dm_timer *timer)
 417 {
 418         u32 l;
 419
 420         if (unlikely(!timer))
 421                 return -EINVAL;
 422
 423         omap_dm_timer_enable(timer);
 424
 425         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 426         if (!(l & OMAP_TIMER_CTRL_ST)) {
 427                 l |= OMAP_TIMER_CTRL_ST;
 428                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 429         }
 430
 431         /* Save the context */
 432         timer->context.tclr = l;
 433         return 0;
 434 }
 435 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 436
 437 int omap_dm_timer_stop(struct omap_dm_timer *timer)
 438 {
 439         unsigned long rate = 0;
 440
 441         if (unlikely(!timer))
 442                 return -EINVAL;
 443
 444         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
 445                 rate = clk_get_rate(timer->fclk);
 446
 447         __omap_dm_timer_stop(timer, timer->posted, rate);
 448
 449         /*
 450          * Since the register values are computed and written within
 451          * __omap_dm_timer_stop, we need to use read to retrieve the
 452          * context.
 453          */
 454         timer->context.tclr =
 455                         omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 456         omap_dm_timer_disable(timer);
 457         return 0;
 458 }
 459 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 460
 461 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 462 {
 463         int ret;
 464         char *parent_name = NULL;
 465         struct clk *parent;
 466         struct dmtimer_platform_data *pdata;
 467
 468         if (unlikely(!timer))
 469                 return -EINVAL;
 470
 471         pdata = timer->pdev->dev.platform_data;
 472
 473         if (source < 0 || source >= 3)
 474                 return -EINVAL;
 475
 476         /*
 477          * FIXME: Used for OMAP1 devices only because they do not currently
 478          * use the clock framework to set the parent clock. To be removed
 479          * once OMAP1 migrated to using clock framework for dmtimers
 480          */
 481         if (pdata && pdata->set_timer_src)
 482                 return pdata->set_timer_src(timer->pdev, source);
 483
 484         if (!timer->fclk)
 485                 return -EINVAL;
 486
 487         switch (source) {
 488         case OMAP_TIMER_SRC_SYS_CLK:
 489                 parent_name = "timer_sys_ck";
 490                 break;
 491
 492         case OMAP_TIMER_SRC_32_KHZ:
 493                 parent_name = "timer_32k_ck";
 494                 break;
 495
 496         case OMAP_TIMER_SRC_EXT_CLK:
 497                 parent_name = "timer_ext_ck";
 498                 break;
 499         }
 500
 501         parent = clk_get(&timer->pdev->dev, parent_name);
 502         if (IS_ERR_OR_NULL(parent)) {
 503                 pr_err("%s: %s not found\n", __func__, parent_name);
 504                 return -EINVAL;
 505         }
 506
 507         ret = clk_set_parent(timer->fclk, parent);
 508         if (IS_ERR_VALUE(ret))
 509                 pr_err("%s: failed to set %s as parent\n", __func__,
 510                         parent_name);
 511
 512         clk_put(parent);
 513
 514         return ret;
 515 }
 516 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 517
 518 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 519                             unsigned int load)
 520 {
 521         u32 l;
 522
 523         if (unlikely(!timer))
 524                 return -EINVAL;
 525
 526         omap_dm_timer_enable(timer);
 527         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 528         if (autoreload)
 529                 l |= OMAP_TIMER_CTRL_AR;
 530         else
 531                 l &= ~OMAP_TIMER_CTRL_AR;
 532         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 533         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 534
 535         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 536         /* Save the context */
 537         timer->context.tclr = l;
 538         timer->context.tldr = load;
 539         omap_dm_timer_disable(timer);
 540         return 0;
 541 }
 542 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 543
 544 /* Optimized set_load which removes costly spin wait in timer_start */
 545 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
 546                             unsigned int load)
 547 {
 548         u32 l;
 549
 550         if (unlikely(!timer))
 551                 return -EINVAL;
 552
 553         omap_dm_timer_enable(timer);
 554
 555         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 556         if (autoreload) {
 557                 l |= OMAP_TIMER_CTRL_AR;
 558                 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 559         } else {
 560                 l &= ~OMAP_TIMER_CTRL_AR;
 561         }
 562         l |= OMAP_TIMER_CTRL_ST;
 563
 564         __omap_dm_timer_load_start(timer, l, load, timer->posted);
 565
 566         /* Save the context */
 567         timer->context.tclr = l;
 568         timer->context.tldr = load;
 569         timer->context.tcrr = load;
 570         return 0;
 571 }
 572 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
 573
 574 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 575                              unsigned int match)
 576 {
 577         u32 l;
 578
 579         if (unlikely(!timer))
 580                 return -EINVAL;
 581
 582         omap_dm_timer_enable(timer);
 583         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 584         if (enable)
 585                 l |= OMAP_TIMER_CTRL_CE;
 586         else
 587                 l &= ~OMAP_TIMER_CTRL_CE;
 588         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 589         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 590
 591         /* Save the context */
 592         timer->context.tclr = l;
 593         timer->context.tmar = match;
 594         omap_dm_timer_disable(timer);
 595         return 0;
 596 }
 597 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
 598
 599 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 600                            int toggle, int trigger)
 601 {
 602         u32 l;
 603
 604         if (unlikely(!timer))
 605                 return -EINVAL;
 606
 607         omap_dm_timer_enable(timer);
 608         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 609         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 610                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 611         if (def_on)
 612                 l |= OMAP_TIMER_CTRL_SCPWM;
 613         if (toggle)
 614                 l |= OMAP_TIMER_CTRL_PT;
 615         l |= trigger << 10;
 616         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 617
 618         /* Save the context */
 619         timer->context.tclr = l;
 620         omap_dm_timer_disable(timer);
 621         return 0;
 622 }
 623 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
 624
 625 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 626 {
 627         u32 l;
 628
 629         if (unlikely(!timer))
 630                 return -EINVAL;
 631
 632         omap_dm_timer_enable(timer);
 633         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 634         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 635         if (prescaler >= 0x00 && prescaler <= 0x07) {
 636                 l |= OMAP_TIMER_CTRL_PRE;
 637                 l |= prescaler << 2;
 638         }
 639         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 640
 641         /* Save the context */
 642         timer->context.tclr = l;
 643         omap_dm_timer_disable(timer);
 644         return 0;
 645 }
 646 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
 647
 648 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 649                                   unsigned int value)
 650 {
 651         if (unlikely(!timer))
 652                 return -EINVAL;
 653
 654         omap_dm_timer_enable(timer);
 655         __omap_dm_timer_int_enable(timer, value);
 656
 657         /* Save the context */
 658         timer->context.tier = value;
 659         timer->context.twer = value;
 660         omap_dm_timer_disable(timer);
 661         return 0;
 662 }
 663 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
 664
 665 /**
 666  * omap_dm_timer_set_int_disable - disable timer interrupts
 667  * @timer:      pointer to timer handle
 668  * @mask:       bit mask of interrupts to be disabled
 669  *
 670  * Disables the specified timer interrupts for a timer.
 671  */
 672 int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
 673 {
 674         u32 l = mask;
 675
 676         if (unlikely(!timer))
 677                 return -EINVAL;
 678
 679         omap_dm_timer_enable(timer);
 680
 681         if (timer->revision == 1)
 682                 l = __raw_readl(timer->irq_ena) & ~mask;
 683
 684         __raw_writel(l, timer->irq_dis);
 685         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
 686         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 687
 688         /* Save the context */
 689         timer->context.tier &= ~mask;
 690         timer->context.twer &= ~mask;
 691         omap_dm_timer_disable(timer);
 692         return 0;
 693 }
 694 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
 695
 696 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 697 {
 698         unsigned int l;
 699
 700         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 701                 pr_err("%s: timer not available or enabled.\n", __func__);
 702                 return 0;
 703         }
 704
 705         l = __raw_readl(timer->irq_stat);
 706
 707         return l;
 708 }
 709 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
 710
 711 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 712 {
 713         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
 714                 return -EINVAL;
 715
 716         __omap_dm_timer_write_status(timer, value);
 717
 718         return 0;
 719 }
 720 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 721
 722 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 723 {
 724         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 725                 pr_err("%s: timer not iavailable or enabled.\n", __func__);
 726                 return 0;
 727         }
 728
 729         return __omap_dm_timer_read_counter(timer, timer->posted);
 730 }
 731 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
 732
 733 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 734 {
 735         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 736                 pr_err("%s: timer not available or enabled.\n", __func__);
 737                 return -EINVAL;
 738         }
 739
 740         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 741
 742         /* Save the context */
 743         timer->context.tcrr = value;
 744         return 0;
 745 }
 746 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 747
 748 int omap_dm_timers_active(void)
 749 {
 750         struct omap_dm_timer *timer;
 751
 752         list_for_each_entry(timer, &omap_timer_list, node) {
 753                 if (!timer->reserved)
 754                         continue;
 755
 756                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 757                     OMAP_TIMER_CTRL_ST) {
 758                         return 1;
 759                 }
 760         }
 761         return 0;
 762 }
 763 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 764
 765 /**
 766  * omap_dm_timer_probe - probe function called for every registered device
 767  * @pdev:       pointer to current timer platform device
 768  *
 769  * Called by driver framework at the end of device registration for all
 770  * timer devices.
 771  */
 772 static int omap_dm_timer_probe(struct platform_device *pdev)
 773 {
 774         unsigned long flags;
 775         struct omap_dm_timer *timer;
 776         struct resource *mem, *irq;
 777         struct device *dev = &pdev->dev;
 778         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 779
 780         if (!pdata && !dev->of_node) {
 781                 dev_err(dev, "%s: no platform data.\n", __func__);
 782                 return -ENODEV;
 783         }
 784
 785         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 786         if (unlikely(!irq)) {
 787                 dev_err(dev, "%s: no IRQ resource.\n", __func__);
 788                 return -ENODEV;
 789         }
 790
 791         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 792         if (unlikely(!mem)) {
 793                 dev_err(dev, "%s: no memory resource.\n", __func__);
 794                 return -ENODEV;
 795         }
 796
 797         timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
 798         if (!timer) {
 799                 dev_err(dev, "%s: memory alloc failed!\n", __func__);
 800                 return  -ENOMEM;
 801         }
 802
 803         timer->io_base = devm_ioremap_resource(dev, mem);
 804         if (IS_ERR(timer->io_base))
 805                 return PTR_ERR(timer->io_base);
 806
 807         if (dev->of_node) {
 808                 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
 809                         timer->capability |= OMAP_TIMER_ALWON;
 810                 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
 811                         timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
 812                 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
 813                         timer->capability |= OMAP_TIMER_HAS_PWM;
 814                 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
 815                         timer->capability |= OMAP_TIMER_SECURE;
 816         } else {
 817                 timer->id = pdev->id;
 818                 timer->errata = pdata->timer_errata;
 819                 timer->capability = pdata->timer_capability;
 820                 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
 821                 timer->get_context_loss_count = pdata->get_context_loss_count;
 822         }
 823
 824         timer->irq = irq->start;
 825         timer->pdev = pdev;
 826
 827         /* Skip pm_runtime_enable for OMAP1 */
 828         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 829                 pm_runtime_enable(dev);
 830                 pm_runtime_irq_safe(dev);
 831         }
 832
 833         if (!timer->reserved) {
 834                 pm_runtime_get_sync(dev);
 835                 __omap_dm_timer_init_regs(timer);
 836                 pm_runtime_put(dev);
 837         }
 838
 839         /* add the timer element to the list */
 840         spin_lock_irqsave(&dm_timer_lock, flags);
 841         list_add_tail(&timer->node, &omap_timer_list);
 842         spin_unlock_irqrestore(&dm_timer_lock, flags);
 843
 844         dev_dbg(dev, "Device Probed.\n");
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * omap_dm_timer_remove - cleanup a registered timer device
 851  * @pdev:       pointer to current timer platform device
 852  *
 853  * Called by driver framework whenever a timer device is unregistered.
 854  * In addition to freeing platform resources it also deletes the timer
 855  * entry from the local list.
 856  */
 857 static int omap_dm_timer_remove(struct platform_device *pdev)
 858 {
 859         struct omap_dm_timer *timer;
 860         unsigned long flags;
 861         int ret = -EINVAL;
 862
 863         spin_lock_irqsave(&dm_timer_lock, flags);
 864         list_for_each_entry(timer, &omap_timer_list, node)
 865                 if (!strcmp(dev_name(&timer->pdev->dev),
 866                             dev_name(&pdev->dev))) {
 867                         list_del(&timer->node);
 868                         ret = 0;
 869                         break;
 870                 }
 871         spin_unlock_irqrestore(&dm_timer_lock, flags);
 872
 873         return ret;
 874 }
 875
 876 static const struct of_device_id omap_timer_match[] = {
 877         { .compatible = "ti,omap2-timer", },
 878         {},
 879 };
 880 MODULE_DEVICE_TABLE(of, omap_timer_match);
 881
 882 static struct platform_driver omap_dm_timer_driver = {
 883         .probe  = omap_dm_timer_probe,
 884         .remove = omap_dm_timer_remove,
 885         .driver = {
 886                 .name   = "omap_timer",
 887                 .of_match_table = of_match_ptr(omap_timer_match),
 888         },
 889 };
 890
 891 early_platform_init("earlytimer", &omap_dm_timer_driver);
 892 module_platform_driver(omap_dm_timer_driver);
 893
 894 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
 895 MODULE_LICENSE("GPL");
 896 MODULE_ALIAS("platform:" DRIVER_NAME);
 897 MODULE_AUTHOR("Texas Instruments Inc");