oprofile: introduce module_param oprofile.cpu_type
[deliverable/linux.git] / arch / arm / plat-omap / dmtimer.c
1 /*
2 * linux/arch/arm/plat-omap/dmtimer.c
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/errno.h>
32 #include <linux/list.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/io.h>
36 #include <linux/module.h>
37 #include <mach/hardware.h>
38 #include <mach/dmtimer.h>
39 #include <mach/irqs.h>
40
41 /* register offsets */
42 #define _OMAP_TIMER_ID_OFFSET 0x00
43 #define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
44 #define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
45 #define _OMAP_TIMER_STAT_OFFSET 0x18
46 #define _OMAP_TIMER_INT_EN_OFFSET 0x1c
47 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
48 #define _OMAP_TIMER_CTRL_OFFSET 0x24
49 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
50 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
51 #define OMAP_TIMER_CTRL_PT (1 << 12)
52 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
53 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
54 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
55 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
56 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
57 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
58 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
59 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
60 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
61 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
62 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
63 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
64 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
65 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
66 #define WP_NONE 0 /* no write pending bit */
67 #define WP_TCLR (1 << 0)
68 #define WP_TCRR (1 << 1)
69 #define WP_TLDR (1 << 2)
70 #define WP_TTGR (1 << 3)
71 #define WP_TMAR (1 << 4)
72 #define WP_TPIR (1 << 5)
73 #define WP_TNIR (1 << 6)
74 #define WP_TCVR (1 << 7)
75 #define WP_TOCR (1 << 8)
76 #define WP_TOWR (1 << 9)
77 #define _OMAP_TIMER_MATCH_OFFSET 0x38
78 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
79 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
80 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
81 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
82 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
83 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
84 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
85 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
86
87 /* register offsets with the write pending bit encoded */
88 #define WPSHIFT 16
89
90 #define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
91 | (WP_NONE << WPSHIFT))
92
93 #define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
94 | (WP_NONE << WPSHIFT))
95
96 #define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
97 | (WP_NONE << WPSHIFT))
98
99 #define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102 #define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
109 | (WP_TCLR << WPSHIFT))
110
111 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
112 | (WP_TCRR << WPSHIFT))
113
114 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
115 | (WP_TLDR << WPSHIFT))
116
117 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
118 | (WP_TTGR << WPSHIFT))
119
120 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
121 | (WP_NONE << WPSHIFT))
122
123 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
124 | (WP_TMAR << WPSHIFT))
125
126 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
127 | (WP_NONE << WPSHIFT))
128
129 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
133 | (WP_NONE << WPSHIFT))
134
135 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
136 | (WP_TPIR << WPSHIFT))
137
138 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
139 | (WP_TNIR << WPSHIFT))
140
141 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
142 | (WP_TCVR << WPSHIFT))
143
144 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
145 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
146
147 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
148 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
149
150 struct omap_dm_timer {
151 unsigned long phys_base;
152 int irq;
153 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
154 struct clk *iclk, *fclk;
155 #endif
156 void __iomem *io_base;
157 unsigned reserved:1;
158 unsigned enabled:1;
159 unsigned posted:1;
160 };
161
162 #ifdef CONFIG_ARCH_OMAP1
163
164 #define omap_dm_clk_enable(x)
165 #define omap_dm_clk_disable(x)
166 #define omap2_dm_timers NULL
167 #define omap2_dm_source_names NULL
168 #define omap2_dm_source_clocks NULL
169 #define omap3_dm_timers NULL
170 #define omap3_dm_source_names NULL
171 #define omap3_dm_source_clocks NULL
172
173 static struct omap_dm_timer omap1_dm_timers[] = {
174 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
175 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
176 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
177 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
178 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
179 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
180 { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
181 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
182 };
183
184 static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
185
186 #elif defined(CONFIG_ARCH_OMAP2)
187
188 #define omap_dm_clk_enable(x) clk_enable(x)
189 #define omap_dm_clk_disable(x) clk_disable(x)
190 #define omap1_dm_timers NULL
191 #define omap3_dm_timers NULL
192 #define omap3_dm_source_names NULL
193 #define omap3_dm_source_clocks NULL
194
195 static struct omap_dm_timer omap2_dm_timers[] = {
196 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
197 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
198 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
199 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
200 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
201 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
202 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
203 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
204 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
205 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
206 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
207 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
208 };
209
210 static const char *omap2_dm_source_names[] __initdata = {
211 "sys_ck",
212 "func_32k_ck",
213 "alt_ck",
214 NULL
215 };
216
217 static struct clk **omap2_dm_source_clocks[3];
218 static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
219
220 #elif defined(CONFIG_ARCH_OMAP3)
221
222 #define omap_dm_clk_enable(x) clk_enable(x)
223 #define omap_dm_clk_disable(x) clk_disable(x)
224 #define omap1_dm_timers NULL
225 #define omap2_dm_timers NULL
226 #define omap2_dm_source_names NULL
227 #define omap2_dm_source_clocks NULL
228
229 static struct omap_dm_timer omap3_dm_timers[] = {
230 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
231 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
232 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
233 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
234 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
235 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
236 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
237 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
238 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
239 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
240 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
241 { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
242 };
243
244 static const char *omap3_dm_source_names[] __initdata = {
245 "sys_ck",
246 "omap_32k_fck",
247 NULL
248 };
249
250 static struct clk **omap3_dm_source_clocks[2];
251 static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
252
253 #else
254
255 #error OMAP architecture not supported!
256
257 #endif
258
259 static struct omap_dm_timer *dm_timers;
260 static char **dm_source_names;
261 static struct clk **dm_source_clocks;
262
263 static spinlock_t dm_timer_lock;
264
265 /*
266 * Reads timer registers in posted and non-posted mode. The posted mode bit
267 * is encoded in reg. Note that in posted mode write pending bit must be
268 * checked. Otherwise a read of a non completed write will produce an error.
269 */
270 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
271 {
272 if (timer->posted)
273 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
274 & (reg >> WPSHIFT))
275 cpu_relax();
276 return readl(timer->io_base + (reg & 0xff));
277 }
278
279 /*
280 * Writes timer registers in posted and non-posted mode. The posted mode bit
281 * is encoded in reg. Note that in posted mode the write pending bit must be
282 * checked. Otherwise a write on a register which has a pending write will be
283 * lost.
284 */
285 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
286 u32 value)
287 {
288 if (timer->posted)
289 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
290 & (reg >> WPSHIFT))
291 cpu_relax();
292 writel(value, timer->io_base + (reg & 0xff));
293 }
294
295 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
296 {
297 int c;
298
299 c = 0;
300 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
301 c++;
302 if (c > 100000) {
303 printk(KERN_ERR "Timer failed to reset\n");
304 return;
305 }
306 }
307 }
308
309 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
310 {
311 u32 l;
312
313 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
314 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
315 omap_dm_timer_wait_for_reset(timer);
316 }
317 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
318
319 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
320 l |= 0x02 << 3; /* Set to smart-idle mode */
321 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
322
323 /*
324 * Enable wake-up only for GPT1 on OMAP2 CPUs.
325 * FIXME: All timers should have wake-up enabled and clear
326 * PRCM status.
327 */
328 if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
329 l |= 1 << 2;
330 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
331
332 /* Match hardware reset default of posted mode */
333 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
334 OMAP_TIMER_CTRL_POSTED);
335 timer->posted = 1;
336 }
337
338 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
339 {
340 omap_dm_timer_enable(timer);
341 omap_dm_timer_reset(timer);
342 }
343
344 struct omap_dm_timer *omap_dm_timer_request(void)
345 {
346 struct omap_dm_timer *timer = NULL;
347 unsigned long flags;
348 int i;
349
350 spin_lock_irqsave(&dm_timer_lock, flags);
351 for (i = 0; i < dm_timer_count; i++) {
352 if (dm_timers[i].reserved)
353 continue;
354
355 timer = &dm_timers[i];
356 timer->reserved = 1;
357 break;
358 }
359 spin_unlock_irqrestore(&dm_timer_lock, flags);
360
361 if (timer != NULL)
362 omap_dm_timer_prepare(timer);
363
364 return timer;
365 }
366 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
367
368 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
369 {
370 struct omap_dm_timer *timer;
371 unsigned long flags;
372
373 spin_lock_irqsave(&dm_timer_lock, flags);
374 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
375 spin_unlock_irqrestore(&dm_timer_lock, flags);
376 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
377 __FILE__, __LINE__, __func__, id);
378 dump_stack();
379 return NULL;
380 }
381
382 timer = &dm_timers[id-1];
383 timer->reserved = 1;
384 spin_unlock_irqrestore(&dm_timer_lock, flags);
385
386 omap_dm_timer_prepare(timer);
387
388 return timer;
389 }
390 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
391
392 void omap_dm_timer_free(struct omap_dm_timer *timer)
393 {
394 omap_dm_timer_enable(timer);
395 omap_dm_timer_reset(timer);
396 omap_dm_timer_disable(timer);
397
398 WARN_ON(!timer->reserved);
399 timer->reserved = 0;
400 }
401 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
402
403 void omap_dm_timer_enable(struct omap_dm_timer *timer)
404 {
405 if (timer->enabled)
406 return;
407
408 omap_dm_clk_enable(timer->fclk);
409 omap_dm_clk_enable(timer->iclk);
410
411 timer->enabled = 1;
412 }
413 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
414
415 void omap_dm_timer_disable(struct omap_dm_timer *timer)
416 {
417 if (!timer->enabled)
418 return;
419
420 omap_dm_clk_disable(timer->iclk);
421 omap_dm_clk_disable(timer->fclk);
422
423 timer->enabled = 0;
424 }
425 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
426
427 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
428 {
429 return timer->irq;
430 }
431 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
432
433 #if defined(CONFIG_ARCH_OMAP1)
434
435 /**
436 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
437 * @inputmask: current value of idlect mask
438 */
439 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
440 {
441 int i;
442
443 /* If ARMXOR cannot be idled this function call is unnecessary */
444 if (!(inputmask & (1 << 1)))
445 return inputmask;
446
447 /* If any active timer is using ARMXOR return modified mask */
448 for (i = 0; i < dm_timer_count; i++) {
449 u32 l;
450
451 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
452 if (l & OMAP_TIMER_CTRL_ST) {
453 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
454 inputmask &= ~(1 << 1);
455 else
456 inputmask &= ~(1 << 2);
457 }
458 }
459
460 return inputmask;
461 }
462 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
463
464 #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
465
466 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
467 {
468 return timer->fclk;
469 }
470 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
471
472 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
473 {
474 BUG();
475
476 return 0;
477 }
478 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
479
480 #endif
481
482 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
483 {
484 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
485 }
486 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
487
488 void omap_dm_timer_start(struct omap_dm_timer *timer)
489 {
490 u32 l;
491
492 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
493 if (!(l & OMAP_TIMER_CTRL_ST)) {
494 l |= OMAP_TIMER_CTRL_ST;
495 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
496 }
497 }
498 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
499
500 void omap_dm_timer_stop(struct omap_dm_timer *timer)
501 {
502 u32 l;
503
504 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
505 if (l & OMAP_TIMER_CTRL_ST) {
506 l &= ~0x1;
507 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
508 }
509 }
510 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
511
512 #ifdef CONFIG_ARCH_OMAP1
513
514 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
515 {
516 int n = (timer - dm_timers) << 1;
517 u32 l;
518
519 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
520 l |= source << n;
521 omap_writel(l, MOD_CONF_CTRL_1);
522 }
523 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
524
525 #else
526
527 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
528 {
529 if (source < 0 || source >= 3)
530 return;
531
532 clk_disable(timer->fclk);
533 clk_set_parent(timer->fclk, dm_source_clocks[source]);
534 clk_enable(timer->fclk);
535
536 /* When the functional clock disappears, too quick writes seem to
537 * cause an abort. */
538 __delay(150000);
539 }
540 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
541
542 #endif
543
544 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
545 unsigned int load)
546 {
547 u32 l;
548
549 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
550 if (autoreload)
551 l |= OMAP_TIMER_CTRL_AR;
552 else
553 l &= ~OMAP_TIMER_CTRL_AR;
554 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
555 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
556
557 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
558 }
559 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
560
561 /* Optimized set_load which removes costly spin wait in timer_start */
562 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
563 unsigned int load)
564 {
565 u32 l;
566
567 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
568 if (autoreload) {
569 l |= OMAP_TIMER_CTRL_AR;
570 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
571 } else {
572 l &= ~OMAP_TIMER_CTRL_AR;
573 }
574 l |= OMAP_TIMER_CTRL_ST;
575
576 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
577 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
578 }
579 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
580
581 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
582 unsigned int match)
583 {
584 u32 l;
585
586 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
587 if (enable)
588 l |= OMAP_TIMER_CTRL_CE;
589 else
590 l &= ~OMAP_TIMER_CTRL_CE;
591 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
592 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
593 }
594 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
595
596 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
597 int toggle, int trigger)
598 {
599 u32 l;
600
601 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
602 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
603 OMAP_TIMER_CTRL_PT | (0x03 << 10));
604 if (def_on)
605 l |= OMAP_TIMER_CTRL_SCPWM;
606 if (toggle)
607 l |= OMAP_TIMER_CTRL_PT;
608 l |= trigger << 10;
609 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
610 }
611 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
612
613 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
614 {
615 u32 l;
616
617 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
618 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
619 if (prescaler >= 0x00 && prescaler <= 0x07) {
620 l |= OMAP_TIMER_CTRL_PRE;
621 l |= prescaler << 2;
622 }
623 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
624 }
625 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
626
627 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
628 unsigned int value)
629 {
630 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
631 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
632 }
633 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
634
635 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
636 {
637 unsigned int l;
638
639 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
640
641 return l;
642 }
643 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
644
645 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
646 {
647 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
648 }
649 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
650
651 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
652 {
653 unsigned int l;
654
655 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
656
657 return l;
658 }
659 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
660
661 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
662 {
663 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
664 }
665 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
666
667 int omap_dm_timers_active(void)
668 {
669 int i;
670
671 for (i = 0; i < dm_timer_count; i++) {
672 struct omap_dm_timer *timer;
673
674 timer = &dm_timers[i];
675
676 if (!timer->enabled)
677 continue;
678
679 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
680 OMAP_TIMER_CTRL_ST) {
681 return 1;
682 }
683 }
684 return 0;
685 }
686 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
687
688 int __init omap_dm_timer_init(void)
689 {
690 struct omap_dm_timer *timer;
691 int i;
692
693 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
694 return -ENODEV;
695
696 spin_lock_init(&dm_timer_lock);
697
698 if (cpu_class_is_omap1())
699 dm_timers = omap1_dm_timers;
700 else if (cpu_is_omap24xx()) {
701 dm_timers = omap2_dm_timers;
702 dm_source_names = (char **)omap2_dm_source_names;
703 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
704 } else if (cpu_is_omap34xx()) {
705 dm_timers = omap3_dm_timers;
706 dm_source_names = (char **)omap3_dm_source_names;
707 dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
708 }
709
710 if (cpu_class_is_omap2())
711 for (i = 0; dm_source_names[i] != NULL; i++)
712 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
713
714 if (cpu_is_omap243x())
715 dm_timers[0].phys_base = 0x49018000;
716
717 for (i = 0; i < dm_timer_count; i++) {
718 timer = &dm_timers[i];
719 timer->io_base = IO_ADDRESS(timer->phys_base);
720 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
721 if (cpu_class_is_omap2()) {
722 char clk_name[16];
723 sprintf(clk_name, "gpt%d_ick", i + 1);
724 timer->iclk = clk_get(NULL, clk_name);
725 sprintf(clk_name, "gpt%d_fck", i + 1);
726 timer->fclk = clk_get(NULL, clk_name);
727 }
728 #endif
729 }
730
731 return 0;
732 }
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