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Initial blind fixup for arm for irq changes
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22
23 #include <asm/hardware.h>
24 #include <asm/irq.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
28
29 #include <asm/io.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP730 specific GPIO registers
72 */
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
85
86 /*
87 * omap24xx specific GPIO registers
88 */
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
98 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
99 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
100 #define OMAP24XX_GPIO_CTRL 0x0030
101 #define OMAP24XX_GPIO_OE 0x0034
102 #define OMAP24XX_GPIO_DATAIN 0x0038
103 #define OMAP24XX_GPIO_DATAOUT 0x003c
104 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
105 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
106 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
107 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
108 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
109 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
110 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
111 #define OMAP24XX_GPIO_SETWKUENA 0x0084
112 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
113 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
114
115 struct gpio_bank {
116 void __iomem *base;
117 u16 irq;
118 u16 virtual_irq_start;
119 int method;
120 u32 reserved_map;
121 u32 suspend_wakeup;
122 u32 saved_wakeup;
123 spinlock_t lock;
124 };
125
126 #define METHOD_MPUIO 0
127 #define METHOD_GPIO_1510 1
128 #define METHOD_GPIO_1610 2
129 #define METHOD_GPIO_730 3
130 #define METHOD_GPIO_24XX 4
131
132 #ifdef CONFIG_ARCH_OMAP16XX
133 static struct gpio_bank gpio_bank_1610[5] = {
134 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
135 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
136 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
138 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
139 };
140 #endif
141
142 #ifdef CONFIG_ARCH_OMAP15XX
143 static struct gpio_bank gpio_bank_1510[2] = {
144 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
145 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
146 };
147 #endif
148
149 #ifdef CONFIG_ARCH_OMAP730
150 static struct gpio_bank gpio_bank_730[7] = {
151 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
152 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
153 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
154 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
155 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
156 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
157 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
158 };
159 #endif
160
161 #ifdef CONFIG_ARCH_OMAP24XX
162 static struct gpio_bank gpio_bank_24xx[4] = {
163 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
166 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
167 };
168 #endif
169
170 static struct gpio_bank *gpio_bank;
171 static int gpio_bank_count;
172
173 static inline struct gpio_bank *get_gpio_bank(int gpio)
174 {
175 #ifdef CONFIG_ARCH_OMAP15XX
176 if (cpu_is_omap15xx()) {
177 if (OMAP_GPIO_IS_MPUIO(gpio))
178 return &gpio_bank[0];
179 return &gpio_bank[1];
180 }
181 #endif
182 #if defined(CONFIG_ARCH_OMAP16XX)
183 if (cpu_is_omap16xx()) {
184 if (OMAP_GPIO_IS_MPUIO(gpio))
185 return &gpio_bank[0];
186 return &gpio_bank[1 + (gpio >> 4)];
187 }
188 #endif
189 #ifdef CONFIG_ARCH_OMAP730
190 if (cpu_is_omap730()) {
191 if (OMAP_GPIO_IS_MPUIO(gpio))
192 return &gpio_bank[0];
193 return &gpio_bank[1 + (gpio >> 5)];
194 }
195 #endif
196 #ifdef CONFIG_ARCH_OMAP24XX
197 if (cpu_is_omap24xx())
198 return &gpio_bank[gpio >> 5];
199 #endif
200 }
201
202 static inline int get_gpio_index(int gpio)
203 {
204 #ifdef CONFIG_ARCH_OMAP730
205 if (cpu_is_omap730())
206 return gpio & 0x1f;
207 #endif
208 #ifdef CONFIG_ARCH_OMAP24XX
209 if (cpu_is_omap24xx())
210 return gpio & 0x1f;
211 #endif
212 return gpio & 0x0f;
213 }
214
215 static inline int gpio_valid(int gpio)
216 {
217 if (gpio < 0)
218 return -1;
219 #ifndef CONFIG_ARCH_OMAP24XX
220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
221 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
222 return -1;
223 return 0;
224 }
225 #endif
226 #ifdef CONFIG_ARCH_OMAP15XX
227 if (cpu_is_omap15xx() && gpio < 16)
228 return 0;
229 #endif
230 #if defined(CONFIG_ARCH_OMAP16XX)
231 if ((cpu_is_omap16xx()) && gpio < 64)
232 return 0;
233 #endif
234 #ifdef CONFIG_ARCH_OMAP730
235 if (cpu_is_omap730() && gpio < 192)
236 return 0;
237 #endif
238 #ifdef CONFIG_ARCH_OMAP24XX
239 if (cpu_is_omap24xx() && gpio < 128)
240 return 0;
241 #endif
242 return -1;
243 }
244
245 static int check_gpio(int gpio)
246 {
247 if (unlikely(gpio_valid(gpio)) < 0) {
248 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
249 dump_stack();
250 return -1;
251 }
252 return 0;
253 }
254
255 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
256 {
257 void __iomem *reg = bank->base;
258 u32 l;
259
260 switch (bank->method) {
261 case METHOD_MPUIO:
262 reg += OMAP_MPUIO_IO_CNTL;
263 break;
264 case METHOD_GPIO_1510:
265 reg += OMAP1510_GPIO_DIR_CONTROL;
266 break;
267 case METHOD_GPIO_1610:
268 reg += OMAP1610_GPIO_DIRECTION;
269 break;
270 case METHOD_GPIO_730:
271 reg += OMAP730_GPIO_DIR_CONTROL;
272 break;
273 case METHOD_GPIO_24XX:
274 reg += OMAP24XX_GPIO_OE;
275 break;
276 }
277 l = __raw_readl(reg);
278 if (is_input)
279 l |= 1 << gpio;
280 else
281 l &= ~(1 << gpio);
282 __raw_writel(l, reg);
283 }
284
285 void omap_set_gpio_direction(int gpio, int is_input)
286 {
287 struct gpio_bank *bank;
288
289 if (check_gpio(gpio) < 0)
290 return;
291 bank = get_gpio_bank(gpio);
292 spin_lock(&bank->lock);
293 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
294 spin_unlock(&bank->lock);
295 }
296
297 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
298 {
299 void __iomem *reg = bank->base;
300 u32 l = 0;
301
302 switch (bank->method) {
303 case METHOD_MPUIO:
304 reg += OMAP_MPUIO_OUTPUT;
305 l = __raw_readl(reg);
306 if (enable)
307 l |= 1 << gpio;
308 else
309 l &= ~(1 << gpio);
310 break;
311 case METHOD_GPIO_1510:
312 reg += OMAP1510_GPIO_DATA_OUTPUT;
313 l = __raw_readl(reg);
314 if (enable)
315 l |= 1 << gpio;
316 else
317 l &= ~(1 << gpio);
318 break;
319 case METHOD_GPIO_1610:
320 if (enable)
321 reg += OMAP1610_GPIO_SET_DATAOUT;
322 else
323 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
324 l = 1 << gpio;
325 break;
326 case METHOD_GPIO_730:
327 reg += OMAP730_GPIO_DATA_OUTPUT;
328 l = __raw_readl(reg);
329 if (enable)
330 l |= 1 << gpio;
331 else
332 l &= ~(1 << gpio);
333 break;
334 case METHOD_GPIO_24XX:
335 if (enable)
336 reg += OMAP24XX_GPIO_SETDATAOUT;
337 else
338 reg += OMAP24XX_GPIO_CLEARDATAOUT;
339 l = 1 << gpio;
340 break;
341 default:
342 BUG();
343 return;
344 }
345 __raw_writel(l, reg);
346 }
347
348 void omap_set_gpio_dataout(int gpio, int enable)
349 {
350 struct gpio_bank *bank;
351
352 if (check_gpio(gpio) < 0)
353 return;
354 bank = get_gpio_bank(gpio);
355 spin_lock(&bank->lock);
356 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
357 spin_unlock(&bank->lock);
358 }
359
360 int omap_get_gpio_datain(int gpio)
361 {
362 struct gpio_bank *bank;
363 void __iomem *reg;
364
365 if (check_gpio(gpio) < 0)
366 return -1;
367 bank = get_gpio_bank(gpio);
368 reg = bank->base;
369 switch (bank->method) {
370 case METHOD_MPUIO:
371 reg += OMAP_MPUIO_INPUT_LATCH;
372 break;
373 case METHOD_GPIO_1510:
374 reg += OMAP1510_GPIO_DATA_INPUT;
375 break;
376 case METHOD_GPIO_1610:
377 reg += OMAP1610_GPIO_DATAIN;
378 break;
379 case METHOD_GPIO_730:
380 reg += OMAP730_GPIO_DATA_INPUT;
381 break;
382 case METHOD_GPIO_24XX:
383 reg += OMAP24XX_GPIO_DATAIN;
384 break;
385 default:
386 BUG();
387 return -1;
388 }
389 return (__raw_readl(reg)
390 & (1 << get_gpio_index(gpio))) != 0;
391 }
392
393 #define MOD_REG_BIT(reg, bit_mask, set) \
394 do { \
395 int l = __raw_readl(base + reg); \
396 if (set) l |= bit_mask; \
397 else l &= ~bit_mask; \
398 __raw_writel(l, base + reg); \
399 } while(0)
400
401 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
402 {
403 u32 gpio_bit = 1 << gpio;
404
405 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
406 trigger & __IRQT_LOWLVL);
407 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
408 trigger & __IRQT_HIGHLVL);
409 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
410 trigger & __IRQT_RISEDGE);
411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
412 trigger & __IRQT_FALEDGE);
413 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
414 * triggering requested. */
415 }
416
417 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
418 {
419 void __iomem *reg = bank->base;
420 u32 l = 0;
421
422 switch (bank->method) {
423 case METHOD_MPUIO:
424 reg += OMAP_MPUIO_GPIO_INT_EDGE;
425 l = __raw_readl(reg);
426 if (trigger & __IRQT_RISEDGE)
427 l |= 1 << gpio;
428 else if (trigger & __IRQT_FALEDGE)
429 l &= ~(1 << gpio);
430 else
431 goto bad;
432 break;
433 case METHOD_GPIO_1510:
434 reg += OMAP1510_GPIO_INT_CONTROL;
435 l = __raw_readl(reg);
436 if (trigger & __IRQT_RISEDGE)
437 l |= 1 << gpio;
438 else if (trigger & __IRQT_FALEDGE)
439 l &= ~(1 << gpio);
440 else
441 goto bad;
442 break;
443 case METHOD_GPIO_1610:
444 if (gpio & 0x08)
445 reg += OMAP1610_GPIO_EDGE_CTRL2;
446 else
447 reg += OMAP1610_GPIO_EDGE_CTRL1;
448 gpio &= 0x07;
449 /* We allow only edge triggering, i.e. two lowest bits */
450 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
451 BUG();
452 l = __raw_readl(reg);
453 l &= ~(3 << (gpio << 1));
454 if (trigger & __IRQT_RISEDGE)
455 l |= 2 << (gpio << 1);
456 if (trigger & __IRQT_FALEDGE)
457 l |= 1 << (gpio << 1);
458 break;
459 case METHOD_GPIO_730:
460 reg += OMAP730_GPIO_INT_CONTROL;
461 l = __raw_readl(reg);
462 if (trigger & __IRQT_RISEDGE)
463 l |= 1 << gpio;
464 else if (trigger & __IRQT_FALEDGE)
465 l &= ~(1 << gpio);
466 else
467 goto bad;
468 break;
469 case METHOD_GPIO_24XX:
470 set_24xx_gpio_triggering(reg, gpio, trigger);
471 break;
472 default:
473 BUG();
474 goto bad;
475 }
476 __raw_writel(l, reg);
477 return 0;
478 bad:
479 return -EINVAL;
480 }
481
482 static int gpio_irq_type(unsigned irq, unsigned type)
483 {
484 struct gpio_bank *bank;
485 unsigned gpio;
486 int retval;
487
488 if (irq > IH_MPUIO_BASE)
489 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
490 else
491 gpio = irq - IH_GPIO_BASE;
492
493 if (check_gpio(gpio) < 0)
494 return -EINVAL;
495
496 if (type & IRQT_PROBE)
497 return -EINVAL;
498 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
499 return -EINVAL;
500
501 bank = get_gpio_bank(gpio);
502 spin_lock(&bank->lock);
503 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
504 spin_unlock(&bank->lock);
505 return retval;
506 }
507
508 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
509 {
510 void __iomem *reg = bank->base;
511
512 switch (bank->method) {
513 case METHOD_MPUIO:
514 /* MPUIO irqstatus is reset by reading the status register,
515 * so do nothing here */
516 return;
517 case METHOD_GPIO_1510:
518 reg += OMAP1510_GPIO_INT_STATUS;
519 break;
520 case METHOD_GPIO_1610:
521 reg += OMAP1610_GPIO_IRQSTATUS1;
522 break;
523 case METHOD_GPIO_730:
524 reg += OMAP730_GPIO_INT_STATUS;
525 break;
526 case METHOD_GPIO_24XX:
527 reg += OMAP24XX_GPIO_IRQSTATUS1;
528 break;
529 default:
530 BUG();
531 return;
532 }
533 __raw_writel(gpio_mask, reg);
534
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (cpu_is_omap2420())
537 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
538 }
539
540 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
541 {
542 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
543 }
544
545 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
546 {
547 void __iomem *reg = bank->base;
548 int inv = 0;
549 u32 l;
550 u32 mask;
551
552 switch (bank->method) {
553 case METHOD_MPUIO:
554 reg += OMAP_MPUIO_GPIO_MASKIT;
555 mask = 0xffff;
556 inv = 1;
557 break;
558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_MASK;
560 mask = 0xffff;
561 inv = 1;
562 break;
563 case METHOD_GPIO_1610:
564 reg += OMAP1610_GPIO_IRQENABLE1;
565 mask = 0xffff;
566 break;
567 case METHOD_GPIO_730:
568 reg += OMAP730_GPIO_INT_MASK;
569 mask = 0xffffffff;
570 inv = 1;
571 break;
572 case METHOD_GPIO_24XX:
573 reg += OMAP24XX_GPIO_IRQENABLE1;
574 mask = 0xffffffff;
575 break;
576 default:
577 BUG();
578 return 0;
579 }
580
581 l = __raw_readl(reg);
582 if (inv)
583 l = ~l;
584 l &= mask;
585 return l;
586 }
587
588 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
589 {
590 void __iomem *reg = bank->base;
591 u32 l;
592
593 switch (bank->method) {
594 case METHOD_MPUIO:
595 reg += OMAP_MPUIO_GPIO_MASKIT;
596 l = __raw_readl(reg);
597 if (enable)
598 l &= ~(gpio_mask);
599 else
600 l |= gpio_mask;
601 break;
602 case METHOD_GPIO_1510:
603 reg += OMAP1510_GPIO_INT_MASK;
604 l = __raw_readl(reg);
605 if (enable)
606 l &= ~(gpio_mask);
607 else
608 l |= gpio_mask;
609 break;
610 case METHOD_GPIO_1610:
611 if (enable)
612 reg += OMAP1610_GPIO_SET_IRQENABLE1;
613 else
614 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
615 l = gpio_mask;
616 break;
617 case METHOD_GPIO_730:
618 reg += OMAP730_GPIO_INT_MASK;
619 l = __raw_readl(reg);
620 if (enable)
621 l &= ~(gpio_mask);
622 else
623 l |= gpio_mask;
624 break;
625 case METHOD_GPIO_24XX:
626 if (enable)
627 reg += OMAP24XX_GPIO_SETIRQENABLE1;
628 else
629 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
630 l = gpio_mask;
631 break;
632 default:
633 BUG();
634 return;
635 }
636 __raw_writel(l, reg);
637 }
638
639 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
640 {
641 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
642 }
643
644 /*
645 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
646 * 1510 does not seem to have a wake-up register. If JTAG is connected
647 * to the target, system will wake up always on GPIO events. While
648 * system is running all registered GPIO interrupts need to have wake-up
649 * enabled. When system is suspended, only selected GPIO interrupts need
650 * to have wake-up enabled.
651 */
652 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
653 {
654 switch (bank->method) {
655 case METHOD_GPIO_1610:
656 case METHOD_GPIO_24XX:
657 spin_lock(&bank->lock);
658 if (enable)
659 bank->suspend_wakeup |= (1 << gpio);
660 else
661 bank->suspend_wakeup &= ~(1 << gpio);
662 spin_unlock(&bank->lock);
663 return 0;
664 default:
665 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
666 bank->method);
667 return -EINVAL;
668 }
669 }
670
671 static void _reset_gpio(struct gpio_bank *bank, int gpio)
672 {
673 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
674 _set_gpio_irqenable(bank, gpio, 0);
675 _clear_gpio_irqstatus(bank, gpio);
676 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
677 }
678
679 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
680 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
681 {
682 unsigned int gpio = irq - IH_GPIO_BASE;
683 struct gpio_bank *bank;
684 int retval;
685
686 if (check_gpio(gpio) < 0)
687 return -ENODEV;
688 bank = get_gpio_bank(gpio);
689 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
690
691 return retval;
692 }
693
694 int omap_request_gpio(int gpio)
695 {
696 struct gpio_bank *bank;
697
698 if (check_gpio(gpio) < 0)
699 return -EINVAL;
700
701 bank = get_gpio_bank(gpio);
702 spin_lock(&bank->lock);
703 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
704 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
705 dump_stack();
706 spin_unlock(&bank->lock);
707 return -1;
708 }
709 bank->reserved_map |= (1 << get_gpio_index(gpio));
710
711 /* Set trigger to none. You need to enable the desired trigger with
712 * request_irq() or set_irq_type().
713 */
714 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
715
716 #ifdef CONFIG_ARCH_OMAP15XX
717 if (bank->method == METHOD_GPIO_1510) {
718 void __iomem *reg;
719
720 /* Claim the pin for MPU */
721 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
722 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
723 }
724 #endif
725 #ifdef CONFIG_ARCH_OMAP16XX
726 if (bank->method == METHOD_GPIO_1610) {
727 /* Enable wake-up during idle for dynamic tick */
728 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
729 __raw_writel(1 << get_gpio_index(gpio), reg);
730 }
731 #endif
732 #ifdef CONFIG_ARCH_OMAP24XX
733 if (bank->method == METHOD_GPIO_24XX) {
734 /* Enable wake-up during idle for dynamic tick */
735 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
736 __raw_writel(1 << get_gpio_index(gpio), reg);
737 }
738 #endif
739 spin_unlock(&bank->lock);
740
741 return 0;
742 }
743
744 void omap_free_gpio(int gpio)
745 {
746 struct gpio_bank *bank;
747
748 if (check_gpio(gpio) < 0)
749 return;
750 bank = get_gpio_bank(gpio);
751 spin_lock(&bank->lock);
752 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
753 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
754 dump_stack();
755 spin_unlock(&bank->lock);
756 return;
757 }
758 #ifdef CONFIG_ARCH_OMAP16XX
759 if (bank->method == METHOD_GPIO_1610) {
760 /* Disable wake-up during idle for dynamic tick */
761 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
762 __raw_writel(1 << get_gpio_index(gpio), reg);
763 }
764 #endif
765 #ifdef CONFIG_ARCH_OMAP24XX
766 if (bank->method == METHOD_GPIO_24XX) {
767 /* Disable wake-up during idle for dynamic tick */
768 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
769 __raw_writel(1 << get_gpio_index(gpio), reg);
770 }
771 #endif
772 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
773 _reset_gpio(bank, gpio);
774 spin_unlock(&bank->lock);
775 }
776
777 /*
778 * We need to unmask the GPIO bank interrupt as soon as possible to
779 * avoid missing GPIO interrupts for other lines in the bank.
780 * Then we need to mask-read-clear-unmask the triggered GPIO lines
781 * in the bank to avoid missing nested interrupts for a GPIO line.
782 * If we wait to unmask individual GPIO lines in the bank after the
783 * line's interrupt handler has been run, we may miss some nested
784 * interrupts.
785 */
786 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
787 {
788 void __iomem *isr_reg = NULL;
789 u32 isr;
790 unsigned int gpio_irq;
791 struct gpio_bank *bank;
792 u32 retrigger = 0;
793 int unmasked = 0;
794
795 desc->chip->ack(irq);
796
797 bank = get_irq_data(irq);
798 if (bank->method == METHOD_MPUIO)
799 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
800 #ifdef CONFIG_ARCH_OMAP15XX
801 if (bank->method == METHOD_GPIO_1510)
802 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
803 #endif
804 #if defined(CONFIG_ARCH_OMAP16XX)
805 if (bank->method == METHOD_GPIO_1610)
806 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
807 #endif
808 #ifdef CONFIG_ARCH_OMAP730
809 if (bank->method == METHOD_GPIO_730)
810 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
811 #endif
812 #ifdef CONFIG_ARCH_OMAP24XX
813 if (bank->method == METHOD_GPIO_24XX)
814 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
815 #endif
816 while(1) {
817 u32 isr_saved, level_mask = 0;
818 u32 enabled;
819
820 enabled = _get_gpio_irqbank_mask(bank);
821 isr_saved = isr = __raw_readl(isr_reg) & enabled;
822
823 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
824 isr &= 0x0000ffff;
825
826 if (cpu_is_omap24xx()) {
827 level_mask =
828 __raw_readl(bank->base +
829 OMAP24XX_GPIO_LEVELDETECT0) |
830 __raw_readl(bank->base +
831 OMAP24XX_GPIO_LEVELDETECT1);
832 level_mask &= enabled;
833 }
834
835 /* clear edge sensitive interrupts before handler(s) are
836 called so that we don't miss any interrupt occurred while
837 executing them */
838 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
839 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
840 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
841
842 /* if there is only edge sensitive GPIO pin interrupts
843 configured, we could unmask GPIO bank interrupt immediately */
844 if (!level_mask && !unmasked) {
845 unmasked = 1;
846 desc->chip->unmask(irq);
847 }
848
849 isr |= retrigger;
850 retrigger = 0;
851 if (!isr)
852 break;
853
854 gpio_irq = bank->virtual_irq_start;
855 for (; isr != 0; isr >>= 1, gpio_irq++) {
856 struct irqdesc *d;
857 int irq_mask;
858 if (!(isr & 1))
859 continue;
860 d = irq_desc + gpio_irq;
861 /* Don't run the handler if it's already running
862 * or was disabled lazely.
863 */
864 if (unlikely((d->depth ||
865 (d->status & IRQ_INPROGRESS)))) {
866 irq_mask = 1 <<
867 (gpio_irq - bank->virtual_irq_start);
868 /* The unmasking will be done by
869 * enable_irq in case it is disabled or
870 * after returning from the handler if
871 * it's already running.
872 */
873 _enable_gpio_irqbank(bank, irq_mask, 0);
874 if (!d->depth) {
875 /* Level triggered interrupts
876 * won't ever be reentered
877 */
878 BUG_ON(level_mask & irq_mask);
879 d->status |= IRQ_PENDING;
880 }
881 continue;
882 }
883
884 desc_handle_irq(gpio_irq, d);
885
886 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
887 irq_mask = 1 <<
888 (gpio_irq - bank->virtual_irq_start);
889 d->status &= ~IRQ_PENDING;
890 _enable_gpio_irqbank(bank, irq_mask, 1);
891 retrigger |= irq_mask;
892 }
893 }
894
895 if (cpu_is_omap24xx()) {
896 /* clear level sensitive interrupts after handler(s) */
897 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
898 _clear_gpio_irqbank(bank, isr_saved & level_mask);
899 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
900 }
901
902 }
903 /* if bank has any level sensitive GPIO pin interrupt
904 configured, we must unmask the bank interrupt only after
905 handler(s) are executed in order to avoid spurious bank
906 interrupt */
907 if (!unmasked)
908 desc->chip->unmask(irq);
909
910 }
911
912 static void gpio_irq_shutdown(unsigned int irq)
913 {
914 unsigned int gpio = irq - IH_GPIO_BASE;
915 struct gpio_bank *bank = get_gpio_bank(gpio);
916
917 _reset_gpio(bank, gpio);
918 }
919
920 static void gpio_ack_irq(unsigned int irq)
921 {
922 unsigned int gpio = irq - IH_GPIO_BASE;
923 struct gpio_bank *bank = get_gpio_bank(gpio);
924
925 _clear_gpio_irqstatus(bank, gpio);
926 }
927
928 static void gpio_mask_irq(unsigned int irq)
929 {
930 unsigned int gpio = irq - IH_GPIO_BASE;
931 struct gpio_bank *bank = get_gpio_bank(gpio);
932
933 _set_gpio_irqenable(bank, gpio, 0);
934 }
935
936 static void gpio_unmask_irq(unsigned int irq)
937 {
938 unsigned int gpio = irq - IH_GPIO_BASE;
939 unsigned int gpio_idx = get_gpio_index(gpio);
940 struct gpio_bank *bank = get_gpio_bank(gpio);
941
942 _set_gpio_irqenable(bank, gpio_idx, 1);
943 }
944
945 static void mpuio_ack_irq(unsigned int irq)
946 {
947 /* The ISR is reset automatically, so do nothing here. */
948 }
949
950 static void mpuio_mask_irq(unsigned int irq)
951 {
952 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
953 struct gpio_bank *bank = get_gpio_bank(gpio);
954
955 _set_gpio_irqenable(bank, gpio, 0);
956 }
957
958 static void mpuio_unmask_irq(unsigned int irq)
959 {
960 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
961 struct gpio_bank *bank = get_gpio_bank(gpio);
962
963 _set_gpio_irqenable(bank, gpio, 1);
964 }
965
966 static struct irq_chip gpio_irq_chip = {
967 .name = "GPIO",
968 .shutdown = gpio_irq_shutdown,
969 .ack = gpio_ack_irq,
970 .mask = gpio_mask_irq,
971 .unmask = gpio_unmask_irq,
972 .set_type = gpio_irq_type,
973 .set_wake = gpio_wake_enable,
974 };
975
976 static struct irq_chip mpuio_irq_chip = {
977 .name = "MPUIO",
978 .ack = mpuio_ack_irq,
979 .mask = mpuio_mask_irq,
980 .unmask = mpuio_unmask_irq
981 };
982
983 static int initialized;
984 static struct clk * gpio_ick;
985 static struct clk * gpio_fck;
986
987 static int __init _omap_gpio_init(void)
988 {
989 int i;
990 struct gpio_bank *bank;
991
992 initialized = 1;
993
994 if (cpu_is_omap15xx()) {
995 gpio_ick = clk_get(NULL, "arm_gpio_ck");
996 if (IS_ERR(gpio_ick))
997 printk("Could not get arm_gpio_ck\n");
998 else
999 clk_enable(gpio_ick);
1000 }
1001 if (cpu_is_omap24xx()) {
1002 gpio_ick = clk_get(NULL, "gpios_ick");
1003 if (IS_ERR(gpio_ick))
1004 printk("Could not get gpios_ick\n");
1005 else
1006 clk_enable(gpio_ick);
1007 gpio_fck = clk_get(NULL, "gpios_fck");
1008 if (IS_ERR(gpio_fck))
1009 printk("Could not get gpios_fck\n");
1010 else
1011 clk_enable(gpio_fck);
1012 }
1013
1014 #ifdef CONFIG_ARCH_OMAP15XX
1015 if (cpu_is_omap15xx()) {
1016 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1017 gpio_bank_count = 2;
1018 gpio_bank = gpio_bank_1510;
1019 }
1020 #endif
1021 #if defined(CONFIG_ARCH_OMAP16XX)
1022 if (cpu_is_omap16xx()) {
1023 u32 rev;
1024
1025 gpio_bank_count = 5;
1026 gpio_bank = gpio_bank_1610;
1027 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1028 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1029 (rev >> 4) & 0x0f, rev & 0x0f);
1030 }
1031 #endif
1032 #ifdef CONFIG_ARCH_OMAP730
1033 if (cpu_is_omap730()) {
1034 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1035 gpio_bank_count = 7;
1036 gpio_bank = gpio_bank_730;
1037 }
1038 #endif
1039 #ifdef CONFIG_ARCH_OMAP24XX
1040 if (cpu_is_omap24xx()) {
1041 int rev;
1042
1043 gpio_bank_count = 4;
1044 gpio_bank = gpio_bank_24xx;
1045 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1046 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1047 (rev >> 4) & 0x0f, rev & 0x0f);
1048 }
1049 #endif
1050 for (i = 0; i < gpio_bank_count; i++) {
1051 int j, gpio_count = 16;
1052
1053 bank = &gpio_bank[i];
1054 bank->reserved_map = 0;
1055 bank->base = IO_ADDRESS(bank->base);
1056 spin_lock_init(&bank->lock);
1057 if (bank->method == METHOD_MPUIO) {
1058 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1059 }
1060 #ifdef CONFIG_ARCH_OMAP15XX
1061 if (bank->method == METHOD_GPIO_1510) {
1062 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1063 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1064 }
1065 #endif
1066 #if defined(CONFIG_ARCH_OMAP16XX)
1067 if (bank->method == METHOD_GPIO_1610) {
1068 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1069 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1070 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1071 }
1072 #endif
1073 #ifdef CONFIG_ARCH_OMAP730
1074 if (bank->method == METHOD_GPIO_730) {
1075 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1076 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1077
1078 gpio_count = 32; /* 730 has 32-bit GPIOs */
1079 }
1080 #endif
1081 #ifdef CONFIG_ARCH_OMAP24XX
1082 if (bank->method == METHOD_GPIO_24XX) {
1083 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1084 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1085
1086 gpio_count = 32;
1087 }
1088 #endif
1089 for (j = bank->virtual_irq_start;
1090 j < bank->virtual_irq_start + gpio_count; j++) {
1091 if (bank->method == METHOD_MPUIO)
1092 set_irq_chip(j, &mpuio_irq_chip);
1093 else
1094 set_irq_chip(j, &gpio_irq_chip);
1095 set_irq_handler(j, do_simple_IRQ);
1096 set_irq_flags(j, IRQF_VALID);
1097 }
1098 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1099 set_irq_data(bank->irq, bank);
1100 }
1101
1102 /* Enable system clock for GPIO module.
1103 * The CAM_CLK_CTRL *is* really the right place. */
1104 if (cpu_is_omap16xx())
1105 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1106
1107 return 0;
1108 }
1109
1110 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1111 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1112 {
1113 int i;
1114
1115 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1116 return 0;
1117
1118 for (i = 0; i < gpio_bank_count; i++) {
1119 struct gpio_bank *bank = &gpio_bank[i];
1120 void __iomem *wake_status;
1121 void __iomem *wake_clear;
1122 void __iomem *wake_set;
1123
1124 switch (bank->method) {
1125 case METHOD_GPIO_1610:
1126 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1127 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1128 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1129 break;
1130 case METHOD_GPIO_24XX:
1131 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1132 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1133 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1134 break;
1135 default:
1136 continue;
1137 }
1138
1139 spin_lock(&bank->lock);
1140 bank->saved_wakeup = __raw_readl(wake_status);
1141 __raw_writel(0xffffffff, wake_clear);
1142 __raw_writel(bank->suspend_wakeup, wake_set);
1143 spin_unlock(&bank->lock);
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int omap_gpio_resume(struct sys_device *dev)
1150 {
1151 int i;
1152
1153 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1154 return 0;
1155
1156 for (i = 0; i < gpio_bank_count; i++) {
1157 struct gpio_bank *bank = &gpio_bank[i];
1158 void __iomem *wake_clear;
1159 void __iomem *wake_set;
1160
1161 switch (bank->method) {
1162 case METHOD_GPIO_1610:
1163 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1164 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1165 break;
1166 case METHOD_GPIO_24XX:
1167 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1168 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1169 break;
1170 default:
1171 continue;
1172 }
1173
1174 spin_lock(&bank->lock);
1175 __raw_writel(0xffffffff, wake_clear);
1176 __raw_writel(bank->saved_wakeup, wake_set);
1177 spin_unlock(&bank->lock);
1178 }
1179
1180 return 0;
1181 }
1182
1183 static struct sysdev_class omap_gpio_sysclass = {
1184 set_kset_name("gpio"),
1185 .suspend = omap_gpio_suspend,
1186 .resume = omap_gpio_resume,
1187 };
1188
1189 static struct sys_device omap_gpio_device = {
1190 .id = 0,
1191 .cls = &omap_gpio_sysclass,
1192 };
1193 #endif
1194
1195 /*
1196 * This may get called early from board specific init
1197 * for boards that have interrupts routed via FPGA.
1198 */
1199 int omap_gpio_init(void)
1200 {
1201 if (!initialized)
1202 return _omap_gpio_init();
1203 else
1204 return 0;
1205 }
1206
1207 static int __init omap_gpio_sysinit(void)
1208 {
1209 int ret = 0;
1210
1211 if (!initialized)
1212 ret = _omap_gpio_init();
1213
1214 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1215 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1216 if (ret == 0) {
1217 ret = sysdev_class_register(&omap_gpio_sysclass);
1218 if (ret == 0)
1219 ret = sysdev_register(&omap_gpio_device);
1220 }
1221 }
1222 #endif
1223
1224 return ret;
1225 }
1226
1227 EXPORT_SYMBOL(omap_request_gpio);
1228 EXPORT_SYMBOL(omap_free_gpio);
1229 EXPORT_SYMBOL(omap_set_gpio_direction);
1230 EXPORT_SYMBOL(omap_set_gpio_dataout);
1231 EXPORT_SYMBOL(omap_get_gpio_datain);
1232
1233 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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