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ARM: OMAP: fix OMAP1 mpuio suspend/resume oops
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21
22 #include <asm/hardware.h>
23 #include <asm/irq.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
27
28 #include <asm/io.h>
29
30 /*
31 * OMAP1510 GPIO registers
32 */
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41
42 #define OMAP1510_IH_GPIO_BASE 64
43
44 /*
45 * OMAP1610 specific GPIO registers
46 */
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68
69 /*
70 * OMAP730 specific GPIO registers
71 */
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
84
85 /*
86 * omap24xx specific GPIO registers
87 */
88 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92
93 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
94 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
95 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
96 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
97 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98
99 #define OMAP24XX_GPIO_REVISION 0x0000
100 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
101 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
102 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
103 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
104 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
105 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
106 #define OMAP24XX_GPIO_CTRL 0x0030
107 #define OMAP24XX_GPIO_OE 0x0034
108 #define OMAP24XX_GPIO_DATAIN 0x0038
109 #define OMAP24XX_GPIO_DATAOUT 0x003c
110 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
113 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
120
121 struct gpio_bank {
122 void __iomem *base;
123 u16 irq;
124 u16 virtual_irq_start;
125 int method;
126 u32 reserved_map;
127 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
128 u32 suspend_wakeup;
129 u32 saved_wakeup;
130 #endif
131 #ifdef CONFIG_ARCH_OMAP24XX
132 u32 non_wakeup_gpios;
133 u32 enabled_non_wakeup_gpios;
134
135 u32 saved_datain;
136 u32 saved_fallingdetect;
137 u32 saved_risingdetect;
138 #endif
139 spinlock_t lock;
140 };
141
142 #define METHOD_MPUIO 0
143 #define METHOD_GPIO_1510 1
144 #define METHOD_GPIO_1610 2
145 #define METHOD_GPIO_730 3
146 #define METHOD_GPIO_24XX 4
147
148 #ifdef CONFIG_ARCH_OMAP16XX
149 static struct gpio_bank gpio_bank_1610[5] = {
150 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
151 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
152 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
153 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
154 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
155 };
156 #endif
157
158 #ifdef CONFIG_ARCH_OMAP15XX
159 static struct gpio_bank gpio_bank_1510[2] = {
160 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
161 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
162 };
163 #endif
164
165 #ifdef CONFIG_ARCH_OMAP730
166 static struct gpio_bank gpio_bank_730[7] = {
167 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
168 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
169 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
170 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
171 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
172 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
173 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
174 };
175 #endif
176
177 #ifdef CONFIG_ARCH_OMAP24XX
178
179 static struct gpio_bank gpio_bank_242x[4] = {
180 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
181 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
182 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
183 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
184 };
185
186 static struct gpio_bank gpio_bank_243x[5] = {
187 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
188 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
189 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
190 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
191 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
192 };
193
194 #endif
195
196 static struct gpio_bank *gpio_bank;
197 static int gpio_bank_count;
198
199 static inline struct gpio_bank *get_gpio_bank(int gpio)
200 {
201 #ifdef CONFIG_ARCH_OMAP15XX
202 if (cpu_is_omap15xx()) {
203 if (OMAP_GPIO_IS_MPUIO(gpio))
204 return &gpio_bank[0];
205 return &gpio_bank[1];
206 }
207 #endif
208 #if defined(CONFIG_ARCH_OMAP16XX)
209 if (cpu_is_omap16xx()) {
210 if (OMAP_GPIO_IS_MPUIO(gpio))
211 return &gpio_bank[0];
212 return &gpio_bank[1 + (gpio >> 4)];
213 }
214 #endif
215 #ifdef CONFIG_ARCH_OMAP730
216 if (cpu_is_omap730()) {
217 if (OMAP_GPIO_IS_MPUIO(gpio))
218 return &gpio_bank[0];
219 return &gpio_bank[1 + (gpio >> 5)];
220 }
221 #endif
222 #ifdef CONFIG_ARCH_OMAP24XX
223 if (cpu_is_omap24xx())
224 return &gpio_bank[gpio >> 5];
225 #endif
226 }
227
228 static inline int get_gpio_index(int gpio)
229 {
230 #ifdef CONFIG_ARCH_OMAP730
231 if (cpu_is_omap730())
232 return gpio & 0x1f;
233 #endif
234 #ifdef CONFIG_ARCH_OMAP24XX
235 if (cpu_is_omap24xx())
236 return gpio & 0x1f;
237 #endif
238 return gpio & 0x0f;
239 }
240
241 static inline int gpio_valid(int gpio)
242 {
243 if (gpio < 0)
244 return -1;
245 #ifndef CONFIG_ARCH_OMAP24XX
246 if (OMAP_GPIO_IS_MPUIO(gpio)) {
247 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
248 return -1;
249 return 0;
250 }
251 #endif
252 #ifdef CONFIG_ARCH_OMAP15XX
253 if (cpu_is_omap15xx() && gpio < 16)
254 return 0;
255 #endif
256 #if defined(CONFIG_ARCH_OMAP16XX)
257 if ((cpu_is_omap16xx()) && gpio < 64)
258 return 0;
259 #endif
260 #ifdef CONFIG_ARCH_OMAP730
261 if (cpu_is_omap730() && gpio < 192)
262 return 0;
263 #endif
264 #ifdef CONFIG_ARCH_OMAP24XX
265 if (cpu_is_omap24xx() && gpio < 128)
266 return 0;
267 #endif
268 return -1;
269 }
270
271 static int check_gpio(int gpio)
272 {
273 if (unlikely(gpio_valid(gpio)) < 0) {
274 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
275 dump_stack();
276 return -1;
277 }
278 return 0;
279 }
280
281 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
282 {
283 void __iomem *reg = bank->base;
284 u32 l;
285
286 switch (bank->method) {
287 #ifdef CONFIG_ARCH_OMAP1
288 case METHOD_MPUIO:
289 reg += OMAP_MPUIO_IO_CNTL;
290 break;
291 #endif
292 #ifdef CONFIG_ARCH_OMAP15XX
293 case METHOD_GPIO_1510:
294 reg += OMAP1510_GPIO_DIR_CONTROL;
295 break;
296 #endif
297 #ifdef CONFIG_ARCH_OMAP16XX
298 case METHOD_GPIO_1610:
299 reg += OMAP1610_GPIO_DIRECTION;
300 break;
301 #endif
302 #ifdef CONFIG_ARCH_OMAP730
303 case METHOD_GPIO_730:
304 reg += OMAP730_GPIO_DIR_CONTROL;
305 break;
306 #endif
307 #ifdef CONFIG_ARCH_OMAP24XX
308 case METHOD_GPIO_24XX:
309 reg += OMAP24XX_GPIO_OE;
310 break;
311 #endif
312 default:
313 WARN_ON(1);
314 return;
315 }
316 l = __raw_readl(reg);
317 if (is_input)
318 l |= 1 << gpio;
319 else
320 l &= ~(1 << gpio);
321 __raw_writel(l, reg);
322 }
323
324 void omap_set_gpio_direction(int gpio, int is_input)
325 {
326 struct gpio_bank *bank;
327
328 if (check_gpio(gpio) < 0)
329 return;
330 bank = get_gpio_bank(gpio);
331 spin_lock(&bank->lock);
332 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
333 spin_unlock(&bank->lock);
334 }
335
336 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
337 {
338 void __iomem *reg = bank->base;
339 u32 l = 0;
340
341 switch (bank->method) {
342 #ifdef CONFIG_ARCH_OMAP1
343 case METHOD_MPUIO:
344 reg += OMAP_MPUIO_OUTPUT;
345 l = __raw_readl(reg);
346 if (enable)
347 l |= 1 << gpio;
348 else
349 l &= ~(1 << gpio);
350 break;
351 #endif
352 #ifdef CONFIG_ARCH_OMAP15XX
353 case METHOD_GPIO_1510:
354 reg += OMAP1510_GPIO_DATA_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
361 #endif
362 #ifdef CONFIG_ARCH_OMAP16XX
363 case METHOD_GPIO_1610:
364 if (enable)
365 reg += OMAP1610_GPIO_SET_DATAOUT;
366 else
367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
368 l = 1 << gpio;
369 break;
370 #endif
371 #ifdef CONFIG_ARCH_OMAP730
372 case METHOD_GPIO_730:
373 reg += OMAP730_GPIO_DATA_OUTPUT;
374 l = __raw_readl(reg);
375 if (enable)
376 l |= 1 << gpio;
377 else
378 l &= ~(1 << gpio);
379 break;
380 #endif
381 #ifdef CONFIG_ARCH_OMAP24XX
382 case METHOD_GPIO_24XX:
383 if (enable)
384 reg += OMAP24XX_GPIO_SETDATAOUT;
385 else
386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
387 l = 1 << gpio;
388 break;
389 #endif
390 default:
391 WARN_ON(1);
392 return;
393 }
394 __raw_writel(l, reg);
395 }
396
397 void omap_set_gpio_dataout(int gpio, int enable)
398 {
399 struct gpio_bank *bank;
400
401 if (check_gpio(gpio) < 0)
402 return;
403 bank = get_gpio_bank(gpio);
404 spin_lock(&bank->lock);
405 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
406 spin_unlock(&bank->lock);
407 }
408
409 int omap_get_gpio_datain(int gpio)
410 {
411 struct gpio_bank *bank;
412 void __iomem *reg;
413
414 if (check_gpio(gpio) < 0)
415 return -EINVAL;
416 bank = get_gpio_bank(gpio);
417 reg = bank->base;
418 switch (bank->method) {
419 #ifdef CONFIG_ARCH_OMAP1
420 case METHOD_MPUIO:
421 reg += OMAP_MPUIO_INPUT_LATCH;
422 break;
423 #endif
424 #ifdef CONFIG_ARCH_OMAP15XX
425 case METHOD_GPIO_1510:
426 reg += OMAP1510_GPIO_DATA_INPUT;
427 break;
428 #endif
429 #ifdef CONFIG_ARCH_OMAP16XX
430 case METHOD_GPIO_1610:
431 reg += OMAP1610_GPIO_DATAIN;
432 break;
433 #endif
434 #ifdef CONFIG_ARCH_OMAP730
435 case METHOD_GPIO_730:
436 reg += OMAP730_GPIO_DATA_INPUT;
437 break;
438 #endif
439 #ifdef CONFIG_ARCH_OMAP24XX
440 case METHOD_GPIO_24XX:
441 reg += OMAP24XX_GPIO_DATAIN;
442 break;
443 #endif
444 default:
445 return -EINVAL;
446 }
447 return (__raw_readl(reg)
448 & (1 << get_gpio_index(gpio))) != 0;
449 }
450
451 #define MOD_REG_BIT(reg, bit_mask, set) \
452 do { \
453 int l = __raw_readl(base + reg); \
454 if (set) l |= bit_mask; \
455 else l &= ~bit_mask; \
456 __raw_writel(l, base + reg); \
457 } while(0)
458
459 #ifdef CONFIG_ARCH_OMAP24XX
460 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
461 {
462 void __iomem *base = bank->base;
463 u32 gpio_bit = 1 << gpio;
464
465 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
466 trigger & __IRQT_LOWLVL);
467 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
468 trigger & __IRQT_HIGHLVL);
469 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
470 trigger & __IRQT_RISEDGE);
471 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
472 trigger & __IRQT_FALEDGE);
473 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
474 if (trigger != 0)
475 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
476 else
477 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
478 } else {
479 if (trigger != 0)
480 bank->enabled_non_wakeup_gpios |= gpio_bit;
481 else
482 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
483 }
484 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
485 * triggering requested. */
486 }
487 #endif
488
489 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
490 {
491 void __iomem *reg = bank->base;
492 u32 l = 0;
493
494 switch (bank->method) {
495 #ifdef CONFIG_ARCH_OMAP1
496 case METHOD_MPUIO:
497 reg += OMAP_MPUIO_GPIO_INT_EDGE;
498 l = __raw_readl(reg);
499 if (trigger & __IRQT_RISEDGE)
500 l |= 1 << gpio;
501 else if (trigger & __IRQT_FALEDGE)
502 l &= ~(1 << gpio);
503 else
504 goto bad;
505 break;
506 #endif
507 #ifdef CONFIG_ARCH_OMAP15XX
508 case METHOD_GPIO_1510:
509 reg += OMAP1510_GPIO_INT_CONTROL;
510 l = __raw_readl(reg);
511 if (trigger & __IRQT_RISEDGE)
512 l |= 1 << gpio;
513 else if (trigger & __IRQT_FALEDGE)
514 l &= ~(1 << gpio);
515 else
516 goto bad;
517 break;
518 #endif
519 #ifdef CONFIG_ARCH_OMAP16XX
520 case METHOD_GPIO_1610:
521 if (gpio & 0x08)
522 reg += OMAP1610_GPIO_EDGE_CTRL2;
523 else
524 reg += OMAP1610_GPIO_EDGE_CTRL1;
525 gpio &= 0x07;
526 l = __raw_readl(reg);
527 l &= ~(3 << (gpio << 1));
528 if (trigger & __IRQT_RISEDGE)
529 l |= 2 << (gpio << 1);
530 if (trigger & __IRQT_FALEDGE)
531 l |= 1 << (gpio << 1);
532 if (trigger)
533 /* Enable wake-up during idle for dynamic tick */
534 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
535 else
536 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
537 break;
538 #endif
539 #ifdef CONFIG_ARCH_OMAP730
540 case METHOD_GPIO_730:
541 reg += OMAP730_GPIO_INT_CONTROL;
542 l = __raw_readl(reg);
543 if (trigger & __IRQT_RISEDGE)
544 l |= 1 << gpio;
545 else if (trigger & __IRQT_FALEDGE)
546 l &= ~(1 << gpio);
547 else
548 goto bad;
549 break;
550 #endif
551 #ifdef CONFIG_ARCH_OMAP24XX
552 case METHOD_GPIO_24XX:
553 set_24xx_gpio_triggering(bank, gpio, trigger);
554 break;
555 #endif
556 default:
557 goto bad;
558 }
559 __raw_writel(l, reg);
560 return 0;
561 bad:
562 return -EINVAL;
563 }
564
565 static int gpio_irq_type(unsigned irq, unsigned type)
566 {
567 struct gpio_bank *bank;
568 unsigned gpio;
569 int retval;
570
571 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
572 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
573 else
574 gpio = irq - IH_GPIO_BASE;
575
576 if (check_gpio(gpio) < 0)
577 return -EINVAL;
578
579 if (type & ~IRQ_TYPE_SENSE_MASK)
580 return -EINVAL;
581
582 /* OMAP1 allows only only edge triggering */
583 if (!cpu_is_omap24xx()
584 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
585 return -EINVAL;
586
587 bank = get_irq_chip_data(irq);
588 spin_lock(&bank->lock);
589 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
590 if (retval == 0) {
591 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
592 irq_desc[irq].status |= type;
593 }
594 spin_unlock(&bank->lock);
595 return retval;
596 }
597
598 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
599 {
600 void __iomem *reg = bank->base;
601
602 switch (bank->method) {
603 #ifdef CONFIG_ARCH_OMAP1
604 case METHOD_MPUIO:
605 /* MPUIO irqstatus is reset by reading the status register,
606 * so do nothing here */
607 return;
608 #endif
609 #ifdef CONFIG_ARCH_OMAP15XX
610 case METHOD_GPIO_1510:
611 reg += OMAP1510_GPIO_INT_STATUS;
612 break;
613 #endif
614 #ifdef CONFIG_ARCH_OMAP16XX
615 case METHOD_GPIO_1610:
616 reg += OMAP1610_GPIO_IRQSTATUS1;
617 break;
618 #endif
619 #ifdef CONFIG_ARCH_OMAP730
620 case METHOD_GPIO_730:
621 reg += OMAP730_GPIO_INT_STATUS;
622 break;
623 #endif
624 #ifdef CONFIG_ARCH_OMAP24XX
625 case METHOD_GPIO_24XX:
626 reg += OMAP24XX_GPIO_IRQSTATUS1;
627 break;
628 #endif
629 default:
630 WARN_ON(1);
631 return;
632 }
633 __raw_writel(gpio_mask, reg);
634
635 /* Workaround for clearing DSP GPIO interrupts to allow retention */
636 if (cpu_is_omap2420())
637 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
638 }
639
640 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
641 {
642 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
643 }
644
645 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
646 {
647 void __iomem *reg = bank->base;
648 int inv = 0;
649 u32 l;
650 u32 mask;
651
652 switch (bank->method) {
653 #ifdef CONFIG_ARCH_OMAP1
654 case METHOD_MPUIO:
655 reg += OMAP_MPUIO_GPIO_MASKIT;
656 mask = 0xffff;
657 inv = 1;
658 break;
659 #endif
660 #ifdef CONFIG_ARCH_OMAP15XX
661 case METHOD_GPIO_1510:
662 reg += OMAP1510_GPIO_INT_MASK;
663 mask = 0xffff;
664 inv = 1;
665 break;
666 #endif
667 #ifdef CONFIG_ARCH_OMAP16XX
668 case METHOD_GPIO_1610:
669 reg += OMAP1610_GPIO_IRQENABLE1;
670 mask = 0xffff;
671 break;
672 #endif
673 #ifdef CONFIG_ARCH_OMAP730
674 case METHOD_GPIO_730:
675 reg += OMAP730_GPIO_INT_MASK;
676 mask = 0xffffffff;
677 inv = 1;
678 break;
679 #endif
680 #ifdef CONFIG_ARCH_OMAP24XX
681 case METHOD_GPIO_24XX:
682 reg += OMAP24XX_GPIO_IRQENABLE1;
683 mask = 0xffffffff;
684 break;
685 #endif
686 default:
687 WARN_ON(1);
688 return 0;
689 }
690
691 l = __raw_readl(reg);
692 if (inv)
693 l = ~l;
694 l &= mask;
695 return l;
696 }
697
698 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
699 {
700 void __iomem *reg = bank->base;
701 u32 l;
702
703 switch (bank->method) {
704 #ifdef CONFIG_ARCH_OMAP1
705 case METHOD_MPUIO:
706 reg += OMAP_MPUIO_GPIO_MASKIT;
707 l = __raw_readl(reg);
708 if (enable)
709 l &= ~(gpio_mask);
710 else
711 l |= gpio_mask;
712 break;
713 #endif
714 #ifdef CONFIG_ARCH_OMAP15XX
715 case METHOD_GPIO_1510:
716 reg += OMAP1510_GPIO_INT_MASK;
717 l = __raw_readl(reg);
718 if (enable)
719 l &= ~(gpio_mask);
720 else
721 l |= gpio_mask;
722 break;
723 #endif
724 #ifdef CONFIG_ARCH_OMAP16XX
725 case METHOD_GPIO_1610:
726 if (enable)
727 reg += OMAP1610_GPIO_SET_IRQENABLE1;
728 else
729 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
730 l = gpio_mask;
731 break;
732 #endif
733 #ifdef CONFIG_ARCH_OMAP730
734 case METHOD_GPIO_730:
735 reg += OMAP730_GPIO_INT_MASK;
736 l = __raw_readl(reg);
737 if (enable)
738 l &= ~(gpio_mask);
739 else
740 l |= gpio_mask;
741 break;
742 #endif
743 #ifdef CONFIG_ARCH_OMAP24XX
744 case METHOD_GPIO_24XX:
745 if (enable)
746 reg += OMAP24XX_GPIO_SETIRQENABLE1;
747 else
748 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
749 l = gpio_mask;
750 break;
751 #endif
752 default:
753 WARN_ON(1);
754 return;
755 }
756 __raw_writel(l, reg);
757 }
758
759 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
760 {
761 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
762 }
763
764 /*
765 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
766 * 1510 does not seem to have a wake-up register. If JTAG is connected
767 * to the target, system will wake up always on GPIO events. While
768 * system is running all registered GPIO interrupts need to have wake-up
769 * enabled. When system is suspended, only selected GPIO interrupts need
770 * to have wake-up enabled.
771 */
772 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
773 {
774 switch (bank->method) {
775 #ifdef CONFIG_ARCH_OMAP16XX
776 case METHOD_MPUIO:
777 case METHOD_GPIO_1610:
778 spin_lock(&bank->lock);
779 if (enable) {
780 bank->suspend_wakeup |= (1 << gpio);
781 enable_irq_wake(bank->irq);
782 } else {
783 disable_irq_wake(bank->irq);
784 bank->suspend_wakeup &= ~(1 << gpio);
785 }
786 spin_unlock(&bank->lock);
787 return 0;
788 #endif
789 #ifdef CONFIG_ARCH_OMAP24XX
790 case METHOD_GPIO_24XX:
791 if (bank->non_wakeup_gpios & (1 << gpio)) {
792 printk(KERN_ERR "Unable to modify wakeup on "
793 "non-wakeup GPIO%d\n",
794 (bank - gpio_bank) * 32 + gpio);
795 return -EINVAL;
796 }
797 spin_lock(&bank->lock);
798 if (enable) {
799 bank->suspend_wakeup |= (1 << gpio);
800 enable_irq_wake(bank->irq);
801 } else {
802 disable_irq_wake(bank->irq);
803 bank->suspend_wakeup &= ~(1 << gpio);
804 }
805 spin_unlock(&bank->lock);
806 return 0;
807 #endif
808 default:
809 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
810 bank->method);
811 return -EINVAL;
812 }
813 }
814
815 static void _reset_gpio(struct gpio_bank *bank, int gpio)
816 {
817 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
818 _set_gpio_irqenable(bank, gpio, 0);
819 _clear_gpio_irqstatus(bank, gpio);
820 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
821 }
822
823 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
824 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
825 {
826 unsigned int gpio = irq - IH_GPIO_BASE;
827 struct gpio_bank *bank;
828 int retval;
829
830 if (check_gpio(gpio) < 0)
831 return -ENODEV;
832 bank = get_irq_chip_data(irq);
833 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
834
835 return retval;
836 }
837
838 int omap_request_gpio(int gpio)
839 {
840 struct gpio_bank *bank;
841
842 if (check_gpio(gpio) < 0)
843 return -EINVAL;
844
845 bank = get_gpio_bank(gpio);
846 spin_lock(&bank->lock);
847 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
848 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
849 dump_stack();
850 spin_unlock(&bank->lock);
851 return -1;
852 }
853 bank->reserved_map |= (1 << get_gpio_index(gpio));
854
855 /* Set trigger to none. You need to enable the desired trigger with
856 * request_irq() or set_irq_type().
857 */
858 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
859
860 #ifdef CONFIG_ARCH_OMAP15XX
861 if (bank->method == METHOD_GPIO_1510) {
862 void __iomem *reg;
863
864 /* Claim the pin for MPU */
865 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
866 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
867 }
868 #endif
869 spin_unlock(&bank->lock);
870
871 return 0;
872 }
873
874 void omap_free_gpio(int gpio)
875 {
876 struct gpio_bank *bank;
877
878 if (check_gpio(gpio) < 0)
879 return;
880 bank = get_gpio_bank(gpio);
881 spin_lock(&bank->lock);
882 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
883 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
884 dump_stack();
885 spin_unlock(&bank->lock);
886 return;
887 }
888 #ifdef CONFIG_ARCH_OMAP16XX
889 if (bank->method == METHOD_GPIO_1610) {
890 /* Disable wake-up during idle for dynamic tick */
891 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
892 __raw_writel(1 << get_gpio_index(gpio), reg);
893 }
894 #endif
895 #ifdef CONFIG_ARCH_OMAP24XX
896 if (bank->method == METHOD_GPIO_24XX) {
897 /* Disable wake-up during idle for dynamic tick */
898 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
899 __raw_writel(1 << get_gpio_index(gpio), reg);
900 }
901 #endif
902 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
903 _reset_gpio(bank, gpio);
904 spin_unlock(&bank->lock);
905 }
906
907 /*
908 * We need to unmask the GPIO bank interrupt as soon as possible to
909 * avoid missing GPIO interrupts for other lines in the bank.
910 * Then we need to mask-read-clear-unmask the triggered GPIO lines
911 * in the bank to avoid missing nested interrupts for a GPIO line.
912 * If we wait to unmask individual GPIO lines in the bank after the
913 * line's interrupt handler has been run, we may miss some nested
914 * interrupts.
915 */
916 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
917 {
918 void __iomem *isr_reg = NULL;
919 u32 isr;
920 unsigned int gpio_irq;
921 struct gpio_bank *bank;
922 u32 retrigger = 0;
923 int unmasked = 0;
924
925 desc->chip->ack(irq);
926
927 bank = get_irq_data(irq);
928 #ifdef CONFIG_ARCH_OMAP1
929 if (bank->method == METHOD_MPUIO)
930 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
931 #endif
932 #ifdef CONFIG_ARCH_OMAP15XX
933 if (bank->method == METHOD_GPIO_1510)
934 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
935 #endif
936 #if defined(CONFIG_ARCH_OMAP16XX)
937 if (bank->method == METHOD_GPIO_1610)
938 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
939 #endif
940 #ifdef CONFIG_ARCH_OMAP730
941 if (bank->method == METHOD_GPIO_730)
942 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
943 #endif
944 #ifdef CONFIG_ARCH_OMAP24XX
945 if (bank->method == METHOD_GPIO_24XX)
946 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
947 #endif
948 while(1) {
949 u32 isr_saved, level_mask = 0;
950 u32 enabled;
951
952 enabled = _get_gpio_irqbank_mask(bank);
953 isr_saved = isr = __raw_readl(isr_reg) & enabled;
954
955 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
956 isr &= 0x0000ffff;
957
958 if (cpu_is_omap24xx()) {
959 level_mask =
960 __raw_readl(bank->base +
961 OMAP24XX_GPIO_LEVELDETECT0) |
962 __raw_readl(bank->base +
963 OMAP24XX_GPIO_LEVELDETECT1);
964 level_mask &= enabled;
965 }
966
967 /* clear edge sensitive interrupts before handler(s) are
968 called so that we don't miss any interrupt occurred while
969 executing them */
970 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
971 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
972 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
973
974 /* if there is only edge sensitive GPIO pin interrupts
975 configured, we could unmask GPIO bank interrupt immediately */
976 if (!level_mask && !unmasked) {
977 unmasked = 1;
978 desc->chip->unmask(irq);
979 }
980
981 isr |= retrigger;
982 retrigger = 0;
983 if (!isr)
984 break;
985
986 gpio_irq = bank->virtual_irq_start;
987 for (; isr != 0; isr >>= 1, gpio_irq++) {
988 struct irq_desc *d;
989 int irq_mask;
990 if (!(isr & 1))
991 continue;
992 d = irq_desc + gpio_irq;
993 /* Don't run the handler if it's already running
994 * or was disabled lazely.
995 */
996 if (unlikely((d->depth ||
997 (d->status & IRQ_INPROGRESS)))) {
998 irq_mask = 1 <<
999 (gpio_irq - bank->virtual_irq_start);
1000 /* The unmasking will be done by
1001 * enable_irq in case it is disabled or
1002 * after returning from the handler if
1003 * it's already running.
1004 */
1005 _enable_gpio_irqbank(bank, irq_mask, 0);
1006 if (!d->depth) {
1007 /* Level triggered interrupts
1008 * won't ever be reentered
1009 */
1010 BUG_ON(level_mask & irq_mask);
1011 d->status |= IRQ_PENDING;
1012 }
1013 continue;
1014 }
1015
1016 desc_handle_irq(gpio_irq, d);
1017
1018 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1019 irq_mask = 1 <<
1020 (gpio_irq - bank->virtual_irq_start);
1021 d->status &= ~IRQ_PENDING;
1022 _enable_gpio_irqbank(bank, irq_mask, 1);
1023 retrigger |= irq_mask;
1024 }
1025 }
1026
1027 if (cpu_is_omap24xx()) {
1028 /* clear level sensitive interrupts after handler(s) */
1029 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1030 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1031 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1032 }
1033
1034 }
1035 /* if bank has any level sensitive GPIO pin interrupt
1036 configured, we must unmask the bank interrupt only after
1037 handler(s) are executed in order to avoid spurious bank
1038 interrupt */
1039 if (!unmasked)
1040 desc->chip->unmask(irq);
1041
1042 }
1043
1044 static void gpio_irq_shutdown(unsigned int irq)
1045 {
1046 unsigned int gpio = irq - IH_GPIO_BASE;
1047 struct gpio_bank *bank = get_irq_chip_data(irq);
1048
1049 _reset_gpio(bank, gpio);
1050 }
1051
1052 static void gpio_ack_irq(unsigned int irq)
1053 {
1054 unsigned int gpio = irq - IH_GPIO_BASE;
1055 struct gpio_bank *bank = get_irq_chip_data(irq);
1056
1057 _clear_gpio_irqstatus(bank, gpio);
1058 }
1059
1060 static void gpio_mask_irq(unsigned int irq)
1061 {
1062 unsigned int gpio = irq - IH_GPIO_BASE;
1063 struct gpio_bank *bank = get_irq_chip_data(irq);
1064
1065 _set_gpio_irqenable(bank, gpio, 0);
1066 }
1067
1068 static void gpio_unmask_irq(unsigned int irq)
1069 {
1070 unsigned int gpio = irq - IH_GPIO_BASE;
1071 unsigned int gpio_idx = get_gpio_index(gpio);
1072 struct gpio_bank *bank = get_irq_chip_data(irq);
1073
1074 _set_gpio_irqenable(bank, gpio_idx, 1);
1075 }
1076
1077 static struct irq_chip gpio_irq_chip = {
1078 .name = "GPIO",
1079 .shutdown = gpio_irq_shutdown,
1080 .ack = gpio_ack_irq,
1081 .mask = gpio_mask_irq,
1082 .unmask = gpio_unmask_irq,
1083 .set_type = gpio_irq_type,
1084 .set_wake = gpio_wake_enable,
1085 };
1086
1087 /*---------------------------------------------------------------------*/
1088
1089 #ifdef CONFIG_ARCH_OMAP1
1090
1091 /* MPUIO uses the always-on 32k clock */
1092
1093 static void mpuio_ack_irq(unsigned int irq)
1094 {
1095 /* The ISR is reset automatically, so do nothing here. */
1096 }
1097
1098 static void mpuio_mask_irq(unsigned int irq)
1099 {
1100 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1101 struct gpio_bank *bank = get_irq_chip_data(irq);
1102
1103 _set_gpio_irqenable(bank, gpio, 0);
1104 }
1105
1106 static void mpuio_unmask_irq(unsigned int irq)
1107 {
1108 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1109 struct gpio_bank *bank = get_irq_chip_data(irq);
1110
1111 _set_gpio_irqenable(bank, gpio, 1);
1112 }
1113
1114 static struct irq_chip mpuio_irq_chip = {
1115 .name = "MPUIO",
1116 .ack = mpuio_ack_irq,
1117 .mask = mpuio_mask_irq,
1118 .unmask = mpuio_unmask_irq,
1119 .set_type = gpio_irq_type,
1120 #ifdef CONFIG_ARCH_OMAP16XX
1121 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1122 .set_wake = gpio_wake_enable,
1123 #endif
1124 };
1125
1126
1127 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1128
1129
1130 #ifdef CONFIG_ARCH_OMAP16XX
1131
1132 #include <linux/platform_device.h>
1133
1134 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1135 {
1136 struct gpio_bank *bank = platform_get_drvdata(pdev);
1137 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1138
1139 spin_lock(&bank->lock);
1140 bank->saved_wakeup = __raw_readl(mask_reg);
1141 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1142 spin_unlock(&bank->lock);
1143
1144 return 0;
1145 }
1146
1147 static int omap_mpuio_resume_early(struct platform_device *pdev)
1148 {
1149 struct gpio_bank *bank = platform_get_drvdata(pdev);
1150 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1151
1152 spin_lock(&bank->lock);
1153 __raw_writel(bank->saved_wakeup, mask_reg);
1154 spin_unlock(&bank->lock);
1155
1156 return 0;
1157 }
1158
1159 /* use platform_driver for this, now that there's no longer any
1160 * point to sys_device (other than not disturbing old code).
1161 */
1162 static struct platform_driver omap_mpuio_driver = {
1163 .suspend_late = omap_mpuio_suspend_late,
1164 .resume_early = omap_mpuio_resume_early,
1165 .driver = {
1166 .name = "mpuio",
1167 },
1168 };
1169
1170 static struct platform_device omap_mpuio_device = {
1171 .name = "mpuio",
1172 .id = -1,
1173 .dev = {
1174 .driver = &omap_mpuio_driver.driver,
1175 }
1176 /* could list the /proc/iomem resources */
1177 };
1178
1179 static inline void mpuio_init(void)
1180 {
1181 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1182
1183 if (platform_driver_register(&omap_mpuio_driver) == 0)
1184 (void) platform_device_register(&omap_mpuio_device);
1185 }
1186
1187 #else
1188 static inline void mpuio_init(void) {}
1189 #endif /* 16xx */
1190
1191 #else
1192
1193 extern struct irq_chip mpuio_irq_chip;
1194
1195 #define bank_is_mpuio(bank) 0
1196 static inline void mpuio_init(void) {}
1197
1198 #endif
1199
1200 /*---------------------------------------------------------------------*/
1201
1202 static int initialized;
1203 static struct clk * gpio_ick;
1204 static struct clk * gpio_fck;
1205
1206 #ifdef CONFIG_ARCH_OMAP2430
1207 static struct clk * gpio5_ick;
1208 static struct clk * gpio5_fck;
1209 #endif
1210
1211 static int __init _omap_gpio_init(void)
1212 {
1213 int i;
1214 struct gpio_bank *bank;
1215
1216 initialized = 1;
1217
1218 if (cpu_is_omap15xx()) {
1219 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1220 if (IS_ERR(gpio_ick))
1221 printk("Could not get arm_gpio_ck\n");
1222 else
1223 clk_enable(gpio_ick);
1224 }
1225 if (cpu_is_omap24xx()) {
1226 gpio_ick = clk_get(NULL, "gpios_ick");
1227 if (IS_ERR(gpio_ick))
1228 printk("Could not get gpios_ick\n");
1229 else
1230 clk_enable(gpio_ick);
1231 gpio_fck = clk_get(NULL, "gpios_fck");
1232 if (IS_ERR(gpio_fck))
1233 printk("Could not get gpios_fck\n");
1234 else
1235 clk_enable(gpio_fck);
1236
1237 /*
1238 * On 2430 GPIO 5 uses CORE L4 ICLK
1239 */
1240 #ifdef CONFIG_ARCH_OMAP2430
1241 if (cpu_is_omap2430()) {
1242 gpio5_ick = clk_get(NULL, "gpio5_ick");
1243 if (IS_ERR(gpio5_ick))
1244 printk("Could not get gpio5_ick\n");
1245 else
1246 clk_enable(gpio5_ick);
1247 gpio5_fck = clk_get(NULL, "gpio5_fck");
1248 if (IS_ERR(gpio5_fck))
1249 printk("Could not get gpio5_fck\n");
1250 else
1251 clk_enable(gpio5_fck);
1252 }
1253 #endif
1254 }
1255
1256 #ifdef CONFIG_ARCH_OMAP15XX
1257 if (cpu_is_omap15xx()) {
1258 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1259 gpio_bank_count = 2;
1260 gpio_bank = gpio_bank_1510;
1261 }
1262 #endif
1263 #if defined(CONFIG_ARCH_OMAP16XX)
1264 if (cpu_is_omap16xx()) {
1265 u32 rev;
1266
1267 gpio_bank_count = 5;
1268 gpio_bank = gpio_bank_1610;
1269 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1270 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1271 (rev >> 4) & 0x0f, rev & 0x0f);
1272 }
1273 #endif
1274 #ifdef CONFIG_ARCH_OMAP730
1275 if (cpu_is_omap730()) {
1276 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1277 gpio_bank_count = 7;
1278 gpio_bank = gpio_bank_730;
1279 }
1280 #endif
1281
1282 #ifdef CONFIG_ARCH_OMAP24XX
1283 if (cpu_is_omap242x()) {
1284 int rev;
1285
1286 gpio_bank_count = 4;
1287 gpio_bank = gpio_bank_242x;
1288 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1289 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1290 (rev >> 4) & 0x0f, rev & 0x0f);
1291 }
1292 if (cpu_is_omap243x()) {
1293 int rev;
1294
1295 gpio_bank_count = 5;
1296 gpio_bank = gpio_bank_243x;
1297 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1298 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1299 (rev >> 4) & 0x0f, rev & 0x0f);
1300 }
1301 #endif
1302 for (i = 0; i < gpio_bank_count; i++) {
1303 int j, gpio_count = 16;
1304
1305 bank = &gpio_bank[i];
1306 bank->reserved_map = 0;
1307 bank->base = IO_ADDRESS(bank->base);
1308 spin_lock_init(&bank->lock);
1309 if (bank_is_mpuio(bank))
1310 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1311 #ifdef CONFIG_ARCH_OMAP15XX
1312 if (bank->method == METHOD_GPIO_1510) {
1313 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1314 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1315 }
1316 #endif
1317 #if defined(CONFIG_ARCH_OMAP16XX)
1318 if (bank->method == METHOD_GPIO_1610) {
1319 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1320 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1321 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1322 }
1323 #endif
1324 #ifdef CONFIG_ARCH_OMAP730
1325 if (bank->method == METHOD_GPIO_730) {
1326 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1327 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1328
1329 gpio_count = 32; /* 730 has 32-bit GPIOs */
1330 }
1331 #endif
1332 #ifdef CONFIG_ARCH_OMAP24XX
1333 if (bank->method == METHOD_GPIO_24XX) {
1334 static const u32 non_wakeup_gpios[] = {
1335 0xe203ffc0, 0x08700040
1336 };
1337
1338 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1339 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1340 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1341
1342 /* Initialize interface clock ungated, module enabled */
1343 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1344 if (i < ARRAY_SIZE(non_wakeup_gpios))
1345 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1346 gpio_count = 32;
1347 }
1348 #endif
1349 for (j = bank->virtual_irq_start;
1350 j < bank->virtual_irq_start + gpio_count; j++) {
1351 set_irq_chip_data(j, bank);
1352 if (bank_is_mpuio(bank))
1353 set_irq_chip(j, &mpuio_irq_chip);
1354 else
1355 set_irq_chip(j, &gpio_irq_chip);
1356 set_irq_handler(j, handle_simple_irq);
1357 set_irq_flags(j, IRQF_VALID);
1358 }
1359 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1360 set_irq_data(bank->irq, bank);
1361 }
1362
1363 /* Enable system clock for GPIO module.
1364 * The CAM_CLK_CTRL *is* really the right place. */
1365 if (cpu_is_omap16xx())
1366 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1367
1368 #ifdef CONFIG_ARCH_OMAP24XX
1369 /* Enable autoidle for the OCP interface */
1370 if (cpu_is_omap24xx())
1371 omap_writel(1 << 0, 0x48019010);
1372 #endif
1373
1374 return 0;
1375 }
1376
1377 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1378 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1379 {
1380 int i;
1381
1382 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1383 return 0;
1384
1385 for (i = 0; i < gpio_bank_count; i++) {
1386 struct gpio_bank *bank = &gpio_bank[i];
1387 void __iomem *wake_status;
1388 void __iomem *wake_clear;
1389 void __iomem *wake_set;
1390
1391 switch (bank->method) {
1392 #ifdef CONFIG_ARCH_OMAP16XX
1393 case METHOD_GPIO_1610:
1394 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1395 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1396 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1397 break;
1398 #endif
1399 #ifdef CONFIG_ARCH_OMAP24XX
1400 case METHOD_GPIO_24XX:
1401 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1402 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1403 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1404 break;
1405 #endif
1406 default:
1407 continue;
1408 }
1409
1410 spin_lock(&bank->lock);
1411 bank->saved_wakeup = __raw_readl(wake_status);
1412 __raw_writel(0xffffffff, wake_clear);
1413 __raw_writel(bank->suspend_wakeup, wake_set);
1414 spin_unlock(&bank->lock);
1415 }
1416
1417 return 0;
1418 }
1419
1420 static int omap_gpio_resume(struct sys_device *dev)
1421 {
1422 int i;
1423
1424 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1425 return 0;
1426
1427 for (i = 0; i < gpio_bank_count; i++) {
1428 struct gpio_bank *bank = &gpio_bank[i];
1429 void __iomem *wake_clear;
1430 void __iomem *wake_set;
1431
1432 switch (bank->method) {
1433 #ifdef CONFIG_ARCH_OMAP16XX
1434 case METHOD_GPIO_1610:
1435 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1436 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1437 break;
1438 #endif
1439 #ifdef CONFIG_ARCH_OMAP24XX
1440 case METHOD_GPIO_24XX:
1441 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1442 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1443 break;
1444 #endif
1445 default:
1446 continue;
1447 }
1448
1449 spin_lock(&bank->lock);
1450 __raw_writel(0xffffffff, wake_clear);
1451 __raw_writel(bank->saved_wakeup, wake_set);
1452 spin_unlock(&bank->lock);
1453 }
1454
1455 return 0;
1456 }
1457
1458 static struct sysdev_class omap_gpio_sysclass = {
1459 set_kset_name("gpio"),
1460 .suspend = omap_gpio_suspend,
1461 .resume = omap_gpio_resume,
1462 };
1463
1464 static struct sys_device omap_gpio_device = {
1465 .id = 0,
1466 .cls = &omap_gpio_sysclass,
1467 };
1468
1469 #endif
1470
1471 #ifdef CONFIG_ARCH_OMAP24XX
1472
1473 static int workaround_enabled;
1474
1475 void omap2_gpio_prepare_for_retention(void)
1476 {
1477 int i, c = 0;
1478
1479 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1480 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1481 for (i = 0; i < gpio_bank_count; i++) {
1482 struct gpio_bank *bank = &gpio_bank[i];
1483 u32 l1, l2;
1484
1485 if (!(bank->enabled_non_wakeup_gpios))
1486 continue;
1487 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1488 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1489 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1490 bank->saved_fallingdetect = l1;
1491 bank->saved_risingdetect = l2;
1492 l1 &= ~bank->enabled_non_wakeup_gpios;
1493 l2 &= ~bank->enabled_non_wakeup_gpios;
1494 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1495 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1496 c++;
1497 }
1498 if (!c) {
1499 workaround_enabled = 0;
1500 return;
1501 }
1502 workaround_enabled = 1;
1503 }
1504
1505 void omap2_gpio_resume_after_retention(void)
1506 {
1507 int i;
1508
1509 if (!workaround_enabled)
1510 return;
1511 for (i = 0; i < gpio_bank_count; i++) {
1512 struct gpio_bank *bank = &gpio_bank[i];
1513 u32 l;
1514
1515 if (!(bank->enabled_non_wakeup_gpios))
1516 continue;
1517 __raw_writel(bank->saved_fallingdetect,
1518 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1519 __raw_writel(bank->saved_risingdetect,
1520 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1521 /* Check if any of the non-wakeup interrupt GPIOs have changed
1522 * state. If so, generate an IRQ by software. This is
1523 * horribly racy, but it's the best we can do to work around
1524 * this silicon bug. */
1525 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1526 l ^= bank->saved_datain;
1527 l &= bank->non_wakeup_gpios;
1528 if (l) {
1529 u32 old0, old1;
1530
1531 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1532 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1533 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1534 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1535 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1536 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1537 }
1538 }
1539
1540 }
1541
1542 #endif
1543
1544 /*
1545 * This may get called early from board specific init
1546 * for boards that have interrupts routed via FPGA.
1547 */
1548 int omap_gpio_init(void)
1549 {
1550 if (!initialized)
1551 return _omap_gpio_init();
1552 else
1553 return 0;
1554 }
1555
1556 static int __init omap_gpio_sysinit(void)
1557 {
1558 int ret = 0;
1559
1560 if (!initialized)
1561 ret = _omap_gpio_init();
1562
1563 mpuio_init();
1564
1565 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1566 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1567 if (ret == 0) {
1568 ret = sysdev_class_register(&omap_gpio_sysclass);
1569 if (ret == 0)
1570 ret = sysdev_register(&omap_gpio_device);
1571 }
1572 }
1573 #endif
1574
1575 return ret;
1576 }
1577
1578 EXPORT_SYMBOL(omap_request_gpio);
1579 EXPORT_SYMBOL(omap_free_gpio);
1580 EXPORT_SYMBOL(omap_set_gpio_direction);
1581 EXPORT_SYMBOL(omap_set_gpio_dataout);
1582 EXPORT_SYMBOL(omap_get_gpio_datain);
1583
1584 arch_initcall(omap_gpio_sysinit);
1585
1586
1587 #ifdef CONFIG_DEBUG_FS
1588
1589 #include <linux/debugfs.h>
1590 #include <linux/seq_file.h>
1591
1592 static int gpio_is_input(struct gpio_bank *bank, int mask)
1593 {
1594 void __iomem *reg = bank->base;
1595
1596 switch (bank->method) {
1597 case METHOD_MPUIO:
1598 reg += OMAP_MPUIO_IO_CNTL;
1599 break;
1600 case METHOD_GPIO_1510:
1601 reg += OMAP1510_GPIO_DIR_CONTROL;
1602 break;
1603 case METHOD_GPIO_1610:
1604 reg += OMAP1610_GPIO_DIRECTION;
1605 break;
1606 case METHOD_GPIO_730:
1607 reg += OMAP730_GPIO_DIR_CONTROL;
1608 break;
1609 case METHOD_GPIO_24XX:
1610 reg += OMAP24XX_GPIO_OE;
1611 break;
1612 }
1613 return __raw_readl(reg) & mask;
1614 }
1615
1616
1617 static int dbg_gpio_show(struct seq_file *s, void *unused)
1618 {
1619 unsigned i, j, gpio;
1620
1621 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1622 struct gpio_bank *bank = gpio_bank + i;
1623 unsigned bankwidth = 16;
1624 u32 mask = 1;
1625
1626 if (bank_is_mpuio(bank))
1627 gpio = OMAP_MPUIO(0);
1628 else if (cpu_is_omap24xx() || cpu_is_omap730())
1629 bankwidth = 32;
1630
1631 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1632 unsigned irq, value, is_in, irqstat;
1633
1634 if (!(bank->reserved_map & mask))
1635 continue;
1636
1637 irq = bank->virtual_irq_start + j;
1638 value = omap_get_gpio_datain(gpio);
1639 is_in = gpio_is_input(bank, mask);
1640
1641 if (bank_is_mpuio(bank))
1642 seq_printf(s, "MPUIO %2d: ", j);
1643 else
1644 seq_printf(s, "GPIO %3d: ", gpio);
1645 seq_printf(s, "%s %s",
1646 is_in ? "in " : "out",
1647 value ? "hi" : "lo");
1648
1649 irqstat = irq_desc[irq].status;
1650 if (is_in && ((bank->suspend_wakeup & mask)
1651 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1652 char *trigger = NULL;
1653
1654 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1655 case IRQ_TYPE_EDGE_FALLING:
1656 trigger = "falling";
1657 break;
1658 case IRQ_TYPE_EDGE_RISING:
1659 trigger = "rising";
1660 break;
1661 case IRQ_TYPE_EDGE_BOTH:
1662 trigger = "bothedge";
1663 break;
1664 case IRQ_TYPE_LEVEL_LOW:
1665 trigger = "low";
1666 break;
1667 case IRQ_TYPE_LEVEL_HIGH:
1668 trigger = "high";
1669 break;
1670 case IRQ_TYPE_NONE:
1671 trigger = "(unspecified)";
1672 break;
1673 }
1674 seq_printf(s, ", irq-%d %s%s",
1675 irq, trigger,
1676 (bank->suspend_wakeup & mask)
1677 ? " wakeup" : "");
1678 }
1679 seq_printf(s, "\n");
1680 }
1681
1682 if (bank_is_mpuio(bank)) {
1683 seq_printf(s, "\n");
1684 gpio = 0;
1685 }
1686 }
1687 return 0;
1688 }
1689
1690 static int dbg_gpio_open(struct inode *inode, struct file *file)
1691 {
1692 return single_open(file, dbg_gpio_show, &inode->i_private);
1693 }
1694
1695 static const struct file_operations debug_fops = {
1696 .open = dbg_gpio_open,
1697 .read = seq_read,
1698 .llseek = seq_lseek,
1699 .release = single_release,
1700 };
1701
1702 static int __init omap_gpio_debuginit(void)
1703 {
1704 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1705 NULL, NULL, &debug_fops);
1706 return 0;
1707 }
1708 late_initcall(omap_gpio_debuginit);
1709 #endif
Linux kernel - Deliverables
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