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sched: Fix rt_rq runtime leakage bug
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include <mach/hardware.h>
28 #include <asm/irq.h>
29 #include <mach/irqs.h>
30 #include <mach/gpio.h>
31 #include <asm/mach/irq.h>
32
33 /*
34 * OMAP1510 GPIO registers
35 */
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67 /*
68 * OMAP7XX specific GPIO registers
69 */
70 #define OMAP7XX_GPIO_DATA_INPUT 0x00
71 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
73 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
74 #define OMAP7XX_GPIO_INT_MASK 0x10
75 #define OMAP7XX_GPIO_INT_STATUS 0x14
76
77 /*
78 * omap2+ specific GPIO registers
79 */
80 #define OMAP24XX_GPIO_REVISION 0x0000
81 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
82 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
84 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
85 #define OMAP24XX_GPIO_WAKE_EN 0x0020
86 #define OMAP24XX_GPIO_CTRL 0x0030
87 #define OMAP24XX_GPIO_OE 0x0034
88 #define OMAP24XX_GPIO_DATAIN 0x0038
89 #define OMAP24XX_GPIO_DATAOUT 0x003c
90 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
93 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
94 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
96 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99 #define OMAP24XX_GPIO_SETWKUENA 0x0084
100 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
103 #define OMAP4_GPIO_REVISION 0x0000
104 #define OMAP4_GPIO_EOI 0x0020
105 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107 #define OMAP4_GPIO_IRQSTATUS0 0x002c
108 #define OMAP4_GPIO_IRQSTATUS1 0x0030
109 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113 #define OMAP4_GPIO_IRQWAKEN0 0x0044
114 #define OMAP4_GPIO_IRQWAKEN1 0x0048
115 #define OMAP4_GPIO_IRQENABLE1 0x011c
116 #define OMAP4_GPIO_WAKE_EN 0x0120
117 #define OMAP4_GPIO_IRQSTATUS2 0x0128
118 #define OMAP4_GPIO_IRQENABLE2 0x012c
119 #define OMAP4_GPIO_CTRL 0x0130
120 #define OMAP4_GPIO_OE 0x0134
121 #define OMAP4_GPIO_DATAIN 0x0138
122 #define OMAP4_GPIO_DATAOUT 0x013c
123 #define OMAP4_GPIO_LEVELDETECT0 0x0140
124 #define OMAP4_GPIO_LEVELDETECT1 0x0144
125 #define OMAP4_GPIO_RISINGDETECT 0x0148
126 #define OMAP4_GPIO_FALLINGDETECT 0x014c
127 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
131 #define OMAP4_GPIO_CLEARWKUENA 0x0180
132 #define OMAP4_GPIO_SETWKUENA 0x0184
133 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
134 #define OMAP4_GPIO_SETDATAOUT 0x0194
135
136 struct gpio_bank {
137 unsigned long pbase;
138 void __iomem *base;
139 u16 irq;
140 u16 virtual_irq_start;
141 int method;
142 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
143 u32 suspend_wakeup;
144 u32 saved_wakeup;
145 #endif
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
152 u32 level_mask;
153 u32 toggle_mask;
154 spinlock_t lock;
155 struct gpio_chip chip;
156 struct clk *dbck;
157 u32 mod_usage;
158 u32 dbck_enable_mask;
159 struct device *dev;
160 bool dbck_flag;
161 int stride;
162 };
163
164 #ifdef CONFIG_ARCH_OMAP3
165 struct omap3_gpio_regs {
166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
176 };
177
178 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
179 #endif
180
181 /*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185 static struct gpio_bank *gpio_bank;
186
187 static int bank_width;
188
189 /* TODO: Analyze removing gpio_bank_count usage from driver code */
190 int gpio_bank_count;
191
192 static inline struct gpio_bank *get_gpio_bank(int gpio)
193 {
194 if (cpu_is_omap15xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
204 if (cpu_is_omap7xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
212 return &gpio_bank[gpio >> 5];
213 BUG();
214 return NULL;
215 }
216
217 static inline int get_gpio_index(int gpio)
218 {
219 if (cpu_is_omap7xx())
220 return gpio & 0x1f;
221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
224 return gpio & 0x1f;
225 return gpio & 0x0f;
226 }
227
228 static inline int gpio_valid(int gpio)
229 {
230 if (gpio < 0)
231 return -1;
232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
234 return -1;
235 return 0;
236 }
237 if (cpu_is_omap15xx() && gpio < 16)
238 return 0;
239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
241 if (cpu_is_omap7xx() && gpio < 192)
242 return 0;
243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
246 return 0;
247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
248 return 0;
249 return -1;
250 }
251
252 static int check_gpio(int gpio)
253 {
254 if (unlikely(gpio_valid(gpio) < 0)) {
255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260 }
261
262 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263 {
264 void __iomem *reg = bank->base;
265 u32 l;
266
267 switch (bank->method) {
268 #ifdef CONFIG_ARCH_OMAP1
269 case METHOD_MPUIO:
270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
271 break;
272 #endif
273 #ifdef CONFIG_ARCH_OMAP15XX
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
277 #endif
278 #ifdef CONFIG_ARCH_OMAP16XX
279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
282 #endif
283 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
286 break;
287 #endif
288 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
292 #endif
293 #if defined(CONFIG_ARCH_OMAP4)
294 case METHOD_GPIO_44XX:
295 reg += OMAP4_GPIO_OE;
296 break;
297 #endif
298 default:
299 WARN_ON(1);
300 return;
301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308 }
309
310 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311 {
312 void __iomem *reg = bank->base;
313 u32 l = 0;
314
315 switch (bank->method) {
316 #ifdef CONFIG_ARCH_OMAP1
317 case METHOD_MPUIO:
318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
325 #endif
326 #ifdef CONFIG_ARCH_OMAP15XX
327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
335 #endif
336 #ifdef CONFIG_ARCH_OMAP16XX
337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
344 #endif
345 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354 #endif
355 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
363 #endif
364 #ifdef CONFIG_ARCH_OMAP4
365 case METHOD_GPIO_44XX:
366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
372 #endif
373 default:
374 WARN_ON(1);
375 return;
376 }
377 __raw_writel(l, reg);
378 }
379
380 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
381 {
382 void __iomem *reg;
383
384 if (check_gpio(gpio) < 0)
385 return -EINVAL;
386 reg = bank->base;
387 switch (bank->method) {
388 #ifdef CONFIG_ARCH_OMAP1
389 case METHOD_MPUIO:
390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
391 break;
392 #endif
393 #ifdef CONFIG_ARCH_OMAP15XX
394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
397 #endif
398 #ifdef CONFIG_ARCH_OMAP16XX
399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
402 #endif
403 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
406 break;
407 #endif
408 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
412 #endif
413 #ifdef CONFIG_ARCH_OMAP4
414 case METHOD_GPIO_44XX:
415 reg += OMAP4_GPIO_DATAIN;
416 break;
417 #endif
418 default:
419 return -EINVAL;
420 }
421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
423 }
424
425 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426 {
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434 #ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
437 break;
438 #endif
439 #ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443 #endif
444 #ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448 #endif
449 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
452 break;
453 #endif
454 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
458 #endif
459 #ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
463 #endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469 }
470
471 #define MOD_REG_BIT(reg, bit_mask, set) \
472 do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477 } while(0)
478
479 /**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490 {
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
495 if (!bank->dbck_flag)
496 return;
497
498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
507 if (bank->method == METHOD_GPIO_44XX)
508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
515 if (bank->method == METHOD_GPIO_44XX)
516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
524 clk_enable(bank->dbck);
525 } else {
526 val &= ~l;
527 clk_disable(bank->dbck);
528 }
529 bank->dbck_enable_mask = val;
530
531 __raw_writel(val, reg);
532 }
533
534 #ifdef CONFIG_ARCH_OMAP2PLUS
535 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
537 {
538 void __iomem *base = bank->base;
539 u32 gpio_bit = 1 << gpio;
540 u32 val;
541
542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
578 __raw_writel(1 << gpio, bank->base
579 + OMAP24XX_GPIO_SETWKUENA);
580 else
581 __raw_writel(1 << gpio, bank->base
582 + OMAP24XX_GPIO_CLEARWKUENA);
583 }
584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
598
599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
608 }
609 #endif
610
611 #ifdef CONFIG_ARCH_OMAP1
612 /*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617 {
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
622 case METHOD_MPUIO:
623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
624 break;
625 #ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629 #endif
630 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634 #endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646 }
647 #endif
648
649 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650 {
651 void __iomem *reg = bank->base;
652 u32 l = 0;
653
654 switch (bank->method) {
655 #ifdef CONFIG_ARCH_OMAP1
656 case METHOD_MPUIO:
657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658 l = __raw_readl(reg);
659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660 bank->toggle_mask |= 1 << gpio;
661 if (trigger & IRQ_TYPE_EDGE_RISING)
662 l |= 1 << gpio;
663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
664 l &= ~(1 << gpio);
665 else
666 goto bad;
667 break;
668 #endif
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674 bank->toggle_mask |= 1 << gpio;
675 if (trigger & IRQ_TYPE_EDGE_RISING)
676 l |= 1 << gpio;
677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
678 l &= ~(1 << gpio);
679 else
680 goto bad;
681 break;
682 #endif
683 #ifdef CONFIG_ARCH_OMAP16XX
684 case METHOD_GPIO_1610:
685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 2 << (gpio << 1);
694 if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l |= 1 << (gpio << 1);
696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
701 break;
702 #endif
703 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
706 l = __raw_readl(reg);
707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708 bank->toggle_mask |= 1 << gpio;
709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716 #endif
717 #ifdef CONFIG_ARCH_OMAP2PLUS
718 case METHOD_GPIO_24XX:
719 case METHOD_GPIO_44XX:
720 set_24xx_gpio_triggering(bank, gpio, trigger);
721 return 0;
722 #endif
723 default:
724 goto bad;
725 }
726 __raw_writel(l, reg);
727 return 0;
728 bad:
729 return -EINVAL;
730 }
731
732 static int gpio_irq_type(struct irq_data *d, unsigned type)
733 {
734 struct gpio_bank *bank;
735 unsigned gpio;
736 int retval;
737 unsigned long flags;
738
739 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
741 else
742 gpio = d->irq - IH_GPIO_BASE;
743
744 if (check_gpio(gpio) < 0)
745 return -EINVAL;
746
747 if (type & ~IRQ_TYPE_SENSE_MASK)
748 return -EINVAL;
749
750 /* OMAP1 allows only only edge triggering */
751 if (!cpu_class_is_omap2()
752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
753 return -EINVAL;
754
755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 spin_unlock_irqrestore(&bank->lock, flags);
759
760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
761 __irq_set_handler_locked(d->irq, handle_level_irq);
762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
763 __irq_set_handler_locked(d->irq, handle_edge_irq);
764
765 return retval;
766 }
767
768 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
769 {
770 void __iomem *reg = bank->base;
771
772 switch (bank->method) {
773 #ifdef CONFIG_ARCH_OMAP1
774 case METHOD_MPUIO:
775 /* MPUIO irqstatus is reset by reading the status register,
776 * so do nothing here */
777 return;
778 #endif
779 #ifdef CONFIG_ARCH_OMAP15XX
780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_STATUS;
782 break;
783 #endif
784 #ifdef CONFIG_ARCH_OMAP16XX
785 case METHOD_GPIO_1610:
786 reg += OMAP1610_GPIO_IRQSTATUS1;
787 break;
788 #endif
789 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
790 case METHOD_GPIO_7XX:
791 reg += OMAP7XX_GPIO_INT_STATUS;
792 break;
793 #endif
794 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
795 case METHOD_GPIO_24XX:
796 reg += OMAP24XX_GPIO_IRQSTATUS1;
797 break;
798 #endif
799 #if defined(CONFIG_ARCH_OMAP4)
800 case METHOD_GPIO_44XX:
801 reg += OMAP4_GPIO_IRQSTATUS0;
802 break;
803 #endif
804 default:
805 WARN_ON(1);
806 return;
807 }
808 __raw_writel(gpio_mask, reg);
809
810 /* Workaround for clearing DSP GPIO interrupts to allow retention */
811 if (cpu_is_omap24xx() || cpu_is_omap34xx())
812 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
813 else if (cpu_is_omap44xx())
814 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
815
816 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
817 __raw_writel(gpio_mask, reg);
818
819 /* Flush posted write for the irq status to avoid spurious interrupts */
820 __raw_readl(reg);
821 }
822 }
823
824 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
825 {
826 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
827 }
828
829 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
830 {
831 void __iomem *reg = bank->base;
832 int inv = 0;
833 u32 l;
834 u32 mask;
835
836 switch (bank->method) {
837 #ifdef CONFIG_ARCH_OMAP1
838 case METHOD_MPUIO:
839 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
840 mask = 0xffff;
841 inv = 1;
842 break;
843 #endif
844 #ifdef CONFIG_ARCH_OMAP15XX
845 case METHOD_GPIO_1510:
846 reg += OMAP1510_GPIO_INT_MASK;
847 mask = 0xffff;
848 inv = 1;
849 break;
850 #endif
851 #ifdef CONFIG_ARCH_OMAP16XX
852 case METHOD_GPIO_1610:
853 reg += OMAP1610_GPIO_IRQENABLE1;
854 mask = 0xffff;
855 break;
856 #endif
857 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
858 case METHOD_GPIO_7XX:
859 reg += OMAP7XX_GPIO_INT_MASK;
860 mask = 0xffffffff;
861 inv = 1;
862 break;
863 #endif
864 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
865 case METHOD_GPIO_24XX:
866 reg += OMAP24XX_GPIO_IRQENABLE1;
867 mask = 0xffffffff;
868 break;
869 #endif
870 #if defined(CONFIG_ARCH_OMAP4)
871 case METHOD_GPIO_44XX:
872 reg += OMAP4_GPIO_IRQSTATUSSET0;
873 mask = 0xffffffff;
874 break;
875 #endif
876 default:
877 WARN_ON(1);
878 return 0;
879 }
880
881 l = __raw_readl(reg);
882 if (inv)
883 l = ~l;
884 l &= mask;
885 return l;
886 }
887
888 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
889 {
890 void __iomem *reg = bank->base;
891 u32 l;
892
893 switch (bank->method) {
894 #ifdef CONFIG_ARCH_OMAP1
895 case METHOD_MPUIO:
896 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
897 l = __raw_readl(reg);
898 if (enable)
899 l &= ~(gpio_mask);
900 else
901 l |= gpio_mask;
902 break;
903 #endif
904 #ifdef CONFIG_ARCH_OMAP15XX
905 case METHOD_GPIO_1510:
906 reg += OMAP1510_GPIO_INT_MASK;
907 l = __raw_readl(reg);
908 if (enable)
909 l &= ~(gpio_mask);
910 else
911 l |= gpio_mask;
912 break;
913 #endif
914 #ifdef CONFIG_ARCH_OMAP16XX
915 case METHOD_GPIO_1610:
916 if (enable)
917 reg += OMAP1610_GPIO_SET_IRQENABLE1;
918 else
919 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
920 l = gpio_mask;
921 break;
922 #endif
923 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
924 case METHOD_GPIO_7XX:
925 reg += OMAP7XX_GPIO_INT_MASK;
926 l = __raw_readl(reg);
927 if (enable)
928 l &= ~(gpio_mask);
929 else
930 l |= gpio_mask;
931 break;
932 #endif
933 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
934 case METHOD_GPIO_24XX:
935 if (enable)
936 reg += OMAP24XX_GPIO_SETIRQENABLE1;
937 else
938 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
939 l = gpio_mask;
940 break;
941 #endif
942 #ifdef CONFIG_ARCH_OMAP4
943 case METHOD_GPIO_44XX:
944 if (enable)
945 reg += OMAP4_GPIO_IRQSTATUSSET0;
946 else
947 reg += OMAP4_GPIO_IRQSTATUSCLR0;
948 l = gpio_mask;
949 break;
950 #endif
951 default:
952 WARN_ON(1);
953 return;
954 }
955 __raw_writel(l, reg);
956 }
957
958 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
959 {
960 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
961 }
962
963 /*
964 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
965 * 1510 does not seem to have a wake-up register. If JTAG is connected
966 * to the target, system will wake up always on GPIO events. While
967 * system is running all registered GPIO interrupts need to have wake-up
968 * enabled. When system is suspended, only selected GPIO interrupts need
969 * to have wake-up enabled.
970 */
971 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
972 {
973 unsigned long uninitialized_var(flags);
974
975 switch (bank->method) {
976 #ifdef CONFIG_ARCH_OMAP16XX
977 case METHOD_MPUIO:
978 case METHOD_GPIO_1610:
979 spin_lock_irqsave(&bank->lock, flags);
980 if (enable)
981 bank->suspend_wakeup |= (1 << gpio);
982 else
983 bank->suspend_wakeup &= ~(1 << gpio);
984 spin_unlock_irqrestore(&bank->lock, flags);
985 return 0;
986 #endif
987 #ifdef CONFIG_ARCH_OMAP2PLUS
988 case METHOD_GPIO_24XX:
989 case METHOD_GPIO_44XX:
990 if (bank->non_wakeup_gpios & (1 << gpio)) {
991 printk(KERN_ERR "Unable to modify wakeup on "
992 "non-wakeup GPIO%d\n",
993 (bank - gpio_bank) * 32 + gpio);
994 return -EINVAL;
995 }
996 spin_lock_irqsave(&bank->lock, flags);
997 if (enable)
998 bank->suspend_wakeup |= (1 << gpio);
999 else
1000 bank->suspend_wakeup &= ~(1 << gpio);
1001 spin_unlock_irqrestore(&bank->lock, flags);
1002 return 0;
1003 #endif
1004 default:
1005 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1006 bank->method);
1007 return -EINVAL;
1008 }
1009 }
1010
1011 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1012 {
1013 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1014 _set_gpio_irqenable(bank, gpio, 0);
1015 _clear_gpio_irqstatus(bank, gpio);
1016 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1017 }
1018
1019 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1020 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
1021 {
1022 unsigned int gpio = d->irq - IH_GPIO_BASE;
1023 struct gpio_bank *bank;
1024 int retval;
1025
1026 if (check_gpio(gpio) < 0)
1027 return -ENODEV;
1028 bank = irq_data_get_irq_chip_data(d);
1029 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1030
1031 return retval;
1032 }
1033
1034 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1035 {
1036 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&bank->lock, flags);
1040
1041 /* Set trigger to none. You need to enable the desired trigger with
1042 * request_irq() or set_irq_type().
1043 */
1044 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1045
1046 #ifdef CONFIG_ARCH_OMAP15XX
1047 if (bank->method == METHOD_GPIO_1510) {
1048 void __iomem *reg;
1049
1050 /* Claim the pin for MPU */
1051 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1052 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1053 }
1054 #endif
1055 if (!cpu_class_is_omap1()) {
1056 if (!bank->mod_usage) {
1057 void __iomem *reg = bank->base;
1058 u32 ctrl;
1059
1060 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1061 reg += OMAP24XX_GPIO_CTRL;
1062 else if (cpu_is_omap44xx())
1063 reg += OMAP4_GPIO_CTRL;
1064 ctrl = __raw_readl(reg);
1065 /* Module is enabled, clocks are not gated */
1066 ctrl &= 0xFFFFFFFE;
1067 __raw_writel(ctrl, reg);
1068 }
1069 bank->mod_usage |= 1 << offset;
1070 }
1071 spin_unlock_irqrestore(&bank->lock, flags);
1072
1073 return 0;
1074 }
1075
1076 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1077 {
1078 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&bank->lock, flags);
1082 #ifdef CONFIG_ARCH_OMAP16XX
1083 if (bank->method == METHOD_GPIO_1610) {
1084 /* Disable wake-up during idle for dynamic tick */
1085 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1086 __raw_writel(1 << offset, reg);
1087 }
1088 #endif
1089 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1090 if (bank->method == METHOD_GPIO_24XX) {
1091 /* Disable wake-up during idle for dynamic tick */
1092 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1093 __raw_writel(1 << offset, reg);
1094 }
1095 #endif
1096 #ifdef CONFIG_ARCH_OMAP4
1097 if (bank->method == METHOD_GPIO_44XX) {
1098 /* Disable wake-up during idle for dynamic tick */
1099 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1100 __raw_writel(1 << offset, reg);
1101 }
1102 #endif
1103 if (!cpu_class_is_omap1()) {
1104 bank->mod_usage &= ~(1 << offset);
1105 if (!bank->mod_usage) {
1106 void __iomem *reg = bank->base;
1107 u32 ctrl;
1108
1109 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1110 reg += OMAP24XX_GPIO_CTRL;
1111 else if (cpu_is_omap44xx())
1112 reg += OMAP4_GPIO_CTRL;
1113 ctrl = __raw_readl(reg);
1114 /* Module is disabled, clocks are gated */
1115 ctrl |= 1;
1116 __raw_writel(ctrl, reg);
1117 }
1118 }
1119 _reset_gpio(bank, bank->chip.base + offset);
1120 spin_unlock_irqrestore(&bank->lock, flags);
1121 }
1122
1123 /*
1124 * We need to unmask the GPIO bank interrupt as soon as possible to
1125 * avoid missing GPIO interrupts for other lines in the bank.
1126 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1127 * in the bank to avoid missing nested interrupts for a GPIO line.
1128 * If we wait to unmask individual GPIO lines in the bank after the
1129 * line's interrupt handler has been run, we may miss some nested
1130 * interrupts.
1131 */
1132 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1133 {
1134 void __iomem *isr_reg = NULL;
1135 u32 isr;
1136 unsigned int gpio_irq, gpio_index;
1137 struct gpio_bank *bank;
1138 u32 retrigger = 0;
1139 int unmasked = 0;
1140
1141 desc->irq_data.chip->irq_ack(&desc->irq_data);
1142
1143 bank = irq_get_handler_data(irq);
1144 #ifdef CONFIG_ARCH_OMAP1
1145 if (bank->method == METHOD_MPUIO)
1146 isr_reg = bank->base +
1147 OMAP_MPUIO_GPIO_INT / bank->stride;
1148 #endif
1149 #ifdef CONFIG_ARCH_OMAP15XX
1150 if (bank->method == METHOD_GPIO_1510)
1151 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1152 #endif
1153 #if defined(CONFIG_ARCH_OMAP16XX)
1154 if (bank->method == METHOD_GPIO_1610)
1155 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1156 #endif
1157 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1158 if (bank->method == METHOD_GPIO_7XX)
1159 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1160 #endif
1161 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1162 if (bank->method == METHOD_GPIO_24XX)
1163 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1164 #endif
1165 #if defined(CONFIG_ARCH_OMAP4)
1166 if (bank->method == METHOD_GPIO_44XX)
1167 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1168 #endif
1169
1170 if (WARN_ON(!isr_reg))
1171 goto exit;
1172
1173 while(1) {
1174 u32 isr_saved, level_mask = 0;
1175 u32 enabled;
1176
1177 enabled = _get_gpio_irqbank_mask(bank);
1178 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1179
1180 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1181 isr &= 0x0000ffff;
1182
1183 if (cpu_class_is_omap2()) {
1184 level_mask = bank->level_mask & enabled;
1185 }
1186
1187 /* clear edge sensitive interrupts before handler(s) are
1188 called so that we don't miss any interrupt occurred while
1189 executing them */
1190 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1191 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1192 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1193
1194 /* if there is only edge sensitive GPIO pin interrupts
1195 configured, we could unmask GPIO bank interrupt immediately */
1196 if (!level_mask && !unmasked) {
1197 unmasked = 1;
1198 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1199 }
1200
1201 isr |= retrigger;
1202 retrigger = 0;
1203 if (!isr)
1204 break;
1205
1206 gpio_irq = bank->virtual_irq_start;
1207 for (; isr != 0; isr >>= 1, gpio_irq++) {
1208 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1209
1210 if (!(isr & 1))
1211 continue;
1212
1213 #ifdef CONFIG_ARCH_OMAP1
1214 /*
1215 * Some chips can't respond to both rising and falling
1216 * at the same time. If this irq was requested with
1217 * both flags, we need to flip the ICR data for the IRQ
1218 * to respond to the IRQ for the opposite direction.
1219 * This will be indicated in the bank toggle_mask.
1220 */
1221 if (bank->toggle_mask & (1 << gpio_index))
1222 _toggle_gpio_edge_triggering(bank, gpio_index);
1223 #endif
1224
1225 generic_handle_irq(gpio_irq);
1226 }
1227 }
1228 /* if bank has any level sensitive GPIO pin interrupt
1229 configured, we must unmask the bank interrupt only after
1230 handler(s) are executed in order to avoid spurious bank
1231 interrupt */
1232 exit:
1233 if (!unmasked)
1234 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1235 }
1236
1237 static void gpio_irq_shutdown(struct irq_data *d)
1238 {
1239 unsigned int gpio = d->irq - IH_GPIO_BASE;
1240 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1241
1242 _reset_gpio(bank, gpio);
1243 }
1244
1245 static void gpio_ack_irq(struct irq_data *d)
1246 {
1247 unsigned int gpio = d->irq - IH_GPIO_BASE;
1248 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1249
1250 _clear_gpio_irqstatus(bank, gpio);
1251 }
1252
1253 static void gpio_mask_irq(struct irq_data *d)
1254 {
1255 unsigned int gpio = d->irq - IH_GPIO_BASE;
1256 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1257
1258 _set_gpio_irqenable(bank, gpio, 0);
1259 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1260 }
1261
1262 static void gpio_unmask_irq(struct irq_data *d)
1263 {
1264 unsigned int gpio = d->irq - IH_GPIO_BASE;
1265 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1266 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1267 u32 trigger = irqd_get_trigger_type(d);
1268
1269 if (trigger)
1270 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1271
1272 /* For level-triggered GPIOs, the clearing must be done after
1273 * the HW source is cleared, thus after the handler has run */
1274 if (bank->level_mask & irq_mask) {
1275 _set_gpio_irqenable(bank, gpio, 0);
1276 _clear_gpio_irqstatus(bank, gpio);
1277 }
1278
1279 _set_gpio_irqenable(bank, gpio, 1);
1280 }
1281
1282 static struct irq_chip gpio_irq_chip = {
1283 .name = "GPIO",
1284 .irq_shutdown = gpio_irq_shutdown,
1285 .irq_ack = gpio_ack_irq,
1286 .irq_mask = gpio_mask_irq,
1287 .irq_unmask = gpio_unmask_irq,
1288 .irq_set_type = gpio_irq_type,
1289 .irq_set_wake = gpio_wake_enable,
1290 };
1291
1292 /*---------------------------------------------------------------------*/
1293
1294 #ifdef CONFIG_ARCH_OMAP1
1295
1296 /* MPUIO uses the always-on 32k clock */
1297
1298 static void mpuio_ack_irq(struct irq_data *d)
1299 {
1300 /* The ISR is reset automatically, so do nothing here. */
1301 }
1302
1303 static void mpuio_mask_irq(struct irq_data *d)
1304 {
1305 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1306 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1307
1308 _set_gpio_irqenable(bank, gpio, 0);
1309 }
1310
1311 static void mpuio_unmask_irq(struct irq_data *d)
1312 {
1313 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1314 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1315
1316 _set_gpio_irqenable(bank, gpio, 1);
1317 }
1318
1319 static struct irq_chip mpuio_irq_chip = {
1320 .name = "MPUIO",
1321 .irq_ack = mpuio_ack_irq,
1322 .irq_mask = mpuio_mask_irq,
1323 .irq_unmask = mpuio_unmask_irq,
1324 .irq_set_type = gpio_irq_type,
1325 #ifdef CONFIG_ARCH_OMAP16XX
1326 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1327 .irq_set_wake = gpio_wake_enable,
1328 #endif
1329 };
1330
1331
1332 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1333
1334
1335 #ifdef CONFIG_ARCH_OMAP16XX
1336
1337 #include <linux/platform_device.h>
1338
1339 static int omap_mpuio_suspend_noirq(struct device *dev)
1340 {
1341 struct platform_device *pdev = to_platform_device(dev);
1342 struct gpio_bank *bank = platform_get_drvdata(pdev);
1343 void __iomem *mask_reg = bank->base +
1344 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1345 unsigned long flags;
1346
1347 spin_lock_irqsave(&bank->lock, flags);
1348 bank->saved_wakeup = __raw_readl(mask_reg);
1349 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1350 spin_unlock_irqrestore(&bank->lock, flags);
1351
1352 return 0;
1353 }
1354
1355 static int omap_mpuio_resume_noirq(struct device *dev)
1356 {
1357 struct platform_device *pdev = to_platform_device(dev);
1358 struct gpio_bank *bank = platform_get_drvdata(pdev);
1359 void __iomem *mask_reg = bank->base +
1360 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1361 unsigned long flags;
1362
1363 spin_lock_irqsave(&bank->lock, flags);
1364 __raw_writel(bank->saved_wakeup, mask_reg);
1365 spin_unlock_irqrestore(&bank->lock, flags);
1366
1367 return 0;
1368 }
1369
1370 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1371 .suspend_noirq = omap_mpuio_suspend_noirq,
1372 .resume_noirq = omap_mpuio_resume_noirq,
1373 };
1374
1375 /* use platform_driver for this, now that there's no longer any
1376 * point to sys_device (other than not disturbing old code).
1377 */
1378 static struct platform_driver omap_mpuio_driver = {
1379 .driver = {
1380 .name = "mpuio",
1381 .pm = &omap_mpuio_dev_pm_ops,
1382 },
1383 };
1384
1385 static struct platform_device omap_mpuio_device = {
1386 .name = "mpuio",
1387 .id = -1,
1388 .dev = {
1389 .driver = &omap_mpuio_driver.driver,
1390 }
1391 /* could list the /proc/iomem resources */
1392 };
1393
1394 static inline void mpuio_init(void)
1395 {
1396 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1397 platform_set_drvdata(&omap_mpuio_device, bank);
1398
1399 if (platform_driver_register(&omap_mpuio_driver) == 0)
1400 (void) platform_device_register(&omap_mpuio_device);
1401 }
1402
1403 #else
1404 static inline void mpuio_init(void) {}
1405 #endif /* 16xx */
1406
1407 #else
1408
1409 extern struct irq_chip mpuio_irq_chip;
1410
1411 #define bank_is_mpuio(bank) 0
1412 static inline void mpuio_init(void) {}
1413
1414 #endif
1415
1416 /*---------------------------------------------------------------------*/
1417
1418 /* REVISIT these are stupid implementations! replace by ones that
1419 * don't switch on METHOD_* and which mostly avoid spinlocks
1420 */
1421
1422 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1423 {
1424 struct gpio_bank *bank;
1425 unsigned long flags;
1426
1427 bank = container_of(chip, struct gpio_bank, chip);
1428 spin_lock_irqsave(&bank->lock, flags);
1429 _set_gpio_direction(bank, offset, 1);
1430 spin_unlock_irqrestore(&bank->lock, flags);
1431 return 0;
1432 }
1433
1434 static int gpio_is_input(struct gpio_bank *bank, int mask)
1435 {
1436 void __iomem *reg = bank->base;
1437
1438 switch (bank->method) {
1439 case METHOD_MPUIO:
1440 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1441 break;
1442 case METHOD_GPIO_1510:
1443 reg += OMAP1510_GPIO_DIR_CONTROL;
1444 break;
1445 case METHOD_GPIO_1610:
1446 reg += OMAP1610_GPIO_DIRECTION;
1447 break;
1448 case METHOD_GPIO_7XX:
1449 reg += OMAP7XX_GPIO_DIR_CONTROL;
1450 break;
1451 case METHOD_GPIO_24XX:
1452 reg += OMAP24XX_GPIO_OE;
1453 break;
1454 case METHOD_GPIO_44XX:
1455 reg += OMAP4_GPIO_OE;
1456 break;
1457 default:
1458 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1459 return -EINVAL;
1460 }
1461 return __raw_readl(reg) & mask;
1462 }
1463
1464 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1465 {
1466 struct gpio_bank *bank;
1467 void __iomem *reg;
1468 int gpio;
1469 u32 mask;
1470
1471 gpio = chip->base + offset;
1472 bank = get_gpio_bank(gpio);
1473 reg = bank->base;
1474 mask = 1 << get_gpio_index(gpio);
1475
1476 if (gpio_is_input(bank, mask))
1477 return _get_gpio_datain(bank, gpio);
1478 else
1479 return _get_gpio_dataout(bank, gpio);
1480 }
1481
1482 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1483 {
1484 struct gpio_bank *bank;
1485 unsigned long flags;
1486
1487 bank = container_of(chip, struct gpio_bank, chip);
1488 spin_lock_irqsave(&bank->lock, flags);
1489 _set_gpio_dataout(bank, offset, value);
1490 _set_gpio_direction(bank, offset, 0);
1491 spin_unlock_irqrestore(&bank->lock, flags);
1492 return 0;
1493 }
1494
1495 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1496 unsigned debounce)
1497 {
1498 struct gpio_bank *bank;
1499 unsigned long flags;
1500
1501 bank = container_of(chip, struct gpio_bank, chip);
1502
1503 if (!bank->dbck) {
1504 bank->dbck = clk_get(bank->dev, "dbclk");
1505 if (IS_ERR(bank->dbck))
1506 dev_err(bank->dev, "Could not get gpio dbck\n");
1507 }
1508
1509 spin_lock_irqsave(&bank->lock, flags);
1510 _set_gpio_debounce(bank, offset, debounce);
1511 spin_unlock_irqrestore(&bank->lock, flags);
1512
1513 return 0;
1514 }
1515
1516 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1517 {
1518 struct gpio_bank *bank;
1519 unsigned long flags;
1520
1521 bank = container_of(chip, struct gpio_bank, chip);
1522 spin_lock_irqsave(&bank->lock, flags);
1523 _set_gpio_dataout(bank, offset, value);
1524 spin_unlock_irqrestore(&bank->lock, flags);
1525 }
1526
1527 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1528 {
1529 struct gpio_bank *bank;
1530
1531 bank = container_of(chip, struct gpio_bank, chip);
1532 return bank->virtual_irq_start + offset;
1533 }
1534
1535 /*---------------------------------------------------------------------*/
1536
1537 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1538 {
1539 u32 rev;
1540
1541 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1542 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1543 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1544 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1545 else if (cpu_is_omap44xx())
1546 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1547 else
1548 return;
1549
1550 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1551 (rev >> 4) & 0x0f, rev & 0x0f);
1552 }
1553
1554 /* This lock class tells lockdep that GPIO irqs are in a different
1555 * category than their parents, so it won't report false recursion.
1556 */
1557 static struct lock_class_key gpio_lock_class;
1558
1559 static inline int init_gpio_info(struct platform_device *pdev)
1560 {
1561 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1562 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1563 GFP_KERNEL);
1564 if (!gpio_bank) {
1565 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1566 return -ENOMEM;
1567 }
1568 return 0;
1569 }
1570
1571 /* TODO: Cleanup cpu_is_* checks */
1572 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1573 {
1574 if (cpu_class_is_omap2()) {
1575 if (cpu_is_omap44xx()) {
1576 __raw_writel(0xffffffff, bank->base +
1577 OMAP4_GPIO_IRQSTATUSCLR0);
1578 __raw_writel(0x00000000, bank->base +
1579 OMAP4_GPIO_DEBOUNCENABLE);
1580 /* Initialize interface clk ungated, module enabled */
1581 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1582 } else if (cpu_is_omap34xx()) {
1583 __raw_writel(0x00000000, bank->base +
1584 OMAP24XX_GPIO_IRQENABLE1);
1585 __raw_writel(0xffffffff, bank->base +
1586 OMAP24XX_GPIO_IRQSTATUS1);
1587 __raw_writel(0x00000000, bank->base +
1588 OMAP24XX_GPIO_DEBOUNCE_EN);
1589
1590 /* Initialize interface clk ungated, module enabled */
1591 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1592 } else if (cpu_is_omap24xx()) {
1593 static const u32 non_wakeup_gpios[] = {
1594 0xe203ffc0, 0x08700040
1595 };
1596 if (id < ARRAY_SIZE(non_wakeup_gpios))
1597 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1598 }
1599 } else if (cpu_class_is_omap1()) {
1600 if (bank_is_mpuio(bank))
1601 __raw_writew(0xffff, bank->base +
1602 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1603 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1604 __raw_writew(0xffff, bank->base
1605 + OMAP1510_GPIO_INT_MASK);
1606 __raw_writew(0x0000, bank->base
1607 + OMAP1510_GPIO_INT_STATUS);
1608 }
1609 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1610 __raw_writew(0x0000, bank->base
1611 + OMAP1610_GPIO_IRQENABLE1);
1612 __raw_writew(0xffff, bank->base
1613 + OMAP1610_GPIO_IRQSTATUS1);
1614 __raw_writew(0x0014, bank->base
1615 + OMAP1610_GPIO_SYSCONFIG);
1616
1617 /*
1618 * Enable system clock for GPIO module.
1619 * The CAM_CLK_CTRL *is* really the right place.
1620 */
1621 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1622 ULPD_CAM_CLK_CTRL);
1623 }
1624 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1625 __raw_writel(0xffffffff, bank->base
1626 + OMAP7XX_GPIO_INT_MASK);
1627 __raw_writel(0x00000000, bank->base
1628 + OMAP7XX_GPIO_INT_STATUS);
1629 }
1630 }
1631 }
1632
1633 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1634 {
1635 int j;
1636 static int gpio;
1637
1638 bank->mod_usage = 0;
1639 /*
1640 * REVISIT eventually switch from OMAP-specific gpio structs
1641 * over to the generic ones
1642 */
1643 bank->chip.request = omap_gpio_request;
1644 bank->chip.free = omap_gpio_free;
1645 bank->chip.direction_input = gpio_input;
1646 bank->chip.get = gpio_get;
1647 bank->chip.direction_output = gpio_output;
1648 bank->chip.set_debounce = gpio_debounce;
1649 bank->chip.set = gpio_set;
1650 bank->chip.to_irq = gpio_2irq;
1651 if (bank_is_mpuio(bank)) {
1652 bank->chip.label = "mpuio";
1653 #ifdef CONFIG_ARCH_OMAP16XX
1654 bank->chip.dev = &omap_mpuio_device.dev;
1655 #endif
1656 bank->chip.base = OMAP_MPUIO(0);
1657 } else {
1658 bank->chip.label = "gpio";
1659 bank->chip.base = gpio;
1660 gpio += bank_width;
1661 }
1662 bank->chip.ngpio = bank_width;
1663
1664 gpiochip_add(&bank->chip);
1665
1666 for (j = bank->virtual_irq_start;
1667 j < bank->virtual_irq_start + bank_width; j++) {
1668 irq_set_lockdep_class(j, &gpio_lock_class);
1669 irq_set_chip_data(j, bank);
1670 if (bank_is_mpuio(bank))
1671 irq_set_chip(j, &mpuio_irq_chip);
1672 else
1673 irq_set_chip(j, &gpio_irq_chip);
1674 irq_set_handler(j, handle_simple_irq);
1675 set_irq_flags(j, IRQF_VALID);
1676 }
1677 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1678 irq_set_handler_data(bank->irq, bank);
1679 }
1680
1681 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1682 {
1683 static int gpio_init_done;
1684 struct omap_gpio_platform_data *pdata;
1685 struct resource *res;
1686 int id;
1687 struct gpio_bank *bank;
1688
1689 if (!pdev->dev.platform_data)
1690 return -EINVAL;
1691
1692 pdata = pdev->dev.platform_data;
1693
1694 if (!gpio_init_done) {
1695 int ret;
1696
1697 ret = init_gpio_info(pdev);
1698 if (ret)
1699 return ret;
1700 }
1701
1702 id = pdev->id;
1703 bank = &gpio_bank[id];
1704
1705 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1706 if (unlikely(!res)) {
1707 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1708 return -ENODEV;
1709 }
1710
1711 bank->irq = res->start;
1712 bank->virtual_irq_start = pdata->virtual_irq_start;
1713 bank->method = pdata->bank_type;
1714 bank->dev = &pdev->dev;
1715 bank->dbck_flag = pdata->dbck_flag;
1716 bank->stride = pdata->bank_stride;
1717 bank_width = pdata->bank_width;
1718
1719 spin_lock_init(&bank->lock);
1720
1721 /* Static mapping, never released */
1722 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1723 if (unlikely(!res)) {
1724 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1725 return -ENODEV;
1726 }
1727
1728 bank->base = ioremap(res->start, resource_size(res));
1729 if (!bank->base) {
1730 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1731 return -ENOMEM;
1732 }
1733
1734 pm_runtime_enable(bank->dev);
1735 pm_runtime_get_sync(bank->dev);
1736
1737 omap_gpio_mod_init(bank, id);
1738 omap_gpio_chip_init(bank);
1739 omap_gpio_show_rev(bank);
1740
1741 if (!gpio_init_done)
1742 gpio_init_done = 1;
1743
1744 return 0;
1745 }
1746
1747 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1748 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1749 {
1750 int i;
1751
1752 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1753 return 0;
1754
1755 for (i = 0; i < gpio_bank_count; i++) {
1756 struct gpio_bank *bank = &gpio_bank[i];
1757 void __iomem *wake_status;
1758 void __iomem *wake_clear;
1759 void __iomem *wake_set;
1760 unsigned long flags;
1761
1762 switch (bank->method) {
1763 #ifdef CONFIG_ARCH_OMAP16XX
1764 case METHOD_GPIO_1610:
1765 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1766 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1767 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1768 break;
1769 #endif
1770 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1771 case METHOD_GPIO_24XX:
1772 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1773 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1774 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1775 break;
1776 #endif
1777 #ifdef CONFIG_ARCH_OMAP4
1778 case METHOD_GPIO_44XX:
1779 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1780 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1781 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1782 break;
1783 #endif
1784 default:
1785 continue;
1786 }
1787
1788 spin_lock_irqsave(&bank->lock, flags);
1789 bank->saved_wakeup = __raw_readl(wake_status);
1790 __raw_writel(0xffffffff, wake_clear);
1791 __raw_writel(bank->suspend_wakeup, wake_set);
1792 spin_unlock_irqrestore(&bank->lock, flags);
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int omap_gpio_resume(struct sys_device *dev)
1799 {
1800 int i;
1801
1802 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1803 return 0;
1804
1805 for (i = 0; i < gpio_bank_count; i++) {
1806 struct gpio_bank *bank = &gpio_bank[i];
1807 void __iomem *wake_clear;
1808 void __iomem *wake_set;
1809 unsigned long flags;
1810
1811 switch (bank->method) {
1812 #ifdef CONFIG_ARCH_OMAP16XX
1813 case METHOD_GPIO_1610:
1814 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1815 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1816 break;
1817 #endif
1818 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1819 case METHOD_GPIO_24XX:
1820 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1821 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1822 break;
1823 #endif
1824 #ifdef CONFIG_ARCH_OMAP4
1825 case METHOD_GPIO_44XX:
1826 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1827 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1828 break;
1829 #endif
1830 default:
1831 continue;
1832 }
1833
1834 spin_lock_irqsave(&bank->lock, flags);
1835 __raw_writel(0xffffffff, wake_clear);
1836 __raw_writel(bank->saved_wakeup, wake_set);
1837 spin_unlock_irqrestore(&bank->lock, flags);
1838 }
1839
1840 return 0;
1841 }
1842
1843 static struct sysdev_class omap_gpio_sysclass = {
1844 .name = "gpio",
1845 .suspend = omap_gpio_suspend,
1846 .resume = omap_gpio_resume,
1847 };
1848
1849 static struct sys_device omap_gpio_device = {
1850 .id = 0,
1851 .cls = &omap_gpio_sysclass,
1852 };
1853
1854 #endif
1855
1856 #ifdef CONFIG_ARCH_OMAP2PLUS
1857
1858 static int workaround_enabled;
1859
1860 void omap2_gpio_prepare_for_idle(int off_mode)
1861 {
1862 int i, c = 0;
1863 int min = 0;
1864
1865 if (cpu_is_omap34xx())
1866 min = 1;
1867
1868 for (i = min; i < gpio_bank_count; i++) {
1869 struct gpio_bank *bank = &gpio_bank[i];
1870 u32 l1 = 0, l2 = 0;
1871 int j;
1872
1873 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1874 clk_disable(bank->dbck);
1875
1876 if (!off_mode)
1877 continue;
1878
1879 /* If going to OFF, remove triggering for all
1880 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1881 * generated. See OMAP2420 Errata item 1.101. */
1882 if (!(bank->enabled_non_wakeup_gpios))
1883 continue;
1884
1885 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1886 bank->saved_datain = __raw_readl(bank->base +
1887 OMAP24XX_GPIO_DATAIN);
1888 l1 = __raw_readl(bank->base +
1889 OMAP24XX_GPIO_FALLINGDETECT);
1890 l2 = __raw_readl(bank->base +
1891 OMAP24XX_GPIO_RISINGDETECT);
1892 }
1893
1894 if (cpu_is_omap44xx()) {
1895 bank->saved_datain = __raw_readl(bank->base +
1896 OMAP4_GPIO_DATAIN);
1897 l1 = __raw_readl(bank->base +
1898 OMAP4_GPIO_FALLINGDETECT);
1899 l2 = __raw_readl(bank->base +
1900 OMAP4_GPIO_RISINGDETECT);
1901 }
1902
1903 bank->saved_fallingdetect = l1;
1904 bank->saved_risingdetect = l2;
1905 l1 &= ~bank->enabled_non_wakeup_gpios;
1906 l2 &= ~bank->enabled_non_wakeup_gpios;
1907
1908 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1909 __raw_writel(l1, bank->base +
1910 OMAP24XX_GPIO_FALLINGDETECT);
1911 __raw_writel(l2, bank->base +
1912 OMAP24XX_GPIO_RISINGDETECT);
1913 }
1914
1915 if (cpu_is_omap44xx()) {
1916 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1917 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1918 }
1919
1920 c++;
1921 }
1922 if (!c) {
1923 workaround_enabled = 0;
1924 return;
1925 }
1926 workaround_enabled = 1;
1927 }
1928
1929 void omap2_gpio_resume_after_idle(void)
1930 {
1931 int i;
1932 int min = 0;
1933
1934 if (cpu_is_omap34xx())
1935 min = 1;
1936 for (i = min; i < gpio_bank_count; i++) {
1937 struct gpio_bank *bank = &gpio_bank[i];
1938 u32 l = 0, gen, gen0, gen1;
1939 int j;
1940
1941 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1942 clk_enable(bank->dbck);
1943
1944 if (!workaround_enabled)
1945 continue;
1946
1947 if (!(bank->enabled_non_wakeup_gpios))
1948 continue;
1949
1950 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1951 __raw_writel(bank->saved_fallingdetect,
1952 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1953 __raw_writel(bank->saved_risingdetect,
1954 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1955 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1956 }
1957
1958 if (cpu_is_omap44xx()) {
1959 __raw_writel(bank->saved_fallingdetect,
1960 bank->base + OMAP4_GPIO_FALLINGDETECT);
1961 __raw_writel(bank->saved_risingdetect,
1962 bank->base + OMAP4_GPIO_RISINGDETECT);
1963 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1964 }
1965
1966 /* Check if any of the non-wakeup interrupt GPIOs have changed
1967 * state. If so, generate an IRQ by software. This is
1968 * horribly racy, but it's the best we can do to work around
1969 * this silicon bug. */
1970 l ^= bank->saved_datain;
1971 l &= bank->enabled_non_wakeup_gpios;
1972
1973 /*
1974 * No need to generate IRQs for the rising edge for gpio IRQs
1975 * configured with falling edge only; and vice versa.
1976 */
1977 gen0 = l & bank->saved_fallingdetect;
1978 gen0 &= bank->saved_datain;
1979
1980 gen1 = l & bank->saved_risingdetect;
1981 gen1 &= ~(bank->saved_datain);
1982
1983 /* FIXME: Consider GPIO IRQs with level detections properly! */
1984 gen = l & (~(bank->saved_fallingdetect) &
1985 ~(bank->saved_risingdetect));
1986 /* Consider all GPIO IRQs needed to be updated */
1987 gen |= gen0 | gen1;
1988
1989 if (gen) {
1990 u32 old0, old1;
1991
1992 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1993 old0 = __raw_readl(bank->base +
1994 OMAP24XX_GPIO_LEVELDETECT0);
1995 old1 = __raw_readl(bank->base +
1996 OMAP24XX_GPIO_LEVELDETECT1);
1997 __raw_writel(old0 | gen, bank->base +
1998 OMAP24XX_GPIO_LEVELDETECT0);
1999 __raw_writel(old1 | gen, bank->base +
2000 OMAP24XX_GPIO_LEVELDETECT1);
2001 __raw_writel(old0, bank->base +
2002 OMAP24XX_GPIO_LEVELDETECT0);
2003 __raw_writel(old1, bank->base +
2004 OMAP24XX_GPIO_LEVELDETECT1);
2005 }
2006
2007 if (cpu_is_omap44xx()) {
2008 old0 = __raw_readl(bank->base +
2009 OMAP4_GPIO_LEVELDETECT0);
2010 old1 = __raw_readl(bank->base +
2011 OMAP4_GPIO_LEVELDETECT1);
2012 __raw_writel(old0 | l, bank->base +
2013 OMAP4_GPIO_LEVELDETECT0);
2014 __raw_writel(old1 | l, bank->base +
2015 OMAP4_GPIO_LEVELDETECT1);
2016 __raw_writel(old0, bank->base +
2017 OMAP4_GPIO_LEVELDETECT0);
2018 __raw_writel(old1, bank->base +
2019 OMAP4_GPIO_LEVELDETECT1);
2020 }
2021 }
2022 }
2023
2024 }
2025
2026 #endif
2027
2028 #ifdef CONFIG_ARCH_OMAP3
2029 /* save the registers of bank 2-6 */
2030 void omap_gpio_save_context(void)
2031 {
2032 int i;
2033
2034 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2035 for (i = 1; i < gpio_bank_count; i++) {
2036 struct gpio_bank *bank = &gpio_bank[i];
2037 gpio_context[i].irqenable1 =
2038 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2039 gpio_context[i].irqenable2 =
2040 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2041 gpio_context[i].wake_en =
2042 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2043 gpio_context[i].ctrl =
2044 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2045 gpio_context[i].oe =
2046 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2047 gpio_context[i].leveldetect0 =
2048 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2049 gpio_context[i].leveldetect1 =
2050 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2051 gpio_context[i].risingdetect =
2052 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2053 gpio_context[i].fallingdetect =
2054 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2055 gpio_context[i].dataout =
2056 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2057 }
2058 }
2059
2060 /* restore the required registers of bank 2-6 */
2061 void omap_gpio_restore_context(void)
2062 {
2063 int i;
2064
2065 for (i = 1; i < gpio_bank_count; i++) {
2066 struct gpio_bank *bank = &gpio_bank[i];
2067 __raw_writel(gpio_context[i].irqenable1,
2068 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2069 __raw_writel(gpio_context[i].irqenable2,
2070 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2071 __raw_writel(gpio_context[i].wake_en,
2072 bank->base + OMAP24XX_GPIO_WAKE_EN);
2073 __raw_writel(gpio_context[i].ctrl,
2074 bank->base + OMAP24XX_GPIO_CTRL);
2075 __raw_writel(gpio_context[i].oe,
2076 bank->base + OMAP24XX_GPIO_OE);
2077 __raw_writel(gpio_context[i].leveldetect0,
2078 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2079 __raw_writel(gpio_context[i].leveldetect1,
2080 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2081 __raw_writel(gpio_context[i].risingdetect,
2082 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2083 __raw_writel(gpio_context[i].fallingdetect,
2084 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2085 __raw_writel(gpio_context[i].dataout,
2086 bank->base + OMAP24XX_GPIO_DATAOUT);
2087 }
2088 }
2089 #endif
2090
2091 static struct platform_driver omap_gpio_driver = {
2092 .probe = omap_gpio_probe,
2093 .driver = {
2094 .name = "omap_gpio",
2095 },
2096 };
2097
2098 /*
2099 * gpio driver register needs to be done before
2100 * machine_init functions access gpio APIs.
2101 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2102 */
2103 static int __init omap_gpio_drv_reg(void)
2104 {
2105 return platform_driver_register(&omap_gpio_driver);
2106 }
2107 postcore_initcall(omap_gpio_drv_reg);
2108
2109 static int __init omap_gpio_sysinit(void)
2110 {
2111 int ret = 0;
2112
2113 mpuio_init();
2114
2115 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2116 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2117 if (ret == 0) {
2118 ret = sysdev_class_register(&omap_gpio_sysclass);
2119 if (ret == 0)
2120 ret = sysdev_register(&omap_gpio_device);
2121 }
2122 }
2123 #endif
2124
2125 return ret;
2126 }
2127
2128 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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