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[ARM] 3429/1: ARM: OMAP: 4/8 Update GPIO
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/ptrace.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23
24 #include <asm/hardware.h>
25 #include <asm/irq.h>
26 #include <asm/arch/irqs.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/mach/irq.h>
29
30 #include <asm/io.h>
31
32 /*
33 * OMAP1510 GPIO registers
34 */
35 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
50 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
51 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
52 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70
71 /*
72 * OMAP730 specific GPIO registers
73 */
74 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
75 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
76 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
77 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
78 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
79 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
80 #define OMAP730_GPIO_DATA_INPUT 0x00
81 #define OMAP730_GPIO_DATA_OUTPUT 0x04
82 #define OMAP730_GPIO_DIR_CONTROL 0x08
83 #define OMAP730_GPIO_INT_CONTROL 0x0c
84 #define OMAP730_GPIO_INT_MASK 0x10
85 #define OMAP730_GPIO_INT_STATUS 0x14
86
87 /*
88 * omap24xx specific GPIO registers
89 */
90 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
91 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
92 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
93 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
94 #define OMAP24XX_GPIO_REVISION 0x0000
95 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
96 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
97 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
113
114 #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
115
116 struct gpio_bank {
117 void __iomem *base;
118 u16 irq;
119 u16 virtual_irq_start;
120 int method;
121 u32 reserved_map;
122 u32 suspend_wakeup;
123 u32 saved_wakeup;
124 spinlock_t lock;
125 };
126
127 #define METHOD_MPUIO 0
128 #define METHOD_GPIO_1510 1
129 #define METHOD_GPIO_1610 2
130 #define METHOD_GPIO_730 3
131 #define METHOD_GPIO_24XX 4
132
133 #ifdef CONFIG_ARCH_OMAP16XX
134 static struct gpio_bank gpio_bank_1610[5] = {
135 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
136 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
138 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
139 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
140 };
141 #endif
142
143 #ifdef CONFIG_ARCH_OMAP15XX
144 static struct gpio_bank gpio_bank_1510[2] = {
145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
146 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
147 };
148 #endif
149
150 #ifdef CONFIG_ARCH_OMAP730
151 static struct gpio_bank gpio_bank_730[7] = {
152 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
153 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
154 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
155 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
156 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
157 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
158 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
159 };
160 #endif
161
162 #ifdef CONFIG_ARCH_OMAP24XX
163 static struct gpio_bank gpio_bank_24xx[4] = {
164 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
166 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
167 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
168 };
169 #endif
170
171 static struct gpio_bank *gpio_bank;
172 static int gpio_bank_count;
173
174 static inline struct gpio_bank *get_gpio_bank(int gpio)
175 {
176 #ifdef CONFIG_ARCH_OMAP15XX
177 if (cpu_is_omap15xx()) {
178 if (OMAP_GPIO_IS_MPUIO(gpio))
179 return &gpio_bank[0];
180 return &gpio_bank[1];
181 }
182 #endif
183 #if defined(CONFIG_ARCH_OMAP16XX)
184 if (cpu_is_omap16xx()) {
185 if (OMAP_GPIO_IS_MPUIO(gpio))
186 return &gpio_bank[0];
187 return &gpio_bank[1 + (gpio >> 4)];
188 }
189 #endif
190 #ifdef CONFIG_ARCH_OMAP730
191 if (cpu_is_omap730()) {
192 if (OMAP_GPIO_IS_MPUIO(gpio))
193 return &gpio_bank[0];
194 return &gpio_bank[1 + (gpio >> 5)];
195 }
196 #endif
197 #ifdef CONFIG_ARCH_OMAP24XX
198 if (cpu_is_omap24xx())
199 return &gpio_bank[gpio >> 5];
200 #endif
201 }
202
203 static inline int get_gpio_index(int gpio)
204 {
205 #ifdef CONFIG_ARCH_OMAP730
206 if (cpu_is_omap730())
207 return gpio & 0x1f;
208 #endif
209 #ifdef CONFIG_ARCH_OMAP24XX
210 if (cpu_is_omap24xx())
211 return gpio & 0x1f;
212 #endif
213 return gpio & 0x0f;
214 }
215
216 static inline int gpio_valid(int gpio)
217 {
218 if (gpio < 0)
219 return -1;
220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
221 if ((gpio & OMAP_MPUIO_MASK) > 16)
222 return -1;
223 return 0;
224 }
225 #ifdef CONFIG_ARCH_OMAP15XX
226 if (cpu_is_omap15xx() && gpio < 16)
227 return 0;
228 #endif
229 #if defined(CONFIG_ARCH_OMAP16XX)
230 if ((cpu_is_omap16xx()) && gpio < 64)
231 return 0;
232 #endif
233 #ifdef CONFIG_ARCH_OMAP730
234 if (cpu_is_omap730() && gpio < 192)
235 return 0;
236 #endif
237 #ifdef CONFIG_ARCH_OMAP24XX
238 if (cpu_is_omap24xx() && gpio < 128)
239 return 0;
240 #endif
241 return -1;
242 }
243
244 static int check_gpio(int gpio)
245 {
246 if (unlikely(gpio_valid(gpio)) < 0) {
247 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
248 dump_stack();
249 return -1;
250 }
251 return 0;
252 }
253
254 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
255 {
256 void __iomem *reg = bank->base;
257 u32 l;
258
259 switch (bank->method) {
260 case METHOD_MPUIO:
261 reg += OMAP_MPUIO_IO_CNTL;
262 break;
263 case METHOD_GPIO_1510:
264 reg += OMAP1510_GPIO_DIR_CONTROL;
265 break;
266 case METHOD_GPIO_1610:
267 reg += OMAP1610_GPIO_DIRECTION;
268 break;
269 case METHOD_GPIO_730:
270 reg += OMAP730_GPIO_DIR_CONTROL;
271 break;
272 case METHOD_GPIO_24XX:
273 reg += OMAP24XX_GPIO_OE;
274 break;
275 }
276 l = __raw_readl(reg);
277 if (is_input)
278 l |= 1 << gpio;
279 else
280 l &= ~(1 << gpio);
281 __raw_writel(l, reg);
282 }
283
284 void omap_set_gpio_direction(int gpio, int is_input)
285 {
286 struct gpio_bank *bank;
287
288 if (check_gpio(gpio) < 0)
289 return;
290 bank = get_gpio_bank(gpio);
291 spin_lock(&bank->lock);
292 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
293 spin_unlock(&bank->lock);
294 }
295
296 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
297 {
298 void __iomem *reg = bank->base;
299 u32 l = 0;
300
301 switch (bank->method) {
302 case METHOD_MPUIO:
303 reg += OMAP_MPUIO_OUTPUT;
304 l = __raw_readl(reg);
305 if (enable)
306 l |= 1 << gpio;
307 else
308 l &= ~(1 << gpio);
309 break;
310 case METHOD_GPIO_1510:
311 reg += OMAP1510_GPIO_DATA_OUTPUT;
312 l = __raw_readl(reg);
313 if (enable)
314 l |= 1 << gpio;
315 else
316 l &= ~(1 << gpio);
317 break;
318 case METHOD_GPIO_1610:
319 if (enable)
320 reg += OMAP1610_GPIO_SET_DATAOUT;
321 else
322 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
323 l = 1 << gpio;
324 break;
325 case METHOD_GPIO_730:
326 reg += OMAP730_GPIO_DATA_OUTPUT;
327 l = __raw_readl(reg);
328 if (enable)
329 l |= 1 << gpio;
330 else
331 l &= ~(1 << gpio);
332 break;
333 case METHOD_GPIO_24XX:
334 if (enable)
335 reg += OMAP24XX_GPIO_SETDATAOUT;
336 else
337 reg += OMAP24XX_GPIO_CLEARDATAOUT;
338 l = 1 << gpio;
339 break;
340 default:
341 BUG();
342 return;
343 }
344 __raw_writel(l, reg);
345 }
346
347 void omap_set_gpio_dataout(int gpio, int enable)
348 {
349 struct gpio_bank *bank;
350
351 if (check_gpio(gpio) < 0)
352 return;
353 bank = get_gpio_bank(gpio);
354 spin_lock(&bank->lock);
355 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
356 spin_unlock(&bank->lock);
357 }
358
359 int omap_get_gpio_datain(int gpio)
360 {
361 struct gpio_bank *bank;
362 void __iomem *reg;
363
364 if (check_gpio(gpio) < 0)
365 return -1;
366 bank = get_gpio_bank(gpio);
367 reg = bank->base;
368 switch (bank->method) {
369 case METHOD_MPUIO:
370 reg += OMAP_MPUIO_INPUT_LATCH;
371 break;
372 case METHOD_GPIO_1510:
373 reg += OMAP1510_GPIO_DATA_INPUT;
374 break;
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DATAIN;
377 break;
378 case METHOD_GPIO_730:
379 reg += OMAP730_GPIO_DATA_INPUT;
380 break;
381 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_DATAIN;
383 break;
384 default:
385 BUG();
386 return -1;
387 }
388 return (__raw_readl(reg)
389 & (1 << get_gpio_index(gpio))) != 0;
390 }
391
392 #define MOD_REG_BIT(reg, bit_mask, set) \
393 do { \
394 int l = __raw_readl(base + reg); \
395 if (set) l |= bit_mask; \
396 else l &= ~bit_mask; \
397 __raw_writel(l, base + reg); \
398 } while(0)
399
400 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
401 {
402 u32 gpio_bit = 1 << gpio;
403
404 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
405 trigger & __IRQT_LOWLVL);
406 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
407 trigger & __IRQT_HIGHLVL);
408 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
409 trigger & __IRQT_RISEDGE);
410 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
411 trigger & __IRQT_FALEDGE);
412 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
413 * triggering requested. */
414 }
415
416 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
417 {
418 void __iomem *reg = bank->base;
419 u32 l = 0;
420
421 switch (bank->method) {
422 case METHOD_MPUIO:
423 reg += OMAP_MPUIO_GPIO_INT_EDGE;
424 l = __raw_readl(reg);
425 if (trigger & __IRQT_RISEDGE)
426 l |= 1 << gpio;
427 else if (trigger & __IRQT_FALEDGE)
428 l &= ~(1 << gpio);
429 else
430 goto bad;
431 break;
432 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_INT_CONTROL;
434 l = __raw_readl(reg);
435 if (trigger & __IRQT_RISEDGE)
436 l |= 1 << gpio;
437 else if (trigger & __IRQT_FALEDGE)
438 l &= ~(1 << gpio);
439 else
440 goto bad;
441 break;
442 case METHOD_GPIO_1610:
443 if (gpio & 0x08)
444 reg += OMAP1610_GPIO_EDGE_CTRL2;
445 else
446 reg += OMAP1610_GPIO_EDGE_CTRL1;
447 gpio &= 0x07;
448 /* We allow only edge triggering, i.e. two lowest bits */
449 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
450 BUG();
451 l = __raw_readl(reg);
452 l &= ~(3 << (gpio << 1));
453 if (trigger & __IRQT_RISEDGE)
454 l |= 2 << (gpio << 1);
455 if (trigger & __IRQT_FALEDGE)
456 l |= 1 << (gpio << 1);
457 break;
458 case METHOD_GPIO_730:
459 reg += OMAP730_GPIO_INT_CONTROL;
460 l = __raw_readl(reg);
461 if (trigger & __IRQT_RISEDGE)
462 l |= 1 << gpio;
463 else if (trigger & __IRQT_FALEDGE)
464 l &= ~(1 << gpio);
465 else
466 goto bad;
467 break;
468 case METHOD_GPIO_24XX:
469 set_24xx_gpio_triggering(reg, gpio, trigger);
470 break;
471 default:
472 BUG();
473 goto bad;
474 }
475 __raw_writel(l, reg);
476 return 0;
477 bad:
478 return -EINVAL;
479 }
480
481 static int gpio_irq_type(unsigned irq, unsigned type)
482 {
483 struct gpio_bank *bank;
484 unsigned gpio;
485 int retval;
486
487 if (irq > IH_MPUIO_BASE)
488 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
489 else
490 gpio = irq - IH_GPIO_BASE;
491
492 if (check_gpio(gpio) < 0)
493 return -EINVAL;
494
495 if (type & IRQT_PROBE)
496 return -EINVAL;
497 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
498 return -EINVAL;
499
500 bank = get_gpio_bank(gpio);
501 spin_lock(&bank->lock);
502 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
503 spin_unlock(&bank->lock);
504 return retval;
505 }
506
507 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
508 {
509 void __iomem *reg = bank->base;
510
511 switch (bank->method) {
512 case METHOD_MPUIO:
513 /* MPUIO irqstatus is reset by reading the status register,
514 * so do nothing here */
515 return;
516 case METHOD_GPIO_1510:
517 reg += OMAP1510_GPIO_INT_STATUS;
518 break;
519 case METHOD_GPIO_1610:
520 reg += OMAP1610_GPIO_IRQSTATUS1;
521 break;
522 case METHOD_GPIO_730:
523 reg += OMAP730_GPIO_INT_STATUS;
524 break;
525 case METHOD_GPIO_24XX:
526 reg += OMAP24XX_GPIO_IRQSTATUS1;
527 break;
528 default:
529 BUG();
530 return;
531 }
532 __raw_writel(gpio_mask, reg);
533 }
534
535 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
536 {
537 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
538 }
539
540 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
541 {
542 void __iomem *reg = bank->base;
543 u32 l;
544
545 switch (bank->method) {
546 case METHOD_MPUIO:
547 reg += OMAP_MPUIO_GPIO_MASKIT;
548 l = __raw_readl(reg);
549 if (enable)
550 l &= ~(gpio_mask);
551 else
552 l |= gpio_mask;
553 break;
554 case METHOD_GPIO_1510:
555 reg += OMAP1510_GPIO_INT_MASK;
556 l = __raw_readl(reg);
557 if (enable)
558 l &= ~(gpio_mask);
559 else
560 l |= gpio_mask;
561 break;
562 case METHOD_GPIO_1610:
563 if (enable)
564 reg += OMAP1610_GPIO_SET_IRQENABLE1;
565 else
566 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
567 l = gpio_mask;
568 break;
569 case METHOD_GPIO_730:
570 reg += OMAP730_GPIO_INT_MASK;
571 l = __raw_readl(reg);
572 if (enable)
573 l &= ~(gpio_mask);
574 else
575 l |= gpio_mask;
576 break;
577 case METHOD_GPIO_24XX:
578 if (enable)
579 reg += OMAP24XX_GPIO_SETIRQENABLE1;
580 else
581 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
582 l = gpio_mask;
583 break;
584 default:
585 BUG();
586 return;
587 }
588 __raw_writel(l, reg);
589 }
590
591 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
592 {
593 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
594 }
595
596 /*
597 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
598 * 1510 does not seem to have a wake-up register. If JTAG is connected
599 * to the target, system will wake up always on GPIO events. While
600 * system is running all registered GPIO interrupts need to have wake-up
601 * enabled. When system is suspended, only selected GPIO interrupts need
602 * to have wake-up enabled.
603 */
604 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
605 {
606 switch (bank->method) {
607 case METHOD_GPIO_1610:
608 case METHOD_GPIO_24XX:
609 spin_lock(&bank->lock);
610 if (enable)
611 bank->suspend_wakeup |= (1 << gpio);
612 else
613 bank->suspend_wakeup &= ~(1 << gpio);
614 spin_unlock(&bank->lock);
615 return 0;
616 default:
617 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
618 bank->method);
619 return -EINVAL;
620 }
621 }
622
623 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
624 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
625 {
626 unsigned int gpio = irq - IH_GPIO_BASE;
627 struct gpio_bank *bank;
628 int retval;
629
630 if (check_gpio(gpio) < 0)
631 return -ENODEV;
632 bank = get_gpio_bank(gpio);
633 spin_lock(&bank->lock);
634 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
635 spin_unlock(&bank->lock);
636
637 return retval;
638 }
639
640 int omap_request_gpio(int gpio)
641 {
642 struct gpio_bank *bank;
643
644 if (check_gpio(gpio) < 0)
645 return -EINVAL;
646
647 bank = get_gpio_bank(gpio);
648 spin_lock(&bank->lock);
649 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
650 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
651 dump_stack();
652 spin_unlock(&bank->lock);
653 return -1;
654 }
655 bank->reserved_map |= (1 << get_gpio_index(gpio));
656
657 /* Set trigger to none. You need to enable the trigger after request_irq */
658 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
659
660 #ifdef CONFIG_ARCH_OMAP15XX
661 if (bank->method == METHOD_GPIO_1510) {
662 void __iomem *reg;
663
664 /* Claim the pin for MPU */
665 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
666 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
667 }
668 #endif
669 #ifdef CONFIG_ARCH_OMAP16XX
670 if (bank->method == METHOD_GPIO_1610) {
671 /* Enable wake-up during idle for dynamic tick */
672 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
673 __raw_writel(1 << get_gpio_index(gpio), reg);
674 }
675 #endif
676 #ifdef CONFIG_ARCH_OMAP24XX
677 if (bank->method == METHOD_GPIO_24XX) {
678 /* Enable wake-up during idle for dynamic tick */
679 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
680 __raw_writel(1 << get_gpio_index(gpio), reg);
681 }
682 #endif
683 spin_unlock(&bank->lock);
684
685 return 0;
686 }
687
688 void omap_free_gpio(int gpio)
689 {
690 struct gpio_bank *bank;
691
692 if (check_gpio(gpio) < 0)
693 return;
694 bank = get_gpio_bank(gpio);
695 spin_lock(&bank->lock);
696 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
697 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
698 dump_stack();
699 spin_unlock(&bank->lock);
700 return;
701 }
702 #ifdef CONFIG_ARCH_OMAP16XX
703 if (bank->method == METHOD_GPIO_1610) {
704 /* Disable wake-up during idle for dynamic tick */
705 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
706 __raw_writel(1 << get_gpio_index(gpio), reg);
707 }
708 #endif
709 #ifdef CONFIG_ARCH_OMAP24XX
710 if (bank->method == METHOD_GPIO_24XX) {
711 /* Disable wake-up during idle for dynamic tick */
712 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
713 __raw_writel(1 << get_gpio_index(gpio), reg);
714 }
715 #endif
716 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
717 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
718 _set_gpio_irqenable(bank, gpio, 0);
719 _clear_gpio_irqstatus(bank, gpio);
720 spin_unlock(&bank->lock);
721 }
722
723 /*
724 * We need to unmask the GPIO bank interrupt as soon as possible to
725 * avoid missing GPIO interrupts for other lines in the bank.
726 * Then we need to mask-read-clear-unmask the triggered GPIO lines
727 * in the bank to avoid missing nested interrupts for a GPIO line.
728 * If we wait to unmask individual GPIO lines in the bank after the
729 * line's interrupt handler has been run, we may miss some nested
730 * interrupts.
731 */
732 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
733 struct pt_regs *regs)
734 {
735 void __iomem *isr_reg = NULL;
736 u32 isr;
737 unsigned int gpio_irq;
738 struct gpio_bank *bank;
739
740 desc->chip->ack(irq);
741
742 bank = (struct gpio_bank *) desc->data;
743 if (bank->method == METHOD_MPUIO)
744 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
745 #ifdef CONFIG_ARCH_OMAP15XX
746 if (bank->method == METHOD_GPIO_1510)
747 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
748 #endif
749 #if defined(CONFIG_ARCH_OMAP16XX)
750 if (bank->method == METHOD_GPIO_1610)
751 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
752 #endif
753 #ifdef CONFIG_ARCH_OMAP730
754 if (bank->method == METHOD_GPIO_730)
755 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
756 #endif
757 #ifdef CONFIG_ARCH_OMAP24XX
758 if (bank->method == METHOD_GPIO_24XX)
759 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
760 #endif
761 while(1) {
762 u32 isr_saved, level_mask = 0;
763
764 isr_saved = isr = __raw_readl(isr_reg);
765
766 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
767 isr &= 0x0000ffff;
768
769 if (cpu_is_omap24xx())
770 level_mask =
771 __raw_readl(bank->base +
772 OMAP24XX_GPIO_LEVELDETECT0) |
773 __raw_readl(bank->base +
774 OMAP24XX_GPIO_LEVELDETECT1);
775
776 /* clear edge sensitive interrupts before handler(s) are
777 called so that we don't miss any interrupt occurred while
778 executing them */
779 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
780 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
781 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
782
783 /* if there is only edge sensitive GPIO pin interrupts
784 configured, we could unmask GPIO bank interrupt immediately */
785 if (!level_mask)
786 desc->chip->unmask(irq);
787
788 if (!isr)
789 break;
790
791 gpio_irq = bank->virtual_irq_start;
792 for (; isr != 0; isr >>= 1, gpio_irq++) {
793 struct irqdesc *d;
794 if (!(isr & 1))
795 continue;
796 d = irq_desc + gpio_irq;
797 desc_handle_irq(gpio_irq, d, regs);
798 }
799
800 if (cpu_is_omap24xx()) {
801 /* clear level sensitive interrupts after handler(s) */
802 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
803 _clear_gpio_irqbank(bank, isr_saved & level_mask);
804 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
805 }
806
807 /* if bank has any level sensitive GPIO pin interrupt
808 configured, we must unmask the bank interrupt only after
809 handler(s) are executed in order to avoid spurious bank
810 interrupt */
811 if (level_mask)
812 desc->chip->unmask(irq);
813 }
814 }
815
816 static void gpio_ack_irq(unsigned int irq)
817 {
818 unsigned int gpio = irq - IH_GPIO_BASE;
819 struct gpio_bank *bank = get_gpio_bank(gpio);
820
821 _clear_gpio_irqstatus(bank, gpio);
822 }
823
824 static void gpio_mask_irq(unsigned int irq)
825 {
826 unsigned int gpio = irq - IH_GPIO_BASE;
827 struct gpio_bank *bank = get_gpio_bank(gpio);
828
829 _set_gpio_irqenable(bank, gpio, 0);
830 }
831
832 static void gpio_unmask_irq(unsigned int irq)
833 {
834 unsigned int gpio = irq - IH_GPIO_BASE;
835 unsigned int gpio_idx = get_gpio_index(gpio);
836 struct gpio_bank *bank = get_gpio_bank(gpio);
837
838 _set_gpio_irqenable(bank, gpio_idx, 1);
839 }
840
841 static void mpuio_ack_irq(unsigned int irq)
842 {
843 /* The ISR is reset automatically, so do nothing here. */
844 }
845
846 static void mpuio_mask_irq(unsigned int irq)
847 {
848 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
849 struct gpio_bank *bank = get_gpio_bank(gpio);
850
851 _set_gpio_irqenable(bank, gpio, 0);
852 }
853
854 static void mpuio_unmask_irq(unsigned int irq)
855 {
856 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
857 struct gpio_bank *bank = get_gpio_bank(gpio);
858
859 _set_gpio_irqenable(bank, gpio, 1);
860 }
861
862 static struct irqchip gpio_irq_chip = {
863 .ack = gpio_ack_irq,
864 .mask = gpio_mask_irq,
865 .unmask = gpio_unmask_irq,
866 .set_type = gpio_irq_type,
867 .set_wake = gpio_wake_enable,
868 };
869
870 static struct irqchip mpuio_irq_chip = {
871 .ack = mpuio_ack_irq,
872 .mask = mpuio_mask_irq,
873 .unmask = mpuio_unmask_irq
874 };
875
876 static int initialized;
877 static struct clk * gpio_ick;
878 static struct clk * gpio_fck;
879
880 static int __init _omap_gpio_init(void)
881 {
882 int i;
883 struct gpio_bank *bank;
884
885 initialized = 1;
886
887 if (cpu_is_omap15xx()) {
888 gpio_ick = clk_get(NULL, "arm_gpio_ck");
889 if (IS_ERR(gpio_ick))
890 printk("Could not get arm_gpio_ck\n");
891 else
892 clk_enable(gpio_ick);
893 }
894 if (cpu_is_omap24xx()) {
895 gpio_ick = clk_get(NULL, "gpios_ick");
896 if (IS_ERR(gpio_ick))
897 printk("Could not get gpios_ick\n");
898 else
899 clk_enable(gpio_ick);
900 gpio_fck = clk_get(NULL, "gpios_fck");
901 if (IS_ERR(gpio_ick))
902 printk("Could not get gpios_fck\n");
903 else
904 clk_enable(gpio_fck);
905 }
906
907 #ifdef CONFIG_ARCH_OMAP15XX
908 if (cpu_is_omap15xx()) {
909 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
910 gpio_bank_count = 2;
911 gpio_bank = gpio_bank_1510;
912 }
913 #endif
914 #if defined(CONFIG_ARCH_OMAP16XX)
915 if (cpu_is_omap16xx()) {
916 u32 rev;
917
918 gpio_bank_count = 5;
919 gpio_bank = gpio_bank_1610;
920 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
921 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
922 (rev >> 4) & 0x0f, rev & 0x0f);
923 }
924 #endif
925 #ifdef CONFIG_ARCH_OMAP730
926 if (cpu_is_omap730()) {
927 printk(KERN_INFO "OMAP730 GPIO hardware\n");
928 gpio_bank_count = 7;
929 gpio_bank = gpio_bank_730;
930 }
931 #endif
932 #ifdef CONFIG_ARCH_OMAP24XX
933 if (cpu_is_omap24xx()) {
934 int rev;
935
936 gpio_bank_count = 4;
937 gpio_bank = gpio_bank_24xx;
938 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
939 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
940 (rev >> 4) & 0x0f, rev & 0x0f);
941 }
942 #endif
943 for (i = 0; i < gpio_bank_count; i++) {
944 int j, gpio_count = 16;
945
946 bank = &gpio_bank[i];
947 bank->reserved_map = 0;
948 bank->base = IO_ADDRESS(bank->base);
949 spin_lock_init(&bank->lock);
950 if (bank->method == METHOD_MPUIO) {
951 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
952 }
953 #ifdef CONFIG_ARCH_OMAP15XX
954 if (bank->method == METHOD_GPIO_1510) {
955 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
956 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
957 }
958 #endif
959 #if defined(CONFIG_ARCH_OMAP16XX)
960 if (bank->method == METHOD_GPIO_1610) {
961 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
962 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
963 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
964 }
965 #endif
966 #ifdef CONFIG_ARCH_OMAP730
967 if (bank->method == METHOD_GPIO_730) {
968 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
969 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
970
971 gpio_count = 32; /* 730 has 32-bit GPIOs */
972 }
973 #endif
974 #ifdef CONFIG_ARCH_OMAP24XX
975 if (bank->method == METHOD_GPIO_24XX) {
976 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
977 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
978
979 gpio_count = 32;
980 }
981 #endif
982 for (j = bank->virtual_irq_start;
983 j < bank->virtual_irq_start + gpio_count; j++) {
984 if (bank->method == METHOD_MPUIO)
985 set_irq_chip(j, &mpuio_irq_chip);
986 else
987 set_irq_chip(j, &gpio_irq_chip);
988 set_irq_handler(j, do_simple_IRQ);
989 set_irq_flags(j, IRQF_VALID);
990 }
991 set_irq_chained_handler(bank->irq, gpio_irq_handler);
992 set_irq_data(bank->irq, bank);
993 }
994
995 /* Enable system clock for GPIO module.
996 * The CAM_CLK_CTRL *is* really the right place. */
997 if (cpu_is_omap16xx())
998 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
999
1000 return 0;
1001 }
1002
1003 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1004 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1005 {
1006 int i;
1007
1008 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1009 return 0;
1010
1011 for (i = 0; i < gpio_bank_count; i++) {
1012 struct gpio_bank *bank = &gpio_bank[i];
1013 void __iomem *wake_status;
1014 void __iomem *wake_clear;
1015 void __iomem *wake_set;
1016
1017 switch (bank->method) {
1018 case METHOD_GPIO_1610:
1019 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1020 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1021 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1022 break;
1023 case METHOD_GPIO_24XX:
1024 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1025 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1026 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1027 break;
1028 default:
1029 continue;
1030 }
1031
1032 spin_lock(&bank->lock);
1033 bank->saved_wakeup = __raw_readl(wake_status);
1034 __raw_writel(0xffffffff, wake_clear);
1035 __raw_writel(bank->suspend_wakeup, wake_set);
1036 spin_unlock(&bank->lock);
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int omap_gpio_resume(struct sys_device *dev)
1043 {
1044 int i;
1045
1046 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1047 return 0;
1048
1049 for (i = 0; i < gpio_bank_count; i++) {
1050 struct gpio_bank *bank = &gpio_bank[i];
1051 void __iomem *wake_clear;
1052 void __iomem *wake_set;
1053
1054 switch (bank->method) {
1055 case METHOD_GPIO_1610:
1056 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1057 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1058 break;
1059 case METHOD_GPIO_24XX:
1060 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1061 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1062 break;
1063 default:
1064 continue;
1065 }
1066
1067 spin_lock(&bank->lock);
1068 __raw_writel(0xffffffff, wake_clear);
1069 __raw_writel(bank->saved_wakeup, wake_set);
1070 spin_unlock(&bank->lock);
1071 }
1072
1073 return 0;
1074 }
1075
1076 static struct sysdev_class omap_gpio_sysclass = {
1077 set_kset_name("gpio"),
1078 .suspend = omap_gpio_suspend,
1079 .resume = omap_gpio_resume,
1080 };
1081
1082 static struct sys_device omap_gpio_device = {
1083 .id = 0,
1084 .cls = &omap_gpio_sysclass,
1085 };
1086 #endif
1087
1088 /*
1089 * This may get called early from board specific init
1090 * for boards that have interrupts routed via FPGA.
1091 */
1092 int omap_gpio_init(void)
1093 {
1094 if (!initialized)
1095 return _omap_gpio_init();
1096 else
1097 return 0;
1098 }
1099
1100 static int __init omap_gpio_sysinit(void)
1101 {
1102 int ret = 0;
1103
1104 if (!initialized)
1105 ret = _omap_gpio_init();
1106
1107 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1108 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1109 if (ret == 0) {
1110 ret = sysdev_class_register(&omap_gpio_sysclass);
1111 if (ret == 0)
1112 ret = sysdev_register(&omap_gpio_device);
1113 }
1114 }
1115 #endif
1116
1117 return ret;
1118 }
1119
1120 EXPORT_SYMBOL(omap_request_gpio);
1121 EXPORT_SYMBOL(omap_free_gpio);
1122 EXPORT_SYMBOL(omap_set_gpio_direction);
1123 EXPORT_SYMBOL(omap_set_gpio_dataout);
1124 EXPORT_SYMBOL(omap_get_gpio_datain);
1125
1126 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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