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ARM: OMAP: Implement workaround for GPIO wakeup bug in OMAP2420 silicon
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21
22 #include <asm/hardware.h>
23 #include <asm/irq.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
27
28 #include <asm/io.h>
29
30 /*
31 * OMAP1510 GPIO registers
32 */
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41
42 #define OMAP1510_IH_GPIO_BASE 64
43
44 /*
45 * OMAP1610 specific GPIO registers
46 */
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68
69 /*
70 * OMAP730 specific GPIO registers
71 */
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
84
85 /*
86 * omap24xx specific GPIO registers
87 */
88 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP24XX_GPIO_REVISION 0x0000
93 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
94 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
95 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
96 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
97 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
113
114 struct gpio_bank {
115 void __iomem *base;
116 u16 irq;
117 u16 virtual_irq_start;
118 int method;
119 u32 reserved_map;
120 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
121 u32 suspend_wakeup;
122 u32 saved_wakeup;
123 #endif
124 #ifdef CONFIG_ARCH_OMAP24XX
125 u32 non_wakeup_gpios;
126 u32 enabled_non_wakeup_gpios;
127
128 u32 saved_datain;
129 u32 saved_fallingdetect;
130 u32 saved_risingdetect;
131 #endif
132 spinlock_t lock;
133 };
134
135 #define METHOD_MPUIO 0
136 #define METHOD_GPIO_1510 1
137 #define METHOD_GPIO_1610 2
138 #define METHOD_GPIO_730 3
139 #define METHOD_GPIO_24XX 4
140
141 #ifdef CONFIG_ARCH_OMAP16XX
142 static struct gpio_bank gpio_bank_1610[5] = {
143 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
144 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
145 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
146 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
147 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
148 };
149 #endif
150
151 #ifdef CONFIG_ARCH_OMAP15XX
152 static struct gpio_bank gpio_bank_1510[2] = {
153 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
154 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
155 };
156 #endif
157
158 #ifdef CONFIG_ARCH_OMAP730
159 static struct gpio_bank gpio_bank_730[7] = {
160 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
161 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
162 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
163 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
164 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
165 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
166 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
167 };
168 #endif
169
170 #ifdef CONFIG_ARCH_OMAP24XX
171 static struct gpio_bank gpio_bank_24xx[4] = {
172 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
173 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
174 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
175 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
176 };
177 #endif
178
179 static struct gpio_bank *gpio_bank;
180 static int gpio_bank_count;
181
182 static inline struct gpio_bank *get_gpio_bank(int gpio)
183 {
184 #ifdef CONFIG_ARCH_OMAP15XX
185 if (cpu_is_omap15xx()) {
186 if (OMAP_GPIO_IS_MPUIO(gpio))
187 return &gpio_bank[0];
188 return &gpio_bank[1];
189 }
190 #endif
191 #if defined(CONFIG_ARCH_OMAP16XX)
192 if (cpu_is_omap16xx()) {
193 if (OMAP_GPIO_IS_MPUIO(gpio))
194 return &gpio_bank[0];
195 return &gpio_bank[1 + (gpio >> 4)];
196 }
197 #endif
198 #ifdef CONFIG_ARCH_OMAP730
199 if (cpu_is_omap730()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 5)];
203 }
204 #endif
205 #ifdef CONFIG_ARCH_OMAP24XX
206 if (cpu_is_omap24xx())
207 return &gpio_bank[gpio >> 5];
208 #endif
209 }
210
211 static inline int get_gpio_index(int gpio)
212 {
213 #ifdef CONFIG_ARCH_OMAP730
214 if (cpu_is_omap730())
215 return gpio & 0x1f;
216 #endif
217 #ifdef CONFIG_ARCH_OMAP24XX
218 if (cpu_is_omap24xx())
219 return gpio & 0x1f;
220 #endif
221 return gpio & 0x0f;
222 }
223
224 static inline int gpio_valid(int gpio)
225 {
226 if (gpio < 0)
227 return -1;
228 #ifndef CONFIG_ARCH_OMAP24XX
229 if (OMAP_GPIO_IS_MPUIO(gpio)) {
230 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
231 return -1;
232 return 0;
233 }
234 #endif
235 #ifdef CONFIG_ARCH_OMAP15XX
236 if (cpu_is_omap15xx() && gpio < 16)
237 return 0;
238 #endif
239 #if defined(CONFIG_ARCH_OMAP16XX)
240 if ((cpu_is_omap16xx()) && gpio < 64)
241 return 0;
242 #endif
243 #ifdef CONFIG_ARCH_OMAP730
244 if (cpu_is_omap730() && gpio < 192)
245 return 0;
246 #endif
247 #ifdef CONFIG_ARCH_OMAP24XX
248 if (cpu_is_omap24xx() && gpio < 128)
249 return 0;
250 #endif
251 return -1;
252 }
253
254 static int check_gpio(int gpio)
255 {
256 if (unlikely(gpio_valid(gpio)) < 0) {
257 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
258 dump_stack();
259 return -1;
260 }
261 return 0;
262 }
263
264 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
265 {
266 void __iomem *reg = bank->base;
267 u32 l;
268
269 switch (bank->method) {
270 case METHOD_MPUIO:
271 reg += OMAP_MPUIO_IO_CNTL;
272 break;
273 case METHOD_GPIO_1510:
274 reg += OMAP1510_GPIO_DIR_CONTROL;
275 break;
276 case METHOD_GPIO_1610:
277 reg += OMAP1610_GPIO_DIRECTION;
278 break;
279 case METHOD_GPIO_730:
280 reg += OMAP730_GPIO_DIR_CONTROL;
281 break;
282 case METHOD_GPIO_24XX:
283 reg += OMAP24XX_GPIO_OE;
284 break;
285 }
286 l = __raw_readl(reg);
287 if (is_input)
288 l |= 1 << gpio;
289 else
290 l &= ~(1 << gpio);
291 __raw_writel(l, reg);
292 }
293
294 void omap_set_gpio_direction(int gpio, int is_input)
295 {
296 struct gpio_bank *bank;
297
298 if (check_gpio(gpio) < 0)
299 return;
300 bank = get_gpio_bank(gpio);
301 spin_lock(&bank->lock);
302 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
303 spin_unlock(&bank->lock);
304 }
305
306 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
307 {
308 void __iomem *reg = bank->base;
309 u32 l = 0;
310
311 switch (bank->method) {
312 case METHOD_MPUIO:
313 reg += OMAP_MPUIO_OUTPUT;
314 l = __raw_readl(reg);
315 if (enable)
316 l |= 1 << gpio;
317 else
318 l &= ~(1 << gpio);
319 break;
320 case METHOD_GPIO_1510:
321 reg += OMAP1510_GPIO_DATA_OUTPUT;
322 l = __raw_readl(reg);
323 if (enable)
324 l |= 1 << gpio;
325 else
326 l &= ~(1 << gpio);
327 break;
328 case METHOD_GPIO_1610:
329 if (enable)
330 reg += OMAP1610_GPIO_SET_DATAOUT;
331 else
332 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
333 l = 1 << gpio;
334 break;
335 case METHOD_GPIO_730:
336 reg += OMAP730_GPIO_DATA_OUTPUT;
337 l = __raw_readl(reg);
338 if (enable)
339 l |= 1 << gpio;
340 else
341 l &= ~(1 << gpio);
342 break;
343 case METHOD_GPIO_24XX:
344 if (enable)
345 reg += OMAP24XX_GPIO_SETDATAOUT;
346 else
347 reg += OMAP24XX_GPIO_CLEARDATAOUT;
348 l = 1 << gpio;
349 break;
350 default:
351 BUG();
352 return;
353 }
354 __raw_writel(l, reg);
355 }
356
357 void omap_set_gpio_dataout(int gpio, int enable)
358 {
359 struct gpio_bank *bank;
360
361 if (check_gpio(gpio) < 0)
362 return;
363 bank = get_gpio_bank(gpio);
364 spin_lock(&bank->lock);
365 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
366 spin_unlock(&bank->lock);
367 }
368
369 int omap_get_gpio_datain(int gpio)
370 {
371 struct gpio_bank *bank;
372 void __iomem *reg;
373
374 if (check_gpio(gpio) < 0)
375 return -1;
376 bank = get_gpio_bank(gpio);
377 reg = bank->base;
378 switch (bank->method) {
379 case METHOD_MPUIO:
380 reg += OMAP_MPUIO_INPUT_LATCH;
381 break;
382 case METHOD_GPIO_1510:
383 reg += OMAP1510_GPIO_DATA_INPUT;
384 break;
385 case METHOD_GPIO_1610:
386 reg += OMAP1610_GPIO_DATAIN;
387 break;
388 case METHOD_GPIO_730:
389 reg += OMAP730_GPIO_DATA_INPUT;
390 break;
391 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_DATAIN;
393 break;
394 default:
395 BUG();
396 return -1;
397 }
398 return (__raw_readl(reg)
399 & (1 << get_gpio_index(gpio))) != 0;
400 }
401
402 #define MOD_REG_BIT(reg, bit_mask, set) \
403 do { \
404 int l = __raw_readl(base + reg); \
405 if (set) l |= bit_mask; \
406 else l &= ~bit_mask; \
407 __raw_writel(l, base + reg); \
408 } while(0)
409
410 #ifdef CONFIG_ARCH_OMAP24XX
411 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
412 {
413 void __iomem *base = bank->base;
414 u32 gpio_bit = 1 << gpio;
415
416 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
417 trigger & __IRQT_LOWLVL);
418 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
419 trigger & __IRQT_HIGHLVL);
420 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
421 trigger & __IRQT_RISEDGE);
422 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
423 trigger & __IRQT_FALEDGE);
424 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
425 if (trigger != 0)
426 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
427 else
428 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
429 } else {
430 if (trigger != 0)
431 bank->enabled_non_wakeup_gpios |= gpio_bit;
432 else
433 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
434 }
435 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
436 * triggering requested. */
437 }
438 #endif
439
440 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
441 {
442 void __iomem *reg = bank->base;
443 u32 l = 0;
444
445 switch (bank->method) {
446 case METHOD_MPUIO:
447 reg += OMAP_MPUIO_GPIO_INT_EDGE;
448 l = __raw_readl(reg);
449 if (trigger & __IRQT_RISEDGE)
450 l |= 1 << gpio;
451 else if (trigger & __IRQT_FALEDGE)
452 l &= ~(1 << gpio);
453 else
454 goto bad;
455 break;
456 case METHOD_GPIO_1510:
457 reg += OMAP1510_GPIO_INT_CONTROL;
458 l = __raw_readl(reg);
459 if (trigger & __IRQT_RISEDGE)
460 l |= 1 << gpio;
461 else if (trigger & __IRQT_FALEDGE)
462 l &= ~(1 << gpio);
463 else
464 goto bad;
465 break;
466 #ifdef CONFIG_ARCH_OMAP16XX
467 case METHOD_GPIO_1610:
468 if (gpio & 0x08)
469 reg += OMAP1610_GPIO_EDGE_CTRL2;
470 else
471 reg += OMAP1610_GPIO_EDGE_CTRL1;
472 gpio &= 0x07;
473 /* We allow only edge triggering, i.e. two lowest bits */
474 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
475 BUG();
476 l = __raw_readl(reg);
477 l &= ~(3 << (gpio << 1));
478 if (trigger & __IRQT_RISEDGE)
479 l |= 2 << (gpio << 1);
480 if (trigger & __IRQT_FALEDGE)
481 l |= 1 << (gpio << 1);
482 if (trigger)
483 /* Enable wake-up during idle for dynamic tick */
484 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
485 else
486 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
487 break;
488 #endif
489 #ifdef CONFIG_ARCH_OMAP730
490 case METHOD_GPIO_730:
491 reg += OMAP730_GPIO_INT_CONTROL;
492 l = __raw_readl(reg);
493 if (trigger & __IRQT_RISEDGE)
494 l |= 1 << gpio;
495 else if (trigger & __IRQT_FALEDGE)
496 l &= ~(1 << gpio);
497 else
498 goto bad;
499 break;
500 #endif
501 #ifdef CONFIG_ARCH_OMAP24XX
502 case METHOD_GPIO_24XX:
503 set_24xx_gpio_triggering(bank, gpio, trigger);
504 break;
505 #endif
506 default:
507 BUG();
508 goto bad;
509 }
510 __raw_writel(l, reg);
511 return 0;
512 bad:
513 return -EINVAL;
514 }
515
516 static int gpio_irq_type(unsigned irq, unsigned type)
517 {
518 struct gpio_bank *bank;
519 unsigned gpio;
520 int retval;
521
522 if (irq > IH_MPUIO_BASE)
523 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
524 else
525 gpio = irq - IH_GPIO_BASE;
526
527 if (check_gpio(gpio) < 0)
528 return -EINVAL;
529
530 if (type & IRQT_PROBE)
531 return -EINVAL;
532 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
533 return -EINVAL;
534
535 bank = get_gpio_bank(gpio);
536 spin_lock(&bank->lock);
537 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
538 spin_unlock(&bank->lock);
539 return retval;
540 }
541
542 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
543 {
544 void __iomem *reg = bank->base;
545
546 switch (bank->method) {
547 case METHOD_MPUIO:
548 /* MPUIO irqstatus is reset by reading the status register,
549 * so do nothing here */
550 return;
551 case METHOD_GPIO_1510:
552 reg += OMAP1510_GPIO_INT_STATUS;
553 break;
554 case METHOD_GPIO_1610:
555 reg += OMAP1610_GPIO_IRQSTATUS1;
556 break;
557 case METHOD_GPIO_730:
558 reg += OMAP730_GPIO_INT_STATUS;
559 break;
560 case METHOD_GPIO_24XX:
561 reg += OMAP24XX_GPIO_IRQSTATUS1;
562 break;
563 default:
564 BUG();
565 return;
566 }
567 __raw_writel(gpio_mask, reg);
568
569 /* Workaround for clearing DSP GPIO interrupts to allow retention */
570 if (cpu_is_omap2420())
571 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
572 }
573
574 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
575 {
576 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
577 }
578
579 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
580 {
581 void __iomem *reg = bank->base;
582 int inv = 0;
583 u32 l;
584 u32 mask;
585
586 switch (bank->method) {
587 case METHOD_MPUIO:
588 reg += OMAP_MPUIO_GPIO_MASKIT;
589 mask = 0xffff;
590 inv = 1;
591 break;
592 case METHOD_GPIO_1510:
593 reg += OMAP1510_GPIO_INT_MASK;
594 mask = 0xffff;
595 inv = 1;
596 break;
597 case METHOD_GPIO_1610:
598 reg += OMAP1610_GPIO_IRQENABLE1;
599 mask = 0xffff;
600 break;
601 case METHOD_GPIO_730:
602 reg += OMAP730_GPIO_INT_MASK;
603 mask = 0xffffffff;
604 inv = 1;
605 break;
606 case METHOD_GPIO_24XX:
607 reg += OMAP24XX_GPIO_IRQENABLE1;
608 mask = 0xffffffff;
609 break;
610 default:
611 BUG();
612 return 0;
613 }
614
615 l = __raw_readl(reg);
616 if (inv)
617 l = ~l;
618 l &= mask;
619 return l;
620 }
621
622 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
623 {
624 void __iomem *reg = bank->base;
625 u32 l;
626
627 switch (bank->method) {
628 case METHOD_MPUIO:
629 reg += OMAP_MPUIO_GPIO_MASKIT;
630 l = __raw_readl(reg);
631 if (enable)
632 l &= ~(gpio_mask);
633 else
634 l |= gpio_mask;
635 break;
636 case METHOD_GPIO_1510:
637 reg += OMAP1510_GPIO_INT_MASK;
638 l = __raw_readl(reg);
639 if (enable)
640 l &= ~(gpio_mask);
641 else
642 l |= gpio_mask;
643 break;
644 case METHOD_GPIO_1610:
645 if (enable)
646 reg += OMAP1610_GPIO_SET_IRQENABLE1;
647 else
648 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
649 l = gpio_mask;
650 break;
651 case METHOD_GPIO_730:
652 reg += OMAP730_GPIO_INT_MASK;
653 l = __raw_readl(reg);
654 if (enable)
655 l &= ~(gpio_mask);
656 else
657 l |= gpio_mask;
658 break;
659 case METHOD_GPIO_24XX:
660 if (enable)
661 reg += OMAP24XX_GPIO_SETIRQENABLE1;
662 else
663 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
664 l = gpio_mask;
665 break;
666 default:
667 BUG();
668 return;
669 }
670 __raw_writel(l, reg);
671 }
672
673 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
674 {
675 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
676 }
677
678 /*
679 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
680 * 1510 does not seem to have a wake-up register. If JTAG is connected
681 * to the target, system will wake up always on GPIO events. While
682 * system is running all registered GPIO interrupts need to have wake-up
683 * enabled. When system is suspended, only selected GPIO interrupts need
684 * to have wake-up enabled.
685 */
686 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
687 {
688 switch (bank->method) {
689 #ifdef CONFIG_ARCH_OMAP16XX
690 case METHOD_GPIO_1610:
691 spin_lock(&bank->lock);
692 if (enable)
693 bank->suspend_wakeup |= (1 << gpio);
694 else
695 bank->suspend_wakeup &= ~(1 << gpio);
696 spin_unlock(&bank->lock);
697 return 0;
698 #endif
699 #ifdef CONFIG_ARCH_OMAP24XX
700 case METHOD_GPIO_24XX:
701 spin_lock(&bank->lock);
702 if (enable) {
703 if (bank->non_wakeup_gpios & (1 << gpio)) {
704 printk(KERN_ERR "Unable to enable wakeup on"
705 "non-wakeup GPIO%d\n",
706 (bank - gpio_bank) * 32 + gpio);
707 spin_unlock(&bank->lock);
708 return -EINVAL;
709 }
710 bank->suspend_wakeup |= (1 << gpio);
711 } else
712 bank->suspend_wakeup &= ~(1 << gpio);
713 spin_unlock(&bank->lock);
714 return 0;
715 #endif
716 default:
717 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
718 bank->method);
719 return -EINVAL;
720 }
721 }
722
723 static void _reset_gpio(struct gpio_bank *bank, int gpio)
724 {
725 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
726 _set_gpio_irqenable(bank, gpio, 0);
727 _clear_gpio_irqstatus(bank, gpio);
728 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
729 }
730
731 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
732 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
733 {
734 unsigned int gpio = irq - IH_GPIO_BASE;
735 struct gpio_bank *bank;
736 int retval;
737
738 if (check_gpio(gpio) < 0)
739 return -ENODEV;
740 bank = get_gpio_bank(gpio);
741 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
742
743 return retval;
744 }
745
746 int omap_request_gpio(int gpio)
747 {
748 struct gpio_bank *bank;
749
750 if (check_gpio(gpio) < 0)
751 return -EINVAL;
752
753 bank = get_gpio_bank(gpio);
754 spin_lock(&bank->lock);
755 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
756 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
757 dump_stack();
758 spin_unlock(&bank->lock);
759 return -1;
760 }
761 bank->reserved_map |= (1 << get_gpio_index(gpio));
762
763 /* Set trigger to none. You need to enable the desired trigger with
764 * request_irq() or set_irq_type().
765 */
766 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
767
768 #ifdef CONFIG_ARCH_OMAP15XX
769 if (bank->method == METHOD_GPIO_1510) {
770 void __iomem *reg;
771
772 /* Claim the pin for MPU */
773 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
774 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
775 }
776 #endif
777 spin_unlock(&bank->lock);
778
779 return 0;
780 }
781
782 void omap_free_gpio(int gpio)
783 {
784 struct gpio_bank *bank;
785
786 if (check_gpio(gpio) < 0)
787 return;
788 bank = get_gpio_bank(gpio);
789 spin_lock(&bank->lock);
790 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
791 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
792 dump_stack();
793 spin_unlock(&bank->lock);
794 return;
795 }
796 #ifdef CONFIG_ARCH_OMAP16XX
797 if (bank->method == METHOD_GPIO_1610) {
798 /* Disable wake-up during idle for dynamic tick */
799 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
800 __raw_writel(1 << get_gpio_index(gpio), reg);
801 }
802 #endif
803 #ifdef CONFIG_ARCH_OMAP24XX
804 if (bank->method == METHOD_GPIO_24XX) {
805 /* Disable wake-up during idle for dynamic tick */
806 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
807 __raw_writel(1 << get_gpio_index(gpio), reg);
808 }
809 #endif
810 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
811 _reset_gpio(bank, gpio);
812 spin_unlock(&bank->lock);
813 }
814
815 /*
816 * We need to unmask the GPIO bank interrupt as soon as possible to
817 * avoid missing GPIO interrupts for other lines in the bank.
818 * Then we need to mask-read-clear-unmask the triggered GPIO lines
819 * in the bank to avoid missing nested interrupts for a GPIO line.
820 * If we wait to unmask individual GPIO lines in the bank after the
821 * line's interrupt handler has been run, we may miss some nested
822 * interrupts.
823 */
824 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
825 {
826 void __iomem *isr_reg = NULL;
827 u32 isr;
828 unsigned int gpio_irq;
829 struct gpio_bank *bank;
830 u32 retrigger = 0;
831 int unmasked = 0;
832
833 desc->chip->ack(irq);
834
835 bank = get_irq_data(irq);
836 if (bank->method == METHOD_MPUIO)
837 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
838 #ifdef CONFIG_ARCH_OMAP15XX
839 if (bank->method == METHOD_GPIO_1510)
840 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
841 #endif
842 #if defined(CONFIG_ARCH_OMAP16XX)
843 if (bank->method == METHOD_GPIO_1610)
844 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
845 #endif
846 #ifdef CONFIG_ARCH_OMAP730
847 if (bank->method == METHOD_GPIO_730)
848 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
849 #endif
850 #ifdef CONFIG_ARCH_OMAP24XX
851 if (bank->method == METHOD_GPIO_24XX)
852 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
853 #endif
854 while(1) {
855 u32 isr_saved, level_mask = 0;
856 u32 enabled;
857
858 enabled = _get_gpio_irqbank_mask(bank);
859 isr_saved = isr = __raw_readl(isr_reg) & enabled;
860
861 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
862 isr &= 0x0000ffff;
863
864 if (cpu_is_omap24xx()) {
865 level_mask =
866 __raw_readl(bank->base +
867 OMAP24XX_GPIO_LEVELDETECT0) |
868 __raw_readl(bank->base +
869 OMAP24XX_GPIO_LEVELDETECT1);
870 level_mask &= enabled;
871 }
872
873 /* clear edge sensitive interrupts before handler(s) are
874 called so that we don't miss any interrupt occurred while
875 executing them */
876 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
877 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
878 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
879
880 /* if there is only edge sensitive GPIO pin interrupts
881 configured, we could unmask GPIO bank interrupt immediately */
882 if (!level_mask && !unmasked) {
883 unmasked = 1;
884 desc->chip->unmask(irq);
885 }
886
887 isr |= retrigger;
888 retrigger = 0;
889 if (!isr)
890 break;
891
892 gpio_irq = bank->virtual_irq_start;
893 for (; isr != 0; isr >>= 1, gpio_irq++) {
894 struct irq_desc *d;
895 int irq_mask;
896 if (!(isr & 1))
897 continue;
898 d = irq_desc + gpio_irq;
899 /* Don't run the handler if it's already running
900 * or was disabled lazely.
901 */
902 if (unlikely((d->depth ||
903 (d->status & IRQ_INPROGRESS)))) {
904 irq_mask = 1 <<
905 (gpio_irq - bank->virtual_irq_start);
906 /* The unmasking will be done by
907 * enable_irq in case it is disabled or
908 * after returning from the handler if
909 * it's already running.
910 */
911 _enable_gpio_irqbank(bank, irq_mask, 0);
912 if (!d->depth) {
913 /* Level triggered interrupts
914 * won't ever be reentered
915 */
916 BUG_ON(level_mask & irq_mask);
917 d->status |= IRQ_PENDING;
918 }
919 continue;
920 }
921
922 desc_handle_irq(gpio_irq, d);
923
924 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
925 irq_mask = 1 <<
926 (gpio_irq - bank->virtual_irq_start);
927 d->status &= ~IRQ_PENDING;
928 _enable_gpio_irqbank(bank, irq_mask, 1);
929 retrigger |= irq_mask;
930 }
931 }
932
933 if (cpu_is_omap24xx()) {
934 /* clear level sensitive interrupts after handler(s) */
935 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
936 _clear_gpio_irqbank(bank, isr_saved & level_mask);
937 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
938 }
939
940 }
941 /* if bank has any level sensitive GPIO pin interrupt
942 configured, we must unmask the bank interrupt only after
943 handler(s) are executed in order to avoid spurious bank
944 interrupt */
945 if (!unmasked)
946 desc->chip->unmask(irq);
947
948 }
949
950 static void gpio_irq_shutdown(unsigned int irq)
951 {
952 unsigned int gpio = irq - IH_GPIO_BASE;
953 struct gpio_bank *bank = get_gpio_bank(gpio);
954
955 _reset_gpio(bank, gpio);
956 }
957
958 static void gpio_ack_irq(unsigned int irq)
959 {
960 unsigned int gpio = irq - IH_GPIO_BASE;
961 struct gpio_bank *bank = get_gpio_bank(gpio);
962
963 _clear_gpio_irqstatus(bank, gpio);
964 }
965
966 static void gpio_mask_irq(unsigned int irq)
967 {
968 unsigned int gpio = irq - IH_GPIO_BASE;
969 struct gpio_bank *bank = get_gpio_bank(gpio);
970
971 _set_gpio_irqenable(bank, gpio, 0);
972 }
973
974 static void gpio_unmask_irq(unsigned int irq)
975 {
976 unsigned int gpio = irq - IH_GPIO_BASE;
977 unsigned int gpio_idx = get_gpio_index(gpio);
978 struct gpio_bank *bank = get_gpio_bank(gpio);
979
980 _set_gpio_irqenable(bank, gpio_idx, 1);
981 }
982
983 static void mpuio_ack_irq(unsigned int irq)
984 {
985 /* The ISR is reset automatically, so do nothing here. */
986 }
987
988 static void mpuio_mask_irq(unsigned int irq)
989 {
990 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
991 struct gpio_bank *bank = get_gpio_bank(gpio);
992
993 _set_gpio_irqenable(bank, gpio, 0);
994 }
995
996 static void mpuio_unmask_irq(unsigned int irq)
997 {
998 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
999 struct gpio_bank *bank = get_gpio_bank(gpio);
1000
1001 _set_gpio_irqenable(bank, gpio, 1);
1002 }
1003
1004 static struct irq_chip gpio_irq_chip = {
1005 .name = "GPIO",
1006 .shutdown = gpio_irq_shutdown,
1007 .ack = gpio_ack_irq,
1008 .mask = gpio_mask_irq,
1009 .unmask = gpio_unmask_irq,
1010 .set_type = gpio_irq_type,
1011 .set_wake = gpio_wake_enable,
1012 };
1013
1014 static struct irq_chip mpuio_irq_chip = {
1015 .name = "MPUIO",
1016 .ack = mpuio_ack_irq,
1017 .mask = mpuio_mask_irq,
1018 .unmask = mpuio_unmask_irq,
1019 .set_type = gpio_irq_type,
1020 };
1021
1022 static int initialized;
1023 static struct clk * gpio_ick;
1024 static struct clk * gpio_fck;
1025
1026 static int __init _omap_gpio_init(void)
1027 {
1028 int i;
1029 struct gpio_bank *bank;
1030
1031 initialized = 1;
1032
1033 if (cpu_is_omap15xx()) {
1034 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1035 if (IS_ERR(gpio_ick))
1036 printk("Could not get arm_gpio_ck\n");
1037 else
1038 clk_enable(gpio_ick);
1039 }
1040 if (cpu_is_omap24xx()) {
1041 gpio_ick = clk_get(NULL, "gpios_ick");
1042 if (IS_ERR(gpio_ick))
1043 printk("Could not get gpios_ick\n");
1044 else
1045 clk_enable(gpio_ick);
1046 gpio_fck = clk_get(NULL, "gpios_fck");
1047 if (IS_ERR(gpio_fck))
1048 printk("Could not get gpios_fck\n");
1049 else
1050 clk_enable(gpio_fck);
1051 }
1052
1053 #ifdef CONFIG_ARCH_OMAP15XX
1054 if (cpu_is_omap15xx()) {
1055 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1056 gpio_bank_count = 2;
1057 gpio_bank = gpio_bank_1510;
1058 }
1059 #endif
1060 #if defined(CONFIG_ARCH_OMAP16XX)
1061 if (cpu_is_omap16xx()) {
1062 u32 rev;
1063
1064 gpio_bank_count = 5;
1065 gpio_bank = gpio_bank_1610;
1066 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1067 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1068 (rev >> 4) & 0x0f, rev & 0x0f);
1069 }
1070 #endif
1071 #ifdef CONFIG_ARCH_OMAP730
1072 if (cpu_is_omap730()) {
1073 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1074 gpio_bank_count = 7;
1075 gpio_bank = gpio_bank_730;
1076 }
1077 #endif
1078 #ifdef CONFIG_ARCH_OMAP24XX
1079 if (cpu_is_omap24xx()) {
1080 int rev;
1081
1082 gpio_bank_count = 4;
1083 gpio_bank = gpio_bank_24xx;
1084 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1085 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1086 (rev >> 4) & 0x0f, rev & 0x0f);
1087 }
1088 #endif
1089 for (i = 0; i < gpio_bank_count; i++) {
1090 int j, gpio_count = 16;
1091
1092 bank = &gpio_bank[i];
1093 bank->reserved_map = 0;
1094 bank->base = IO_ADDRESS(bank->base);
1095 spin_lock_init(&bank->lock);
1096 if (bank->method == METHOD_MPUIO) {
1097 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1098 }
1099 #ifdef CONFIG_ARCH_OMAP15XX
1100 if (bank->method == METHOD_GPIO_1510) {
1101 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1102 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1103 }
1104 #endif
1105 #if defined(CONFIG_ARCH_OMAP16XX)
1106 if (bank->method == METHOD_GPIO_1610) {
1107 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1108 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1109 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1110 }
1111 #endif
1112 #ifdef CONFIG_ARCH_OMAP730
1113 if (bank->method == METHOD_GPIO_730) {
1114 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1115 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1116
1117 gpio_count = 32; /* 730 has 32-bit GPIOs */
1118 }
1119 #endif
1120 #ifdef CONFIG_ARCH_OMAP24XX
1121 if (bank->method == METHOD_GPIO_24XX) {
1122 static const u32 non_wakeup_gpios[] = {
1123 0xe203ffc0, 0x08700040
1124 };
1125
1126 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1127 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1128 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1129
1130 /* Initialize interface clock ungated, module enabled */
1131 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1132 if (i < ARRAY_SIZE(non_wakeup_gpios))
1133 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1134 gpio_count = 32;
1135 }
1136 #endif
1137 for (j = bank->virtual_irq_start;
1138 j < bank->virtual_irq_start + gpio_count; j++) {
1139 if (bank->method == METHOD_MPUIO)
1140 set_irq_chip(j, &mpuio_irq_chip);
1141 else
1142 set_irq_chip(j, &gpio_irq_chip);
1143 set_irq_handler(j, handle_simple_irq);
1144 set_irq_flags(j, IRQF_VALID);
1145 }
1146 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1147 set_irq_data(bank->irq, bank);
1148 }
1149
1150 /* Enable system clock for GPIO module.
1151 * The CAM_CLK_CTRL *is* really the right place. */
1152 if (cpu_is_omap16xx())
1153 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1154
1155 #ifdef CONFIG_ARCH_OMAP24XX
1156 /* Enable autoidle for the OCP interface */
1157 if (cpu_is_omap24xx())
1158 omap_writel(1 << 0, 0x48019010);
1159 #endif
1160
1161 return 0;
1162 }
1163
1164 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1165 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1166 {
1167 int i;
1168
1169 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1170 return 0;
1171
1172 for (i = 0; i < gpio_bank_count; i++) {
1173 struct gpio_bank *bank = &gpio_bank[i];
1174 void __iomem *wake_status;
1175 void __iomem *wake_clear;
1176 void __iomem *wake_set;
1177
1178 switch (bank->method) {
1179 case METHOD_GPIO_1610:
1180 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1181 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1182 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1183 break;
1184 case METHOD_GPIO_24XX:
1185 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1186 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1187 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1188 break;
1189 default:
1190 continue;
1191 }
1192
1193 spin_lock(&bank->lock);
1194 bank->saved_wakeup = __raw_readl(wake_status);
1195 __raw_writel(0xffffffff, wake_clear);
1196 __raw_writel(bank->suspend_wakeup, wake_set);
1197 spin_unlock(&bank->lock);
1198 }
1199
1200 return 0;
1201 }
1202
1203 static int omap_gpio_resume(struct sys_device *dev)
1204 {
1205 int i;
1206
1207 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1208 return 0;
1209
1210 for (i = 0; i < gpio_bank_count; i++) {
1211 struct gpio_bank *bank = &gpio_bank[i];
1212 void __iomem *wake_clear;
1213 void __iomem *wake_set;
1214
1215 switch (bank->method) {
1216 case METHOD_GPIO_1610:
1217 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1218 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1219 break;
1220 case METHOD_GPIO_24XX:
1221 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1222 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1223 break;
1224 default:
1225 continue;
1226 }
1227
1228 spin_lock(&bank->lock);
1229 __raw_writel(0xffffffff, wake_clear);
1230 __raw_writel(bank->saved_wakeup, wake_set);
1231 spin_unlock(&bank->lock);
1232 }
1233
1234 return 0;
1235 }
1236
1237 static struct sysdev_class omap_gpio_sysclass = {
1238 set_kset_name("gpio"),
1239 .suspend = omap_gpio_suspend,
1240 .resume = omap_gpio_resume,
1241 };
1242
1243 static struct sys_device omap_gpio_device = {
1244 .id = 0,
1245 .cls = &omap_gpio_sysclass,
1246 };
1247
1248 #endif
1249
1250 #ifdef CONFIG_ARCH_OMAP24XX
1251
1252 static int workaround_enabled;
1253
1254 void omap2_gpio_prepare_for_retention(void)
1255 {
1256 int i, c = 0;
1257
1258 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1259 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1260 for (i = 0; i < gpio_bank_count; i++) {
1261 struct gpio_bank *bank = &gpio_bank[i];
1262 u32 l1, l2;
1263
1264 if (!(bank->enabled_non_wakeup_gpios))
1265 continue;
1266 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1267 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1268 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1269 bank->saved_fallingdetect = l1;
1270 bank->saved_risingdetect = l2;
1271 l1 &= ~bank->enabled_non_wakeup_gpios;
1272 l2 &= ~bank->enabled_non_wakeup_gpios;
1273 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1274 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1275 c++;
1276 }
1277 if (!c) {
1278 workaround_enabled = 0;
1279 return;
1280 }
1281 workaround_enabled = 1;
1282 }
1283
1284 void omap2_gpio_resume_after_retention(void)
1285 {
1286 int i;
1287
1288 if (!workaround_enabled)
1289 return;
1290 for (i = 0; i < gpio_bank_count; i++) {
1291 struct gpio_bank *bank = &gpio_bank[i];
1292 u32 l;
1293
1294 if (!(bank->enabled_non_wakeup_gpios))
1295 continue;
1296 __raw_writel(bank->saved_fallingdetect,
1297 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1298 __raw_writel(bank->saved_risingdetect,
1299 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1300 /* Check if any of the non-wakeup interrupt GPIOs have changed
1301 * state. If so, generate an IRQ by software. This is
1302 * horribly racy, but it's the best we can do to work around
1303 * this silicon bug. */
1304 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1305 l ^= bank->saved_datain;
1306 l &= bank->non_wakeup_gpios;
1307 if (l) {
1308 u32 old0, old1;
1309
1310 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1311 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1312 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1313 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1314 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1315 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1316 }
1317 }
1318
1319 }
1320
1321 #endif
1322
1323 /*
1324 * This may get called early from board specific init
1325 * for boards that have interrupts routed via FPGA.
1326 */
1327 int omap_gpio_init(void)
1328 {
1329 if (!initialized)
1330 return _omap_gpio_init();
1331 else
1332 return 0;
1333 }
1334
1335 static int __init omap_gpio_sysinit(void)
1336 {
1337 int ret = 0;
1338
1339 if (!initialized)
1340 ret = _omap_gpio_init();
1341
1342 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1343 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1344 if (ret == 0) {
1345 ret = sysdev_class_register(&omap_gpio_sysclass);
1346 if (ret == 0)
1347 ret = sysdev_register(&omap_gpio_device);
1348 }
1349 }
1350 #endif
1351
1352 return ret;
1353 }
1354
1355 EXPORT_SYMBOL(omap_request_gpio);
1356 EXPORT_SYMBOL(omap_free_gpio);
1357 EXPORT_SYMBOL(omap_set_gpio_direction);
1358 EXPORT_SYMBOL(omap_set_gpio_dataout);
1359 EXPORT_SYMBOL(omap_get_gpio_datain);
1360
1361 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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