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ARM: OMAP4: Update the GPIO support
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP730 specific GPIO registers
72 */
73 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
85
86 /*
87 * OMAP850 specific GPIO registers
88 */
89 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
101
102 /*
103 * omap24xx specific GPIO registers
104 */
105 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
109
110 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
115
116 #define OMAP24XX_GPIO_REVISION 0x0000
117 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
118 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
119 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
120 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
122 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
123 #define OMAP24XX_GPIO_WAKE_EN 0x0020
124 #define OMAP24XX_GPIO_CTRL 0x0030
125 #define OMAP24XX_GPIO_OE 0x0034
126 #define OMAP24XX_GPIO_DATAIN 0x0038
127 #define OMAP24XX_GPIO_DATAOUT 0x003c
128 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
131 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
132 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
134 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137 #define OMAP24XX_GPIO_SETWKUENA 0x0084
138 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
140
141 #define OMAP4_GPIO_REVISION 0x0000
142 #define OMAP4_GPIO_SYSCONFIG 0x0010
143 #define OMAP4_GPIO_EOI 0x0020
144 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
145 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
146 #define OMAP4_GPIO_IRQSTATUS0 0x002c
147 #define OMAP4_GPIO_IRQSTATUS1 0x0030
148 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
149 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
150 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
151 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
152 #define OMAP4_GPIO_IRQWAKEN0 0x0044
153 #define OMAP4_GPIO_IRQWAKEN1 0x0048
154 #define OMAP4_GPIO_SYSSTATUS 0x0104
155 #define OMAP4_GPIO_CTRL 0x0130
156 #define OMAP4_GPIO_OE 0x0134
157 #define OMAP4_GPIO_DATAIN 0x0138
158 #define OMAP4_GPIO_DATAOUT 0x013c
159 #define OMAP4_GPIO_LEVELDETECT0 0x0140
160 #define OMAP4_GPIO_LEVELDETECT1 0x0144
161 #define OMAP4_GPIO_RISINGDETECT 0x0148
162 #define OMAP4_GPIO_FALLINGDETECT 0x014c
163 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
164 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
165 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
166 #define OMAP4_GPIO_SETDATAOUT 0x0194
167 /*
168 * omap34xx specific GPIO registers
169 */
170
171 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
172 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
173 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
174 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
175 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
176 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
177
178 /*
179 * OMAP44XX specific GPIO registers
180 */
181 #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
182 #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
183 #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
184 #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
185 #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
186 #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
187
188 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
189
190 struct gpio_bank {
191 void __iomem *base;
192 u16 irq;
193 u16 virtual_irq_start;
194 int method;
195 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
196 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
197 u32 suspend_wakeup;
198 u32 saved_wakeup;
199 #endif
200 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
201 defined(CONFIG_ARCH_OMAP4)
202 u32 non_wakeup_gpios;
203 u32 enabled_non_wakeup_gpios;
204
205 u32 saved_datain;
206 u32 saved_fallingdetect;
207 u32 saved_risingdetect;
208 #endif
209 u32 level_mask;
210 spinlock_t lock;
211 struct gpio_chip chip;
212 struct clk *dbck;
213 };
214
215 #define METHOD_MPUIO 0
216 #define METHOD_GPIO_1510 1
217 #define METHOD_GPIO_1610 2
218 #define METHOD_GPIO_730 3
219 #define METHOD_GPIO_850 4
220 #define METHOD_GPIO_24XX 5
221
222 #ifdef CONFIG_ARCH_OMAP16XX
223 static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
229 };
230 #endif
231
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
236 };
237 #endif
238
239 #ifdef CONFIG_ARCH_OMAP730
240 static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
248 };
249 #endif
250
251 #ifdef CONFIG_ARCH_OMAP850
252 static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
260 };
261 #endif
262
263
264 #ifdef CONFIG_ARCH_OMAP24XX
265
266 static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
271 };
272
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
279 };
280
281 #endif
282
283 #ifdef CONFIG_ARCH_OMAP34XX
284 static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
291 };
292
293 #endif
294
295 #ifdef CONFIG_ARCH_OMAP4
296 static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
298 METHOD_GPIO_24XX },
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
300 METHOD_GPIO_24XX },
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
302 METHOD_GPIO_24XX },
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
304 METHOD_GPIO_24XX },
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
306 METHOD_GPIO_24XX },
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
308 METHOD_GPIO_24XX },
309 };
310
311 #endif
312
313 static struct gpio_bank *gpio_bank;
314 static int gpio_bank_count;
315
316 static inline struct gpio_bank *get_gpio_bank(int gpio)
317 {
318 if (cpu_is_omap15xx()) {
319 if (OMAP_GPIO_IS_MPUIO(gpio))
320 return &gpio_bank[0];
321 return &gpio_bank[1];
322 }
323 if (cpu_is_omap16xx()) {
324 if (OMAP_GPIO_IS_MPUIO(gpio))
325 return &gpio_bank[0];
326 return &gpio_bank[1 + (gpio >> 4)];
327 }
328 if (cpu_is_omap7xx()) {
329 if (OMAP_GPIO_IS_MPUIO(gpio))
330 return &gpio_bank[0];
331 return &gpio_bank[1 + (gpio >> 5)];
332 }
333 if (cpu_is_omap24xx())
334 return &gpio_bank[gpio >> 5];
335 if (cpu_is_omap34xx() || cpu_is_omap44xx())
336 return &gpio_bank[gpio >> 5];
337 BUG();
338 return NULL;
339 }
340
341 static inline int get_gpio_index(int gpio)
342 {
343 if (cpu_is_omap7xx())
344 return gpio & 0x1f;
345 if (cpu_is_omap24xx())
346 return gpio & 0x1f;
347 if (cpu_is_omap34xx() || cpu_is_omap44xx())
348 return gpio & 0x1f;
349 return gpio & 0x0f;
350 }
351
352 static inline int gpio_valid(int gpio)
353 {
354 if (gpio < 0)
355 return -1;
356 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
357 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
358 return -1;
359 return 0;
360 }
361 if (cpu_is_omap15xx() && gpio < 16)
362 return 0;
363 if ((cpu_is_omap16xx()) && gpio < 64)
364 return 0;
365 if (cpu_is_omap7xx() && gpio < 192)
366 return 0;
367 if (cpu_is_omap24xx() && gpio < 128)
368 return 0;
369 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
370 return 0;
371 return -1;
372 }
373
374 static int check_gpio(int gpio)
375 {
376 if (unlikely(gpio_valid(gpio)) < 0) {
377 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
378 dump_stack();
379 return -1;
380 }
381 return 0;
382 }
383
384 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
385 {
386 void __iomem *reg = bank->base;
387 u32 l;
388
389 switch (bank->method) {
390 #ifdef CONFIG_ARCH_OMAP1
391 case METHOD_MPUIO:
392 reg += OMAP_MPUIO_IO_CNTL;
393 break;
394 #endif
395 #ifdef CONFIG_ARCH_OMAP15XX
396 case METHOD_GPIO_1510:
397 reg += OMAP1510_GPIO_DIR_CONTROL;
398 break;
399 #endif
400 #ifdef CONFIG_ARCH_OMAP16XX
401 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_DIRECTION;
403 break;
404 #endif
405 #ifdef CONFIG_ARCH_OMAP730
406 case METHOD_GPIO_730:
407 reg += OMAP730_GPIO_DIR_CONTROL;
408 break;
409 #endif
410 #ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break;
414 #endif
415 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
416 case METHOD_GPIO_24XX:
417 reg += OMAP24XX_GPIO_OE;
418 break;
419 #endif
420 #if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
423 break;
424 #endif
425 default:
426 WARN_ON(1);
427 return;
428 }
429 l = __raw_readl(reg);
430 if (is_input)
431 l |= 1 << gpio;
432 else
433 l &= ~(1 << gpio);
434 __raw_writel(l, reg);
435 }
436
437 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
438 {
439 void __iomem *reg = bank->base;
440 u32 l = 0;
441
442 switch (bank->method) {
443 #ifdef CONFIG_ARCH_OMAP1
444 case METHOD_MPUIO:
445 reg += OMAP_MPUIO_OUTPUT;
446 l = __raw_readl(reg);
447 if (enable)
448 l |= 1 << gpio;
449 else
450 l &= ~(1 << gpio);
451 break;
452 #endif
453 #ifdef CONFIG_ARCH_OMAP15XX
454 case METHOD_GPIO_1510:
455 reg += OMAP1510_GPIO_DATA_OUTPUT;
456 l = __raw_readl(reg);
457 if (enable)
458 l |= 1 << gpio;
459 else
460 l &= ~(1 << gpio);
461 break;
462 #endif
463 #ifdef CONFIG_ARCH_OMAP16XX
464 case METHOD_GPIO_1610:
465 if (enable)
466 reg += OMAP1610_GPIO_SET_DATAOUT;
467 else
468 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
469 l = 1 << gpio;
470 break;
471 #endif
472 #ifdef CONFIG_ARCH_OMAP730
473 case METHOD_GPIO_730:
474 reg += OMAP730_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
476 if (enable)
477 l |= 1 << gpio;
478 else
479 l &= ~(1 << gpio);
480 break;
481 #endif
482 #ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg);
486 if (enable)
487 l |= 1 << gpio;
488 else
489 l &= ~(1 << gpio);
490 break;
491 #endif
492 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 case METHOD_GPIO_24XX:
494 if (enable)
495 reg += OMAP24XX_GPIO_SETDATAOUT;
496 else
497 reg += OMAP24XX_GPIO_CLEARDATAOUT;
498 l = 1 << gpio;
499 break;
500 #endif
501 #ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
503 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT;
505 else
506 reg += OMAP4_GPIO_CLEARDATAOUT;
507 l = 1 << gpio;
508 break;
509 #endif
510 default:
511 WARN_ON(1);
512 return;
513 }
514 __raw_writel(l, reg);
515 }
516
517 static int __omap_get_gpio_datain(int gpio)
518 {
519 struct gpio_bank *bank;
520 void __iomem *reg;
521
522 if (check_gpio(gpio) < 0)
523 return -EINVAL;
524 bank = get_gpio_bank(gpio);
525 reg = bank->base;
526 switch (bank->method) {
527 #ifdef CONFIG_ARCH_OMAP1
528 case METHOD_MPUIO:
529 reg += OMAP_MPUIO_INPUT_LATCH;
530 break;
531 #endif
532 #ifdef CONFIG_ARCH_OMAP15XX
533 case METHOD_GPIO_1510:
534 reg += OMAP1510_GPIO_DATA_INPUT;
535 break;
536 #endif
537 #ifdef CONFIG_ARCH_OMAP16XX
538 case METHOD_GPIO_1610:
539 reg += OMAP1610_GPIO_DATAIN;
540 break;
541 #endif
542 #ifdef CONFIG_ARCH_OMAP730
543 case METHOD_GPIO_730:
544 reg += OMAP730_GPIO_DATA_INPUT;
545 break;
546 #endif
547 #ifdef CONFIG_ARCH_OMAP850
548 case METHOD_GPIO_850:
549 reg += OMAP850_GPIO_DATA_INPUT;
550 break;
551 #endif
552 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
553 case METHOD_GPIO_24XX:
554 reg += OMAP24XX_GPIO_DATAIN;
555 break;
556 #endif
557 #ifdef CONFIG_ARCH_OMAP4
558 case METHOD_GPIO_24XX:
559 reg += OMAP4_GPIO_DATAIN;
560 break;
561 #endif
562 default:
563 return -EINVAL;
564 }
565 return (__raw_readl(reg)
566 & (1 << get_gpio_index(gpio))) != 0;
567 }
568
569 #define MOD_REG_BIT(reg, bit_mask, set) \
570 do { \
571 int l = __raw_readl(base + reg); \
572 if (set) l |= bit_mask; \
573 else l &= ~bit_mask; \
574 __raw_writel(l, base + reg); \
575 } while(0)
576
577 void omap_set_gpio_debounce(int gpio, int enable)
578 {
579 struct gpio_bank *bank;
580 void __iomem *reg;
581 unsigned long flags;
582 u32 val, l = 1 << get_gpio_index(gpio);
583
584 if (cpu_class_is_omap1())
585 return;
586
587 bank = get_gpio_bank(gpio);
588 reg = bank->base;
589 #ifdef CONFIG_ARCH_OMAP4
590 reg += OMAP4_GPIO_DEBOUNCENABLE;
591 #else
592 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
593 #endif
594
595 spin_lock_irqsave(&bank->lock, flags);
596 val = __raw_readl(reg);
597
598 if (enable && !(val & l))
599 val |= l;
600 else if (!enable && (val & l))
601 val &= ~l;
602 else
603 goto done;
604
605 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
606 if (enable)
607 clk_enable(bank->dbck);
608 else
609 clk_disable(bank->dbck);
610 }
611
612 __raw_writel(val, reg);
613 done:
614 spin_unlock_irqrestore(&bank->lock, flags);
615 }
616 EXPORT_SYMBOL(omap_set_gpio_debounce);
617
618 void omap_set_gpio_debounce_time(int gpio, int enc_time)
619 {
620 struct gpio_bank *bank;
621 void __iomem *reg;
622
623 if (cpu_class_is_omap1())
624 return;
625
626 bank = get_gpio_bank(gpio);
627 reg = bank->base;
628
629 enc_time &= 0xff;
630 #ifdef CONFIG_ARCH_OMAP4
631 reg += OMAP4_GPIO_DEBOUNCINGTIME;
632 #else
633 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
634 #endif
635 __raw_writel(enc_time, reg);
636 }
637 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
638
639 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
640 defined(CONFIG_ARCH_OMAP4)
641 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
642 int trigger)
643 {
644 void __iomem *base = bank->base;
645 u32 gpio_bit = 1 << gpio;
646 u32 val;
647
648 if (cpu_is_omap44xx()) {
649 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
650 trigger & IRQ_TYPE_LEVEL_LOW);
651 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
652 trigger & IRQ_TYPE_LEVEL_HIGH);
653 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
654 trigger & IRQ_TYPE_EDGE_RISING);
655 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
656 trigger & IRQ_TYPE_EDGE_FALLING);
657 } else {
658 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
659 trigger & IRQ_TYPE_LEVEL_LOW);
660 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
661 trigger & IRQ_TYPE_LEVEL_HIGH);
662 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
663 trigger & IRQ_TYPE_EDGE_RISING);
664 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
665 trigger & IRQ_TYPE_EDGE_FALLING);
666 }
667 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
668 if (cpu_is_omap44xx()) {
669 if (trigger != 0)
670 __raw_writel(1 << gpio, bank->base+
671 OMAP4_GPIO_IRQWAKEN0);
672 else {
673 val = __raw_readl(bank->base +
674 OMAP4_GPIO_IRQWAKEN0);
675 __raw_writel(val & (~(1 << gpio)), bank->base +
676 OMAP4_GPIO_IRQWAKEN0);
677 }
678 } else {
679 if (trigger != 0)
680 __raw_writel(1 << gpio, bank->base
681 + OMAP24XX_GPIO_SETWKUENA);
682 else
683 __raw_writel(1 << gpio, bank->base
684 + OMAP24XX_GPIO_CLEARWKUENA);
685 }
686 } else {
687 if (trigger != 0)
688 bank->enabled_non_wakeup_gpios |= gpio_bit;
689 else
690 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
691 }
692
693 if (cpu_is_omap44xx()) {
694 bank->level_mask =
695 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
696 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
697 } else {
698 bank->level_mask =
699 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
700 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
701 }
702 }
703 #endif
704
705 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
706 {
707 void __iomem *reg = bank->base;
708 u32 l = 0;
709
710 switch (bank->method) {
711 #ifdef CONFIG_ARCH_OMAP1
712 case METHOD_MPUIO:
713 reg += OMAP_MPUIO_GPIO_INT_EDGE;
714 l = __raw_readl(reg);
715 if (trigger & IRQ_TYPE_EDGE_RISING)
716 l |= 1 << gpio;
717 else if (trigger & IRQ_TYPE_EDGE_FALLING)
718 l &= ~(1 << gpio);
719 else
720 goto bad;
721 break;
722 #endif
723 #ifdef CONFIG_ARCH_OMAP15XX
724 case METHOD_GPIO_1510:
725 reg += OMAP1510_GPIO_INT_CONTROL;
726 l = __raw_readl(reg);
727 if (trigger & IRQ_TYPE_EDGE_RISING)
728 l |= 1 << gpio;
729 else if (trigger & IRQ_TYPE_EDGE_FALLING)
730 l &= ~(1 << gpio);
731 else
732 goto bad;
733 break;
734 #endif
735 #ifdef CONFIG_ARCH_OMAP16XX
736 case METHOD_GPIO_1610:
737 if (gpio & 0x08)
738 reg += OMAP1610_GPIO_EDGE_CTRL2;
739 else
740 reg += OMAP1610_GPIO_EDGE_CTRL1;
741 gpio &= 0x07;
742 l = __raw_readl(reg);
743 l &= ~(3 << (gpio << 1));
744 if (trigger & IRQ_TYPE_EDGE_RISING)
745 l |= 2 << (gpio << 1);
746 if (trigger & IRQ_TYPE_EDGE_FALLING)
747 l |= 1 << (gpio << 1);
748 if (trigger)
749 /* Enable wake-up during idle for dynamic tick */
750 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
751 else
752 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
753 break;
754 #endif
755 #ifdef CONFIG_ARCH_OMAP730
756 case METHOD_GPIO_730:
757 reg += OMAP730_GPIO_INT_CONTROL;
758 l = __raw_readl(reg);
759 if (trigger & IRQ_TYPE_EDGE_RISING)
760 l |= 1 << gpio;
761 else if (trigger & IRQ_TYPE_EDGE_FALLING)
762 l &= ~(1 << gpio);
763 else
764 goto bad;
765 break;
766 #endif
767 #ifdef CONFIG_ARCH_OMAP850
768 case METHOD_GPIO_850:
769 reg += OMAP850_GPIO_INT_CONTROL;
770 l = __raw_readl(reg);
771 if (trigger & IRQ_TYPE_EDGE_RISING)
772 l |= 1 << gpio;
773 else if (trigger & IRQ_TYPE_EDGE_FALLING)
774 l &= ~(1 << gpio);
775 else
776 goto bad;
777 break;
778 #endif
779 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
780 defined(CONFIG_ARCH_OMAP4)
781 case METHOD_GPIO_24XX:
782 set_24xx_gpio_triggering(bank, gpio, trigger);
783 break;
784 #endif
785 default:
786 goto bad;
787 }
788 __raw_writel(l, reg);
789 return 0;
790 bad:
791 return -EINVAL;
792 }
793
794 static int gpio_irq_type(unsigned irq, unsigned type)
795 {
796 struct gpio_bank *bank;
797 unsigned gpio;
798 int retval;
799 unsigned long flags;
800
801 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
802 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
803 else
804 gpio = irq - IH_GPIO_BASE;
805
806 if (check_gpio(gpio) < 0)
807 return -EINVAL;
808
809 if (type & ~IRQ_TYPE_SENSE_MASK)
810 return -EINVAL;
811
812 /* OMAP1 allows only only edge triggering */
813 if (!cpu_class_is_omap2()
814 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
815 return -EINVAL;
816
817 bank = get_irq_chip_data(irq);
818 spin_lock_irqsave(&bank->lock, flags);
819 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
820 if (retval == 0) {
821 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
822 irq_desc[irq].status |= type;
823 }
824 spin_unlock_irqrestore(&bank->lock, flags);
825
826 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
827 __set_irq_handler_unlocked(irq, handle_level_irq);
828 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
829 __set_irq_handler_unlocked(irq, handle_edge_irq);
830
831 return retval;
832 }
833
834 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
835 {
836 void __iomem *reg = bank->base;
837
838 switch (bank->method) {
839 #ifdef CONFIG_ARCH_OMAP1
840 case METHOD_MPUIO:
841 /* MPUIO irqstatus is reset by reading the status register,
842 * so do nothing here */
843 return;
844 #endif
845 #ifdef CONFIG_ARCH_OMAP15XX
846 case METHOD_GPIO_1510:
847 reg += OMAP1510_GPIO_INT_STATUS;
848 break;
849 #endif
850 #ifdef CONFIG_ARCH_OMAP16XX
851 case METHOD_GPIO_1610:
852 reg += OMAP1610_GPIO_IRQSTATUS1;
853 break;
854 #endif
855 #ifdef CONFIG_ARCH_OMAP730
856 case METHOD_GPIO_730:
857 reg += OMAP730_GPIO_INT_STATUS;
858 break;
859 #endif
860 #ifdef CONFIG_ARCH_OMAP850
861 case METHOD_GPIO_850:
862 reg += OMAP850_GPIO_INT_STATUS;
863 break;
864 #endif
865 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
866 case METHOD_GPIO_24XX:
867 reg += OMAP24XX_GPIO_IRQSTATUS1;
868 break;
869 #endif
870 #if defined(CONFIG_ARCH_OMAP4)
871 case METHOD_GPIO_24XX:
872 reg += OMAP4_GPIO_IRQSTATUS0;
873 break;
874 #endif
875 default:
876 WARN_ON(1);
877 return;
878 }
879 __raw_writel(gpio_mask, reg);
880
881 /* Workaround for clearing DSP GPIO interrupts to allow retention */
882 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
883 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
884 #endif
885 #if defined(CONFIG_ARCH_OMAP4)
886 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
887 #endif
888 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
889 __raw_writel(gpio_mask, reg);
890
891 /* Flush posted write for the irq status to avoid spurious interrupts */
892 __raw_readl(reg);
893 }
894 }
895
896 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
897 {
898 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
899 }
900
901 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
902 {
903 void __iomem *reg = bank->base;
904 int inv = 0;
905 u32 l;
906 u32 mask;
907
908 switch (bank->method) {
909 #ifdef CONFIG_ARCH_OMAP1
910 case METHOD_MPUIO:
911 reg += OMAP_MPUIO_GPIO_MASKIT;
912 mask = 0xffff;
913 inv = 1;
914 break;
915 #endif
916 #ifdef CONFIG_ARCH_OMAP15XX
917 case METHOD_GPIO_1510:
918 reg += OMAP1510_GPIO_INT_MASK;
919 mask = 0xffff;
920 inv = 1;
921 break;
922 #endif
923 #ifdef CONFIG_ARCH_OMAP16XX
924 case METHOD_GPIO_1610:
925 reg += OMAP1610_GPIO_IRQENABLE1;
926 mask = 0xffff;
927 break;
928 #endif
929 #ifdef CONFIG_ARCH_OMAP730
930 case METHOD_GPIO_730:
931 reg += OMAP730_GPIO_INT_MASK;
932 mask = 0xffffffff;
933 inv = 1;
934 break;
935 #endif
936 #ifdef CONFIG_ARCH_OMAP850
937 case METHOD_GPIO_850:
938 reg += OMAP850_GPIO_INT_MASK;
939 mask = 0xffffffff;
940 inv = 1;
941 break;
942 #endif
943 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
944 case METHOD_GPIO_24XX:
945 reg += OMAP24XX_GPIO_IRQENABLE1;
946 mask = 0xffffffff;
947 break;
948 #endif
949 #if defined(CONFIG_ARCH_OMAP4)
950 case METHOD_GPIO_24XX:
951 reg += OMAP4_GPIO_IRQSTATUSSET0;
952 mask = 0xffffffff;
953 break;
954 #endif
955 default:
956 WARN_ON(1);
957 return 0;
958 }
959
960 l = __raw_readl(reg);
961 if (inv)
962 l = ~l;
963 l &= mask;
964 return l;
965 }
966
967 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
968 {
969 void __iomem *reg = bank->base;
970 u32 l;
971
972 switch (bank->method) {
973 #ifdef CONFIG_ARCH_OMAP1
974 case METHOD_MPUIO:
975 reg += OMAP_MPUIO_GPIO_MASKIT;
976 l = __raw_readl(reg);
977 if (enable)
978 l &= ~(gpio_mask);
979 else
980 l |= gpio_mask;
981 break;
982 #endif
983 #ifdef CONFIG_ARCH_OMAP15XX
984 case METHOD_GPIO_1510:
985 reg += OMAP1510_GPIO_INT_MASK;
986 l = __raw_readl(reg);
987 if (enable)
988 l &= ~(gpio_mask);
989 else
990 l |= gpio_mask;
991 break;
992 #endif
993 #ifdef CONFIG_ARCH_OMAP16XX
994 case METHOD_GPIO_1610:
995 if (enable)
996 reg += OMAP1610_GPIO_SET_IRQENABLE1;
997 else
998 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
999 l = gpio_mask;
1000 break;
1001 #endif
1002 #ifdef CONFIG_ARCH_OMAP730
1003 case METHOD_GPIO_730:
1004 reg += OMAP730_GPIO_INT_MASK;
1005 l = __raw_readl(reg);
1006 if (enable)
1007 l &= ~(gpio_mask);
1008 else
1009 l |= gpio_mask;
1010 break;
1011 #endif
1012 #ifdef CONFIG_ARCH_OMAP850
1013 case METHOD_GPIO_850:
1014 reg += OMAP850_GPIO_INT_MASK;
1015 l = __raw_readl(reg);
1016 if (enable)
1017 l &= ~(gpio_mask);
1018 else
1019 l |= gpio_mask;
1020 break;
1021 #endif
1022 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1023 case METHOD_GPIO_24XX:
1024 if (enable)
1025 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1026 else
1027 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1028 l = gpio_mask;
1029 break;
1030 #endif
1031 #ifdef CONFIG_ARCH_OMAP4
1032 case METHOD_GPIO_24XX:
1033 if (enable)
1034 reg += OMAP4_GPIO_IRQSTATUSSET0;
1035 else
1036 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1037 l = gpio_mask;
1038 break;
1039 #endif
1040 default:
1041 WARN_ON(1);
1042 return;
1043 }
1044 __raw_writel(l, reg);
1045 }
1046
1047 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1048 {
1049 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1050 }
1051
1052 /*
1053 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1054 * 1510 does not seem to have a wake-up register. If JTAG is connected
1055 * to the target, system will wake up always on GPIO events. While
1056 * system is running all registered GPIO interrupts need to have wake-up
1057 * enabled. When system is suspended, only selected GPIO interrupts need
1058 * to have wake-up enabled.
1059 */
1060 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1061 {
1062 unsigned long flags;
1063
1064 switch (bank->method) {
1065 #ifdef CONFIG_ARCH_OMAP16XX
1066 case METHOD_MPUIO:
1067 case METHOD_GPIO_1610:
1068 spin_lock_irqsave(&bank->lock, flags);
1069 if (enable)
1070 bank->suspend_wakeup |= (1 << gpio);
1071 else
1072 bank->suspend_wakeup &= ~(1 << gpio);
1073 spin_unlock_irqrestore(&bank->lock, flags);
1074 return 0;
1075 #endif
1076 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1077 defined(CONFIG_ARCH_OMAP4)
1078 case METHOD_GPIO_24XX:
1079 if (bank->non_wakeup_gpios & (1 << gpio)) {
1080 printk(KERN_ERR "Unable to modify wakeup on "
1081 "non-wakeup GPIO%d\n",
1082 (bank - gpio_bank) * 32 + gpio);
1083 return -EINVAL;
1084 }
1085 spin_lock_irqsave(&bank->lock, flags);
1086 if (enable)
1087 bank->suspend_wakeup |= (1 << gpio);
1088 else
1089 bank->suspend_wakeup &= ~(1 << gpio);
1090 spin_unlock_irqrestore(&bank->lock, flags);
1091 return 0;
1092 #endif
1093 default:
1094 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1095 bank->method);
1096 return -EINVAL;
1097 }
1098 }
1099
1100 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1101 {
1102 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1103 _set_gpio_irqenable(bank, gpio, 0);
1104 _clear_gpio_irqstatus(bank, gpio);
1105 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1106 }
1107
1108 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1109 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1110 {
1111 unsigned int gpio = irq - IH_GPIO_BASE;
1112 struct gpio_bank *bank;
1113 int retval;
1114
1115 if (check_gpio(gpio) < 0)
1116 return -ENODEV;
1117 bank = get_irq_chip_data(irq);
1118 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1119
1120 return retval;
1121 }
1122
1123 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1124 {
1125 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1126 unsigned long flags;
1127
1128 spin_lock_irqsave(&bank->lock, flags);
1129
1130 /* Set trigger to none. You need to enable the desired trigger with
1131 * request_irq() or set_irq_type().
1132 */
1133 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1134
1135 #ifdef CONFIG_ARCH_OMAP15XX
1136 if (bank->method == METHOD_GPIO_1510) {
1137 void __iomem *reg;
1138
1139 /* Claim the pin for MPU */
1140 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1141 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1142 }
1143 #endif
1144 spin_unlock_irqrestore(&bank->lock, flags);
1145
1146 return 0;
1147 }
1148
1149 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1150 {
1151 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1152 unsigned long flags;
1153
1154 spin_lock_irqsave(&bank->lock, flags);
1155 #ifdef CONFIG_ARCH_OMAP16XX
1156 if (bank->method == METHOD_GPIO_1610) {
1157 /* Disable wake-up during idle for dynamic tick */
1158 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1159 __raw_writel(1 << offset, reg);
1160 }
1161 #endif
1162 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1163 defined(CONFIG_ARCH_OMAP4)
1164 if (bank->method == METHOD_GPIO_24XX) {
1165 /* Disable wake-up during idle for dynamic tick */
1166 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1167 __raw_writel(1 << offset, reg);
1168 }
1169 #endif
1170 _reset_gpio(bank, bank->chip.base + offset);
1171 spin_unlock_irqrestore(&bank->lock, flags);
1172 }
1173
1174 /*
1175 * We need to unmask the GPIO bank interrupt as soon as possible to
1176 * avoid missing GPIO interrupts for other lines in the bank.
1177 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1178 * in the bank to avoid missing nested interrupts for a GPIO line.
1179 * If we wait to unmask individual GPIO lines in the bank after the
1180 * line's interrupt handler has been run, we may miss some nested
1181 * interrupts.
1182 */
1183 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1184 {
1185 void __iomem *isr_reg = NULL;
1186 u32 isr;
1187 unsigned int gpio_irq;
1188 struct gpio_bank *bank;
1189 u32 retrigger = 0;
1190 int unmasked = 0;
1191
1192 desc->chip->ack(irq);
1193
1194 bank = get_irq_data(irq);
1195 #ifdef CONFIG_ARCH_OMAP1
1196 if (bank->method == METHOD_MPUIO)
1197 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1198 #endif
1199 #ifdef CONFIG_ARCH_OMAP15XX
1200 if (bank->method == METHOD_GPIO_1510)
1201 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1202 #endif
1203 #if defined(CONFIG_ARCH_OMAP16XX)
1204 if (bank->method == METHOD_GPIO_1610)
1205 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1206 #endif
1207 #ifdef CONFIG_ARCH_OMAP730
1208 if (bank->method == METHOD_GPIO_730)
1209 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1210 #endif
1211 #ifdef CONFIG_ARCH_OMAP850
1212 if (bank->method == METHOD_GPIO_850)
1213 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1214 #endif
1215 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1216 if (bank->method == METHOD_GPIO_24XX)
1217 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1218 #endif
1219 #if defined(CONFIG_ARCH_OMAP4)
1220 if (bank->method == METHOD_GPIO_24XX)
1221 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1222 #endif
1223 while(1) {
1224 u32 isr_saved, level_mask = 0;
1225 u32 enabled;
1226
1227 enabled = _get_gpio_irqbank_mask(bank);
1228 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1229
1230 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1231 isr &= 0x0000ffff;
1232
1233 if (cpu_class_is_omap2()) {
1234 level_mask = bank->level_mask & enabled;
1235 }
1236
1237 /* clear edge sensitive interrupts before handler(s) are
1238 called so that we don't miss any interrupt occurred while
1239 executing them */
1240 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1241 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1242 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1243
1244 /* if there is only edge sensitive GPIO pin interrupts
1245 configured, we could unmask GPIO bank interrupt immediately */
1246 if (!level_mask && !unmasked) {
1247 unmasked = 1;
1248 desc->chip->unmask(irq);
1249 }
1250
1251 isr |= retrigger;
1252 retrigger = 0;
1253 if (!isr)
1254 break;
1255
1256 gpio_irq = bank->virtual_irq_start;
1257 for (; isr != 0; isr >>= 1, gpio_irq++) {
1258 if (!(isr & 1))
1259 continue;
1260
1261 generic_handle_irq(gpio_irq);
1262 }
1263 }
1264 /* if bank has any level sensitive GPIO pin interrupt
1265 configured, we must unmask the bank interrupt only after
1266 handler(s) are executed in order to avoid spurious bank
1267 interrupt */
1268 if (!unmasked)
1269 desc->chip->unmask(irq);
1270
1271 }
1272
1273 static void gpio_irq_shutdown(unsigned int irq)
1274 {
1275 unsigned int gpio = irq - IH_GPIO_BASE;
1276 struct gpio_bank *bank = get_irq_chip_data(irq);
1277
1278 _reset_gpio(bank, gpio);
1279 }
1280
1281 static void gpio_ack_irq(unsigned int irq)
1282 {
1283 unsigned int gpio = irq - IH_GPIO_BASE;
1284 struct gpio_bank *bank = get_irq_chip_data(irq);
1285
1286 _clear_gpio_irqstatus(bank, gpio);
1287 }
1288
1289 static void gpio_mask_irq(unsigned int irq)
1290 {
1291 unsigned int gpio = irq - IH_GPIO_BASE;
1292 struct gpio_bank *bank = get_irq_chip_data(irq);
1293
1294 _set_gpio_irqenable(bank, gpio, 0);
1295 }
1296
1297 static void gpio_unmask_irq(unsigned int irq)
1298 {
1299 unsigned int gpio = irq - IH_GPIO_BASE;
1300 struct gpio_bank *bank = get_irq_chip_data(irq);
1301 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1302
1303 /* For level-triggered GPIOs, the clearing must be done after
1304 * the HW source is cleared, thus after the handler has run */
1305 if (bank->level_mask & irq_mask) {
1306 _set_gpio_irqenable(bank, gpio, 0);
1307 _clear_gpio_irqstatus(bank, gpio);
1308 }
1309
1310 _set_gpio_irqenable(bank, gpio, 1);
1311 }
1312
1313 static struct irq_chip gpio_irq_chip = {
1314 .name = "GPIO",
1315 .shutdown = gpio_irq_shutdown,
1316 .ack = gpio_ack_irq,
1317 .mask = gpio_mask_irq,
1318 .unmask = gpio_unmask_irq,
1319 .set_type = gpio_irq_type,
1320 .set_wake = gpio_wake_enable,
1321 };
1322
1323 /*---------------------------------------------------------------------*/
1324
1325 #ifdef CONFIG_ARCH_OMAP1
1326
1327 /* MPUIO uses the always-on 32k clock */
1328
1329 static void mpuio_ack_irq(unsigned int irq)
1330 {
1331 /* The ISR is reset automatically, so do nothing here. */
1332 }
1333
1334 static void mpuio_mask_irq(unsigned int irq)
1335 {
1336 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1337 struct gpio_bank *bank = get_irq_chip_data(irq);
1338
1339 _set_gpio_irqenable(bank, gpio, 0);
1340 }
1341
1342 static void mpuio_unmask_irq(unsigned int irq)
1343 {
1344 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1345 struct gpio_bank *bank = get_irq_chip_data(irq);
1346
1347 _set_gpio_irqenable(bank, gpio, 1);
1348 }
1349
1350 static struct irq_chip mpuio_irq_chip = {
1351 .name = "MPUIO",
1352 .ack = mpuio_ack_irq,
1353 .mask = mpuio_mask_irq,
1354 .unmask = mpuio_unmask_irq,
1355 .set_type = gpio_irq_type,
1356 #ifdef CONFIG_ARCH_OMAP16XX
1357 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1358 .set_wake = gpio_wake_enable,
1359 #endif
1360 };
1361
1362
1363 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1364
1365
1366 #ifdef CONFIG_ARCH_OMAP16XX
1367
1368 #include <linux/platform_device.h>
1369
1370 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1371 {
1372 struct gpio_bank *bank = platform_get_drvdata(pdev);
1373 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1374 unsigned long flags;
1375
1376 spin_lock_irqsave(&bank->lock, flags);
1377 bank->saved_wakeup = __raw_readl(mask_reg);
1378 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1379 spin_unlock_irqrestore(&bank->lock, flags);
1380
1381 return 0;
1382 }
1383
1384 static int omap_mpuio_resume_early(struct platform_device *pdev)
1385 {
1386 struct gpio_bank *bank = platform_get_drvdata(pdev);
1387 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1388 unsigned long flags;
1389
1390 spin_lock_irqsave(&bank->lock, flags);
1391 __raw_writel(bank->saved_wakeup, mask_reg);
1392 spin_unlock_irqrestore(&bank->lock, flags);
1393
1394 return 0;
1395 }
1396
1397 /* use platform_driver for this, now that there's no longer any
1398 * point to sys_device (other than not disturbing old code).
1399 */
1400 static struct platform_driver omap_mpuio_driver = {
1401 .suspend_late = omap_mpuio_suspend_late,
1402 .resume_early = omap_mpuio_resume_early,
1403 .driver = {
1404 .name = "mpuio",
1405 },
1406 };
1407
1408 static struct platform_device omap_mpuio_device = {
1409 .name = "mpuio",
1410 .id = -1,
1411 .dev = {
1412 .driver = &omap_mpuio_driver.driver,
1413 }
1414 /* could list the /proc/iomem resources */
1415 };
1416
1417 static inline void mpuio_init(void)
1418 {
1419 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1420
1421 if (platform_driver_register(&omap_mpuio_driver) == 0)
1422 (void) platform_device_register(&omap_mpuio_device);
1423 }
1424
1425 #else
1426 static inline void mpuio_init(void) {}
1427 #endif /* 16xx */
1428
1429 #else
1430
1431 extern struct irq_chip mpuio_irq_chip;
1432
1433 #define bank_is_mpuio(bank) 0
1434 static inline void mpuio_init(void) {}
1435
1436 #endif
1437
1438 /*---------------------------------------------------------------------*/
1439
1440 /* REVISIT these are stupid implementations! replace by ones that
1441 * don't switch on METHOD_* and which mostly avoid spinlocks
1442 */
1443
1444 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1445 {
1446 struct gpio_bank *bank;
1447 unsigned long flags;
1448
1449 bank = container_of(chip, struct gpio_bank, chip);
1450 spin_lock_irqsave(&bank->lock, flags);
1451 _set_gpio_direction(bank, offset, 1);
1452 spin_unlock_irqrestore(&bank->lock, flags);
1453 return 0;
1454 }
1455
1456 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1457 {
1458 return __omap_get_gpio_datain(chip->base + offset);
1459 }
1460
1461 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1462 {
1463 struct gpio_bank *bank;
1464 unsigned long flags;
1465
1466 bank = container_of(chip, struct gpio_bank, chip);
1467 spin_lock_irqsave(&bank->lock, flags);
1468 _set_gpio_dataout(bank, offset, value);
1469 _set_gpio_direction(bank, offset, 0);
1470 spin_unlock_irqrestore(&bank->lock, flags);
1471 return 0;
1472 }
1473
1474 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1475 {
1476 struct gpio_bank *bank;
1477 unsigned long flags;
1478
1479 bank = container_of(chip, struct gpio_bank, chip);
1480 spin_lock_irqsave(&bank->lock, flags);
1481 _set_gpio_dataout(bank, offset, value);
1482 spin_unlock_irqrestore(&bank->lock, flags);
1483 }
1484
1485 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1486 {
1487 struct gpio_bank *bank;
1488
1489 bank = container_of(chip, struct gpio_bank, chip);
1490 return bank->virtual_irq_start + offset;
1491 }
1492
1493 /*---------------------------------------------------------------------*/
1494
1495 static int initialized;
1496 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1497 static struct clk * gpio_ick;
1498 #endif
1499
1500 #if defined(CONFIG_ARCH_OMAP2)
1501 static struct clk * gpio_fck;
1502 #endif
1503
1504 #if defined(CONFIG_ARCH_OMAP2430)
1505 static struct clk * gpio5_ick;
1506 static struct clk * gpio5_fck;
1507 #endif
1508
1509 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1510 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1511 #endif
1512
1513 /* This lock class tells lockdep that GPIO irqs are in a different
1514 * category than their parents, so it won't report false recursion.
1515 */
1516 static struct lock_class_key gpio_lock_class;
1517
1518 static int __init _omap_gpio_init(void)
1519 {
1520 int i;
1521 int gpio = 0;
1522 struct gpio_bank *bank;
1523 char clk_name[11];
1524
1525 initialized = 1;
1526
1527 #if defined(CONFIG_ARCH_OMAP1)
1528 if (cpu_is_omap15xx()) {
1529 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1530 if (IS_ERR(gpio_ick))
1531 printk("Could not get arm_gpio_ck\n");
1532 else
1533 clk_enable(gpio_ick);
1534 }
1535 #endif
1536 #if defined(CONFIG_ARCH_OMAP2)
1537 if (cpu_class_is_omap2()) {
1538 gpio_ick = clk_get(NULL, "gpios_ick");
1539 if (IS_ERR(gpio_ick))
1540 printk("Could not get gpios_ick\n");
1541 else
1542 clk_enable(gpio_ick);
1543 gpio_fck = clk_get(NULL, "gpios_fck");
1544 if (IS_ERR(gpio_fck))
1545 printk("Could not get gpios_fck\n");
1546 else
1547 clk_enable(gpio_fck);
1548
1549 /*
1550 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1551 */
1552 #if defined(CONFIG_ARCH_OMAP2430)
1553 if (cpu_is_omap2430()) {
1554 gpio5_ick = clk_get(NULL, "gpio5_ick");
1555 if (IS_ERR(gpio5_ick))
1556 printk("Could not get gpio5_ick\n");
1557 else
1558 clk_enable(gpio5_ick);
1559 gpio5_fck = clk_get(NULL, "gpio5_fck");
1560 if (IS_ERR(gpio5_fck))
1561 printk("Could not get gpio5_fck\n");
1562 else
1563 clk_enable(gpio5_fck);
1564 }
1565 #endif
1566 }
1567 #endif
1568
1569 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1570 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1571 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1572 sprintf(clk_name, "gpio%d_ick", i + 1);
1573 gpio_iclks[i] = clk_get(NULL, clk_name);
1574 if (IS_ERR(gpio_iclks[i]))
1575 printk(KERN_ERR "Could not get %s\n", clk_name);
1576 else
1577 clk_enable(gpio_iclks[i]);
1578 }
1579 }
1580 #endif
1581
1582
1583 #ifdef CONFIG_ARCH_OMAP15XX
1584 if (cpu_is_omap15xx()) {
1585 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1586 gpio_bank_count = 2;
1587 gpio_bank = gpio_bank_1510;
1588 }
1589 #endif
1590 #if defined(CONFIG_ARCH_OMAP16XX)
1591 if (cpu_is_omap16xx()) {
1592 u32 rev;
1593
1594 gpio_bank_count = 5;
1595 gpio_bank = gpio_bank_1610;
1596 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1597 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1598 (rev >> 4) & 0x0f, rev & 0x0f);
1599 }
1600 #endif
1601 #ifdef CONFIG_ARCH_OMAP730
1602 if (cpu_is_omap730()) {
1603 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1604 gpio_bank_count = 7;
1605 gpio_bank = gpio_bank_730;
1606 }
1607 #endif
1608 #ifdef CONFIG_ARCH_OMAP850
1609 if (cpu_is_omap850()) {
1610 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1611 gpio_bank_count = 7;
1612 gpio_bank = gpio_bank_850;
1613 }
1614 #endif
1615
1616 #ifdef CONFIG_ARCH_OMAP24XX
1617 if (cpu_is_omap242x()) {
1618 int rev;
1619
1620 gpio_bank_count = 4;
1621 gpio_bank = gpio_bank_242x;
1622 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1623 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1624 (rev >> 4) & 0x0f, rev & 0x0f);
1625 }
1626 if (cpu_is_omap243x()) {
1627 int rev;
1628
1629 gpio_bank_count = 5;
1630 gpio_bank = gpio_bank_243x;
1631 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1632 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1633 (rev >> 4) & 0x0f, rev & 0x0f);
1634 }
1635 #endif
1636 #ifdef CONFIG_ARCH_OMAP34XX
1637 if (cpu_is_omap34xx()) {
1638 int rev;
1639
1640 gpio_bank_count = OMAP34XX_NR_GPIOS;
1641 gpio_bank = gpio_bank_34xx;
1642 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1643 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1644 (rev >> 4) & 0x0f, rev & 0x0f);
1645 }
1646 #endif
1647 #ifdef CONFIG_ARCH_OMAP4
1648 if (cpu_is_omap44xx()) {
1649 int rev;
1650
1651 gpio_bank_count = OMAP34XX_NR_GPIOS;
1652 gpio_bank = gpio_bank_44xx;
1653 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1654 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1655 (rev >> 4) & 0x0f, rev & 0x0f);
1656 }
1657 #endif
1658 for (i = 0; i < gpio_bank_count; i++) {
1659 int j, gpio_count = 16;
1660
1661 bank = &gpio_bank[i];
1662 spin_lock_init(&bank->lock);
1663 if (bank_is_mpuio(bank))
1664 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1665 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1666 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1667 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1668 }
1669 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1670 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1671 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1672 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1673 }
1674 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1675 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1676 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1677
1678 gpio_count = 32; /* 730 has 32-bit GPIOs */
1679 }
1680
1681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1682 defined(CONFIG_ARCH_OMAP4)
1683 if (bank->method == METHOD_GPIO_24XX) {
1684 static const u32 non_wakeup_gpios[] = {
1685 0xe203ffc0, 0x08700040
1686 };
1687 if (cpu_is_omap44xx()) {
1688 __raw_writel(0xffffffff, bank->base +
1689 OMAP4_GPIO_IRQSTATUSCLR0);
1690 __raw_writew(0x0015, bank->base +
1691 OMAP4_GPIO_SYSCONFIG);
1692 __raw_writel(0x00000000, bank->base +
1693 OMAP4_GPIO_DEBOUNCENABLE);
1694 /* Initialize interface clock ungated, module enabled */
1695 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1696 } else {
1697 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1698 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1699 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1700 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1701
1702 /* Initialize interface clock ungated, module enabled */
1703 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1704 }
1705 if (i < ARRAY_SIZE(non_wakeup_gpios))
1706 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1707 gpio_count = 32;
1708 }
1709 #endif
1710 /* REVISIT eventually switch from OMAP-specific gpio structs
1711 * over to the generic ones
1712 */
1713 bank->chip.request = omap_gpio_request;
1714 bank->chip.free = omap_gpio_free;
1715 bank->chip.direction_input = gpio_input;
1716 bank->chip.get = gpio_get;
1717 bank->chip.direction_output = gpio_output;
1718 bank->chip.set = gpio_set;
1719 bank->chip.to_irq = gpio_2irq;
1720 if (bank_is_mpuio(bank)) {
1721 bank->chip.label = "mpuio";
1722 #ifdef CONFIG_ARCH_OMAP16XX
1723 bank->chip.dev = &omap_mpuio_device.dev;
1724 #endif
1725 bank->chip.base = OMAP_MPUIO(0);
1726 } else {
1727 bank->chip.label = "gpio";
1728 bank->chip.base = gpio;
1729 gpio += gpio_count;
1730 }
1731 bank->chip.ngpio = gpio_count;
1732
1733 gpiochip_add(&bank->chip);
1734
1735 for (j = bank->virtual_irq_start;
1736 j < bank->virtual_irq_start + gpio_count; j++) {
1737 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1738 set_irq_chip_data(j, bank);
1739 if (bank_is_mpuio(bank))
1740 set_irq_chip(j, &mpuio_irq_chip);
1741 else
1742 set_irq_chip(j, &gpio_irq_chip);
1743 set_irq_handler(j, handle_simple_irq);
1744 set_irq_flags(j, IRQF_VALID);
1745 }
1746 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1747 set_irq_data(bank->irq, bank);
1748
1749 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1750 sprintf(clk_name, "gpio%d_dbck", i + 1);
1751 bank->dbck = clk_get(NULL, clk_name);
1752 if (IS_ERR(bank->dbck))
1753 printk(KERN_ERR "Could not get %s\n", clk_name);
1754 }
1755 }
1756
1757 /* Enable system clock for GPIO module.
1758 * The CAM_CLK_CTRL *is* really the right place. */
1759 if (cpu_is_omap16xx())
1760 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1761
1762 /* Enable autoidle for the OCP interface */
1763 if (cpu_is_omap24xx())
1764 omap_writel(1 << 0, 0x48019010);
1765 if (cpu_is_omap34xx())
1766 omap_writel(1 << 0, 0x48306814);
1767
1768 return 0;
1769 }
1770
1771 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1772 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1773 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1774 {
1775 int i;
1776
1777 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1778 return 0;
1779
1780 for (i = 0; i < gpio_bank_count; i++) {
1781 struct gpio_bank *bank = &gpio_bank[i];
1782 void __iomem *wake_status;
1783 void __iomem *wake_clear;
1784 void __iomem *wake_set;
1785 unsigned long flags;
1786
1787 switch (bank->method) {
1788 #ifdef CONFIG_ARCH_OMAP16XX
1789 case METHOD_GPIO_1610:
1790 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1791 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1792 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1793 break;
1794 #endif
1795 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1796 case METHOD_GPIO_24XX:
1797 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1798 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1799 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1800 break;
1801 #endif
1802 #ifdef CONFIG_ARCH_OMAP4
1803 case METHOD_GPIO_24XX:
1804 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1805 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1806 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1807 break;
1808 #endif
1809 default:
1810 continue;
1811 }
1812
1813 spin_lock_irqsave(&bank->lock, flags);
1814 bank->saved_wakeup = __raw_readl(wake_status);
1815 __raw_writel(0xffffffff, wake_clear);
1816 __raw_writel(bank->suspend_wakeup, wake_set);
1817 spin_unlock_irqrestore(&bank->lock, flags);
1818 }
1819
1820 return 0;
1821 }
1822
1823 static int omap_gpio_resume(struct sys_device *dev)
1824 {
1825 int i;
1826
1827 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1828 return 0;
1829
1830 for (i = 0; i < gpio_bank_count; i++) {
1831 struct gpio_bank *bank = &gpio_bank[i];
1832 void __iomem *wake_clear;
1833 void __iomem *wake_set;
1834 unsigned long flags;
1835
1836 switch (bank->method) {
1837 #ifdef CONFIG_ARCH_OMAP16XX
1838 case METHOD_GPIO_1610:
1839 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1840 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1841 break;
1842 #endif
1843 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1844 case METHOD_GPIO_24XX:
1845 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1846 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1847 break;
1848 #endif
1849 #ifdef CONFIG_ARCH_OMAP4
1850 case METHOD_GPIO_24XX:
1851 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1852 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1853 break;
1854 #endif
1855 default:
1856 continue;
1857 }
1858
1859 spin_lock_irqsave(&bank->lock, flags);
1860 __raw_writel(0xffffffff, wake_clear);
1861 __raw_writel(bank->saved_wakeup, wake_set);
1862 spin_unlock_irqrestore(&bank->lock, flags);
1863 }
1864
1865 return 0;
1866 }
1867
1868 static struct sysdev_class omap_gpio_sysclass = {
1869 .name = "gpio",
1870 .suspend = omap_gpio_suspend,
1871 .resume = omap_gpio_resume,
1872 };
1873
1874 static struct sys_device omap_gpio_device = {
1875 .id = 0,
1876 .cls = &omap_gpio_sysclass,
1877 };
1878
1879 #endif
1880
1881 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1882 defined(CONFIG_ARCH_OMAP4)
1883
1884 static int workaround_enabled;
1885
1886 void omap2_gpio_prepare_for_retention(void)
1887 {
1888 int i, c = 0;
1889
1890 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1891 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1892 for (i = 0; i < gpio_bank_count; i++) {
1893 struct gpio_bank *bank = &gpio_bank[i];
1894 u32 l1, l2;
1895
1896 if (!(bank->enabled_non_wakeup_gpios))
1897 continue;
1898 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1899 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1900 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1901 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1902 #endif
1903 #ifdef CONFIG_ARCH_OMAP4
1904 bank->saved_datain = __raw_readl(bank->base +
1905 OMAP4_GPIO_DATAIN);
1906 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1907 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1908 #endif
1909 bank->saved_fallingdetect = l1;
1910 bank->saved_risingdetect = l2;
1911 l1 &= ~bank->enabled_non_wakeup_gpios;
1912 l2 &= ~bank->enabled_non_wakeup_gpios;
1913 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1914 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1915 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1916 #endif
1917 #ifdef CONFIG_ARCH_OMAP4
1918 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1919 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1920 #endif
1921 c++;
1922 }
1923 if (!c) {
1924 workaround_enabled = 0;
1925 return;
1926 }
1927 workaround_enabled = 1;
1928 }
1929
1930 void omap2_gpio_resume_after_retention(void)
1931 {
1932 int i;
1933
1934 if (!workaround_enabled)
1935 return;
1936 for (i = 0; i < gpio_bank_count; i++) {
1937 struct gpio_bank *bank = &gpio_bank[i];
1938 u32 l;
1939
1940 if (!(bank->enabled_non_wakeup_gpios))
1941 continue;
1942 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1943 __raw_writel(bank->saved_fallingdetect,
1944 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1945 __raw_writel(bank->saved_risingdetect,
1946 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1947 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1948 #endif
1949 #ifdef CONFIG_ARCH_OMAP4
1950 __raw_writel(bank->saved_fallingdetect,
1951 bank->base + OMAP4_GPIO_FALLINGDETECT);
1952 __raw_writel(bank->saved_risingdetect,
1953 bank->base + OMAP4_GPIO_RISINGDETECT);
1954 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1955 #endif
1956 /* Check if any of the non-wakeup interrupt GPIOs have changed
1957 * state. If so, generate an IRQ by software. This is
1958 * horribly racy, but it's the best we can do to work around
1959 * this silicon bug. */
1960 l ^= bank->saved_datain;
1961 l &= bank->non_wakeup_gpios;
1962 if (l) {
1963 u32 old0, old1;
1964 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1965 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1966 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1967 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1968 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1969 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1970 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1971 #endif
1972 #ifdef CONFIG_ARCH_OMAP4
1973 old0 = __raw_readl(bank->base +
1974 OMAP4_GPIO_LEVELDETECT0);
1975 old1 = __raw_readl(bank->base +
1976 OMAP4_GPIO_LEVELDETECT1);
1977 __raw_writel(old0 | l, bank->base +
1978 OMAP4_GPIO_LEVELDETECT0);
1979 __raw_writel(old1 | l, bank->base +
1980 OMAP4_GPIO_LEVELDETECT1);
1981 __raw_writel(old0, bank->base +
1982 OMAP4_GPIO_LEVELDETECT0);
1983 __raw_writel(old1, bank->base +
1984 OMAP4_GPIO_LEVELDETECT1);
1985 #endif
1986 }
1987 }
1988
1989 }
1990
1991 #endif
1992
1993 /*
1994 * This may get called early from board specific init
1995 * for boards that have interrupts routed via FPGA.
1996 */
1997 int __init omap_gpio_init(void)
1998 {
1999 if (!initialized)
2000 return _omap_gpio_init();
2001 else
2002 return 0;
2003 }
2004
2005 static int __init omap_gpio_sysinit(void)
2006 {
2007 int ret = 0;
2008
2009 if (!initialized)
2010 ret = _omap_gpio_init();
2011
2012 mpuio_init();
2013
2014 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2015 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2016 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2017 if (ret == 0) {
2018 ret = sysdev_class_register(&omap_gpio_sysclass);
2019 if (ret == 0)
2020 ret = sysdev_register(&omap_gpio_device);
2021 }
2022 }
2023 #endif
2024
2025 return ret;
2026 }
2027
2028 arch_initcall(omap_gpio_sysinit);
2029
2030
2031 #ifdef CONFIG_DEBUG_FS
2032
2033 #include <linux/debugfs.h>
2034 #include <linux/seq_file.h>
2035
2036 static int gpio_is_input(struct gpio_bank *bank, int mask)
2037 {
2038 void __iomem *reg = bank->base;
2039
2040 switch (bank->method) {
2041 case METHOD_MPUIO:
2042 reg += OMAP_MPUIO_IO_CNTL;
2043 break;
2044 case METHOD_GPIO_1510:
2045 reg += OMAP1510_GPIO_DIR_CONTROL;
2046 break;
2047 case METHOD_GPIO_1610:
2048 reg += OMAP1610_GPIO_DIRECTION;
2049 break;
2050 case METHOD_GPIO_730:
2051 reg += OMAP730_GPIO_DIR_CONTROL;
2052 break;
2053 case METHOD_GPIO_850:
2054 reg += OMAP850_GPIO_DIR_CONTROL;
2055 break;
2056 case METHOD_GPIO_24XX:
2057 reg += OMAP24XX_GPIO_OE;
2058 break;
2059 }
2060 return __raw_readl(reg) & mask;
2061 }
2062
2063
2064 static int dbg_gpio_show(struct seq_file *s, void *unused)
2065 {
2066 unsigned i, j, gpio;
2067
2068 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2069 struct gpio_bank *bank = gpio_bank + i;
2070 unsigned bankwidth = 16;
2071 u32 mask = 1;
2072
2073 if (bank_is_mpuio(bank))
2074 gpio = OMAP_MPUIO(0);
2075 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
2076 cpu_is_omap850())
2077 bankwidth = 32;
2078
2079 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2080 unsigned irq, value, is_in, irqstat;
2081 const char *label;
2082
2083 label = gpiochip_is_requested(&bank->chip, j);
2084 if (!label)
2085 continue;
2086
2087 irq = bank->virtual_irq_start + j;
2088 value = gpio_get_value(gpio);
2089 is_in = gpio_is_input(bank, mask);
2090
2091 if (bank_is_mpuio(bank))
2092 seq_printf(s, "MPUIO %2d ", j);
2093 else
2094 seq_printf(s, "GPIO %3d ", gpio);
2095 seq_printf(s, "(%-20.20s): %s %s",
2096 label,
2097 is_in ? "in " : "out",
2098 value ? "hi" : "lo");
2099
2100 /* FIXME for at least omap2, show pullup/pulldown state */
2101
2102 irqstat = irq_desc[irq].status;
2103 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2104 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2105 if (is_in && ((bank->suspend_wakeup & mask)
2106 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2107 char *trigger = NULL;
2108
2109 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2110 case IRQ_TYPE_EDGE_FALLING:
2111 trigger = "falling";
2112 break;
2113 case IRQ_TYPE_EDGE_RISING:
2114 trigger = "rising";
2115 break;
2116 case IRQ_TYPE_EDGE_BOTH:
2117 trigger = "bothedge";
2118 break;
2119 case IRQ_TYPE_LEVEL_LOW:
2120 trigger = "low";
2121 break;
2122 case IRQ_TYPE_LEVEL_HIGH:
2123 trigger = "high";
2124 break;
2125 case IRQ_TYPE_NONE:
2126 trigger = "(?)";
2127 break;
2128 }
2129 seq_printf(s, ", irq-%d %-8s%s",
2130 irq, trigger,
2131 (bank->suspend_wakeup & mask)
2132 ? " wakeup" : "");
2133 }
2134 #endif
2135 seq_printf(s, "\n");
2136 }
2137
2138 if (bank_is_mpuio(bank)) {
2139 seq_printf(s, "\n");
2140 gpio = 0;
2141 }
2142 }
2143 return 0;
2144 }
2145
2146 static int dbg_gpio_open(struct inode *inode, struct file *file)
2147 {
2148 return single_open(file, dbg_gpio_show, &inode->i_private);
2149 }
2150
2151 static const struct file_operations debug_fops = {
2152 .open = dbg_gpio_open,
2153 .read = seq_read,
2154 .llseek = seq_lseek,
2155 .release = single_release,
2156 };
2157
2158 static int __init omap_gpio_debuginit(void)
2159 {
2160 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2161 NULL, NULL, &debug_fops);
2162 return 0;
2163 }
2164 late_initcall(omap_gpio_debuginit);
2165 #endif
Linux kernel - Deliverables
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