2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP7XX specific GPIO registers
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
89 * omap24xx specific GPIO registers
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
154 * omap34xx specific GPIO registers
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
165 * OMAP44XX specific GPIO registers
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
178 u16 virtual_irq_start
;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
184 #ifdef CONFIG_ARCH_OMAP2PLUS
185 u32 non_wakeup_gpios
;
186 u32 enabled_non_wakeup_gpios
;
189 u32 saved_fallingdetect
;
190 u32 saved_risingdetect
;
195 struct gpio_chip chip
;
200 #define METHOD_MPUIO 0
201 #define METHOD_GPIO_1510 1
202 #define METHOD_GPIO_1610 2
203 #define METHOD_GPIO_7XX 3
204 #define METHOD_GPIO_24XX 5
205 #define METHOD_GPIO_44XX 6
207 #ifdef CONFIG_ARCH_OMAP16XX
208 static struct gpio_bank gpio_bank_1610
[5] = {
209 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
211 { OMAP1610_GPIO1_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
213 { OMAP1610_GPIO2_BASE
, NULL
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16,
215 { OMAP1610_GPIO3_BASE
, NULL
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32,
217 { OMAP1610_GPIO4_BASE
, NULL
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48,
222 #ifdef CONFIG_ARCH_OMAP15XX
223 static struct gpio_bank gpio_bank_1510
[2] = {
224 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
226 { OMAP1510_GPIO_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
231 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
232 static struct gpio_bank gpio_bank_7xx
[7] = {
233 { OMAP1_MPUIO_VBASE
, NULL
, INT_7XX_MPUIO
, IH_MPUIO_BASE
,
235 { OMAP7XX_GPIO1_BASE
, NULL
, INT_7XX_GPIO_BANK1
, IH_GPIO_BASE
,
237 { OMAP7XX_GPIO2_BASE
, NULL
, INT_7XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
239 { OMAP7XX_GPIO3_BASE
, NULL
, INT_7XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
241 { OMAP7XX_GPIO4_BASE
, NULL
, INT_7XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
243 { OMAP7XX_GPIO5_BASE
, NULL
, INT_7XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
245 { OMAP7XX_GPIO6_BASE
, NULL
, INT_7XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
250 #ifdef CONFIG_ARCH_OMAP2
252 static struct gpio_bank gpio_bank_242x
[4] = {
253 { OMAP242X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
255 { OMAP242X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
257 { OMAP242X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
259 { OMAP242X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
263 static struct gpio_bank gpio_bank_243x
[5] = {
264 { OMAP243X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
266 { OMAP243X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
268 { OMAP243X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
270 { OMAP243X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
272 { OMAP243X_GPIO5_BASE
, NULL
, INT_24XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
278 #ifdef CONFIG_ARCH_OMAP3
279 static struct gpio_bank gpio_bank_34xx
[6] = {
280 { OMAP34XX_GPIO1_BASE
, NULL
, INT_34XX_GPIO_BANK1
, IH_GPIO_BASE
,
282 { OMAP34XX_GPIO2_BASE
, NULL
, INT_34XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
284 { OMAP34XX_GPIO3_BASE
, NULL
, INT_34XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
286 { OMAP34XX_GPIO4_BASE
, NULL
, INT_34XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
288 { OMAP34XX_GPIO5_BASE
, NULL
, INT_34XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
290 { OMAP34XX_GPIO6_BASE
, NULL
, INT_34XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
294 struct omap3_gpio_regs
{
310 static struct omap3_gpio_regs gpio_context
[OMAP34XX_NR_GPIOS
];
313 #ifdef CONFIG_ARCH_OMAP4
314 static struct gpio_bank gpio_bank_44xx
[6] = {
315 { OMAP44XX_GPIO1_BASE
, NULL
, OMAP44XX_IRQ_GPIO1
, IH_GPIO_BASE
,
317 { OMAP44XX_GPIO2_BASE
, NULL
, OMAP44XX_IRQ_GPIO2
, IH_GPIO_BASE
+ 32,
319 { OMAP44XX_GPIO3_BASE
, NULL
, OMAP44XX_IRQ_GPIO3
, IH_GPIO_BASE
+ 64,
321 { OMAP44XX_GPIO4_BASE
, NULL
, OMAP44XX_IRQ_GPIO4
, IH_GPIO_BASE
+ 96,
323 { OMAP44XX_GPIO5_BASE
, NULL
, OMAP44XX_IRQ_GPIO5
, IH_GPIO_BASE
+ 128,
325 { OMAP44XX_GPIO6_BASE
, NULL
, OMAP44XX_IRQ_GPIO6
, IH_GPIO_BASE
+ 160,
331 static struct gpio_bank
*gpio_bank
;
332 static int gpio_bank_count
;
334 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
336 if (cpu_is_omap15xx()) {
337 if (OMAP_GPIO_IS_MPUIO(gpio
))
338 return &gpio_bank
[0];
339 return &gpio_bank
[1];
341 if (cpu_is_omap16xx()) {
342 if (OMAP_GPIO_IS_MPUIO(gpio
))
343 return &gpio_bank
[0];
344 return &gpio_bank
[1 + (gpio
>> 4)];
346 if (cpu_is_omap7xx()) {
347 if (OMAP_GPIO_IS_MPUIO(gpio
))
348 return &gpio_bank
[0];
349 return &gpio_bank
[1 + (gpio
>> 5)];
351 if (cpu_is_omap24xx())
352 return &gpio_bank
[gpio
>> 5];
353 if (cpu_is_omap34xx() || cpu_is_omap44xx())
354 return &gpio_bank
[gpio
>> 5];
359 static inline int get_gpio_index(int gpio
)
361 if (cpu_is_omap7xx())
363 if (cpu_is_omap24xx())
365 if (cpu_is_omap34xx() || cpu_is_omap44xx())
370 static inline int gpio_valid(int gpio
)
374 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
375 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
379 if (cpu_is_omap15xx() && gpio
< 16)
381 if ((cpu_is_omap16xx()) && gpio
< 64)
383 if (cpu_is_omap7xx() && gpio
< 192)
385 if (cpu_is_omap24xx() && gpio
< 128)
387 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio
< 192)
392 static int check_gpio(int gpio
)
394 if (unlikely(gpio_valid(gpio
) < 0)) {
395 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
402 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
404 void __iomem
*reg
= bank
->base
;
407 switch (bank
->method
) {
408 #ifdef CONFIG_ARCH_OMAP1
410 reg
+= OMAP_MPUIO_IO_CNTL
;
413 #ifdef CONFIG_ARCH_OMAP15XX
414 case METHOD_GPIO_1510
:
415 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
418 #ifdef CONFIG_ARCH_OMAP16XX
419 case METHOD_GPIO_1610
:
420 reg
+= OMAP1610_GPIO_DIRECTION
;
423 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
424 case METHOD_GPIO_7XX
:
425 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
428 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
429 case METHOD_GPIO_24XX
:
430 reg
+= OMAP24XX_GPIO_OE
;
433 #if defined(CONFIG_ARCH_OMAP4)
434 case METHOD_GPIO_44XX
:
435 reg
+= OMAP4_GPIO_OE
;
442 l
= __raw_readl(reg
);
447 __raw_writel(l
, reg
);
450 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
452 void __iomem
*reg
= bank
->base
;
455 switch (bank
->method
) {
456 #ifdef CONFIG_ARCH_OMAP1
458 reg
+= OMAP_MPUIO_OUTPUT
;
459 l
= __raw_readl(reg
);
466 #ifdef CONFIG_ARCH_OMAP15XX
467 case METHOD_GPIO_1510
:
468 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
469 l
= __raw_readl(reg
);
476 #ifdef CONFIG_ARCH_OMAP16XX
477 case METHOD_GPIO_1610
:
479 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
481 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
485 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
486 case METHOD_GPIO_7XX
:
487 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
488 l
= __raw_readl(reg
);
495 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
496 case METHOD_GPIO_24XX
:
498 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
500 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
504 #ifdef CONFIG_ARCH_OMAP4
505 case METHOD_GPIO_44XX
:
507 reg
+= OMAP4_GPIO_SETDATAOUT
;
509 reg
+= OMAP4_GPIO_CLEARDATAOUT
;
517 __raw_writel(l
, reg
);
520 static int _get_gpio_datain(struct gpio_bank
*bank
, int gpio
)
524 if (check_gpio(gpio
) < 0)
527 switch (bank
->method
) {
528 #ifdef CONFIG_ARCH_OMAP1
530 reg
+= OMAP_MPUIO_INPUT_LATCH
;
533 #ifdef CONFIG_ARCH_OMAP15XX
534 case METHOD_GPIO_1510
:
535 reg
+= OMAP1510_GPIO_DATA_INPUT
;
538 #ifdef CONFIG_ARCH_OMAP16XX
539 case METHOD_GPIO_1610
:
540 reg
+= OMAP1610_GPIO_DATAIN
;
543 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
544 case METHOD_GPIO_7XX
:
545 reg
+= OMAP7XX_GPIO_DATA_INPUT
;
548 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
549 case METHOD_GPIO_24XX
:
550 reg
+= OMAP24XX_GPIO_DATAIN
;
553 #ifdef CONFIG_ARCH_OMAP4
554 case METHOD_GPIO_44XX
:
555 reg
+= OMAP4_GPIO_DATAIN
;
561 return (__raw_readl(reg
)
562 & (1 << get_gpio_index(gpio
))) != 0;
565 static int _get_gpio_dataout(struct gpio_bank
*bank
, int gpio
)
569 if (check_gpio(gpio
) < 0)
573 switch (bank
->method
) {
574 #ifdef CONFIG_ARCH_OMAP1
576 reg
+= OMAP_MPUIO_OUTPUT
;
579 #ifdef CONFIG_ARCH_OMAP15XX
580 case METHOD_GPIO_1510
:
581 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
584 #ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610
:
586 reg
+= OMAP1610_GPIO_DATAOUT
;
589 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
590 case METHOD_GPIO_7XX
:
591 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
594 #ifdef CONFIG_ARCH_OMAP2PLUS
595 case METHOD_GPIO_24XX
:
596 case METHOD_GPIO_44XX
:
597 reg
+= OMAP24XX_GPIO_DATAOUT
;
604 return (__raw_readl(reg
) & (1 << get_gpio_index(gpio
))) != 0;
607 #define MOD_REG_BIT(reg, bit_mask, set) \
609 int l = __raw_readl(base + reg); \
610 if (set) l |= bit_mask; \
611 else l &= ~bit_mask; \
612 __raw_writel(l, base + reg); \
615 void omap_set_gpio_debounce(int gpio
, int enable
)
617 struct gpio_bank
*bank
;
620 u32 val
, l
= 1 << get_gpio_index(gpio
);
622 if (cpu_class_is_omap1())
625 bank
= get_gpio_bank(gpio
);
628 if (cpu_is_omap44xx())
629 reg
+= OMAP4_GPIO_DEBOUNCENABLE
;
631 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
633 if (!(bank
->mod_usage
& l
)) {
634 printk(KERN_ERR
"GPIO %d not requested\n", gpio
);
638 spin_lock_irqsave(&bank
->lock
, flags
);
639 val
= __raw_readl(reg
);
641 if (enable
&& !(val
& l
))
643 else if (!enable
&& (val
& l
))
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
650 clk_enable(bank
->dbck
);
652 clk_disable(bank
->dbck
);
655 __raw_writel(val
, reg
);
657 spin_unlock_irqrestore(&bank
->lock
, flags
);
659 EXPORT_SYMBOL(omap_set_gpio_debounce
);
661 void omap_set_gpio_debounce_time(int gpio
, int enc_time
)
663 struct gpio_bank
*bank
;
666 if (cpu_class_is_omap1())
669 bank
= get_gpio_bank(gpio
);
672 if (!bank
->mod_usage
) {
673 printk(KERN_ERR
"GPIO not requested\n");
679 if (cpu_is_omap44xx())
680 reg
+= OMAP4_GPIO_DEBOUNCINGTIME
;
682 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
684 __raw_writel(enc_time
, reg
);
686 EXPORT_SYMBOL(omap_set_gpio_debounce_time
);
688 #ifdef CONFIG_ARCH_OMAP2PLUS
689 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
692 void __iomem
*base
= bank
->base
;
693 u32 gpio_bit
= 1 << gpio
;
696 if (cpu_is_omap44xx()) {
697 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0
, gpio_bit
,
698 trigger
& IRQ_TYPE_LEVEL_LOW
);
699 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1
, gpio_bit
,
700 trigger
& IRQ_TYPE_LEVEL_HIGH
);
701 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT
, gpio_bit
,
702 trigger
& IRQ_TYPE_EDGE_RISING
);
703 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT
, gpio_bit
,
704 trigger
& IRQ_TYPE_EDGE_FALLING
);
706 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
707 trigger
& IRQ_TYPE_LEVEL_LOW
);
708 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
709 trigger
& IRQ_TYPE_LEVEL_HIGH
);
710 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
711 trigger
& IRQ_TYPE_EDGE_RISING
);
712 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
713 trigger
& IRQ_TYPE_EDGE_FALLING
);
715 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
716 if (cpu_is_omap44xx()) {
718 __raw_writel(1 << gpio
, bank
->base
+
719 OMAP4_GPIO_IRQWAKEN0
);
721 val
= __raw_readl(bank
->base
+
722 OMAP4_GPIO_IRQWAKEN0
);
723 __raw_writel(val
& (~(1 << gpio
)), bank
->base
+
724 OMAP4_GPIO_IRQWAKEN0
);
728 __raw_writel(1 << gpio
, bank
->base
729 + OMAP24XX_GPIO_SETWKUENA
);
731 __raw_writel(1 << gpio
, bank
->base
732 + OMAP24XX_GPIO_CLEARWKUENA
);
736 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
738 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
741 if (cpu_is_omap44xx()) {
743 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT0
) |
744 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT1
);
747 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
748 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
753 #ifdef CONFIG_ARCH_OMAP1
755 * This only applies to chips that can't do both rising and falling edge
756 * detection at once. For all other chips, this function is a noop.
758 static void _toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
760 void __iomem
*reg
= bank
->base
;
763 switch (bank
->method
) {
765 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
767 #ifdef CONFIG_ARCH_OMAP15XX
768 case METHOD_GPIO_1510
:
769 reg
+= OMAP1510_GPIO_INT_CONTROL
;
772 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
773 case METHOD_GPIO_7XX
:
774 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
781 l
= __raw_readl(reg
);
787 __raw_writel(l
, reg
);
791 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
793 void __iomem
*reg
= bank
->base
;
796 switch (bank
->method
) {
797 #ifdef CONFIG_ARCH_OMAP1
799 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
800 l
= __raw_readl(reg
);
801 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
802 bank
->toggle_mask
|= 1 << gpio
;
803 if (trigger
& IRQ_TYPE_EDGE_RISING
)
805 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
811 #ifdef CONFIG_ARCH_OMAP15XX
812 case METHOD_GPIO_1510
:
813 reg
+= OMAP1510_GPIO_INT_CONTROL
;
814 l
= __raw_readl(reg
);
815 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
816 bank
->toggle_mask
|= 1 << gpio
;
817 if (trigger
& IRQ_TYPE_EDGE_RISING
)
819 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
825 #ifdef CONFIG_ARCH_OMAP16XX
826 case METHOD_GPIO_1610
:
828 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
830 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
832 l
= __raw_readl(reg
);
833 l
&= ~(3 << (gpio
<< 1));
834 if (trigger
& IRQ_TYPE_EDGE_RISING
)
835 l
|= 2 << (gpio
<< 1);
836 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
837 l
|= 1 << (gpio
<< 1);
839 /* Enable wake-up during idle for dynamic tick */
840 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
842 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
845 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
846 case METHOD_GPIO_7XX
:
847 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
848 l
= __raw_readl(reg
);
849 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
850 bank
->toggle_mask
|= 1 << gpio
;
851 if (trigger
& IRQ_TYPE_EDGE_RISING
)
853 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
859 #ifdef CONFIG_ARCH_OMAP2PLUS
860 case METHOD_GPIO_24XX
:
861 case METHOD_GPIO_44XX
:
862 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
868 __raw_writel(l
, reg
);
874 static int gpio_irq_type(unsigned irq
, unsigned type
)
876 struct gpio_bank
*bank
;
881 if (!cpu_class_is_omap2() && irq
> IH_MPUIO_BASE
)
882 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
884 gpio
= irq
- IH_GPIO_BASE
;
886 if (check_gpio(gpio
) < 0)
889 if (type
& ~IRQ_TYPE_SENSE_MASK
)
892 /* OMAP1 allows only only edge triggering */
893 if (!cpu_class_is_omap2()
894 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
897 bank
= get_irq_chip_data(irq
);
898 spin_lock_irqsave(&bank
->lock
, flags
);
899 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
901 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
902 irq_desc
[irq
].status
|= type
;
904 spin_unlock_irqrestore(&bank
->lock
, flags
);
906 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
907 __set_irq_handler_unlocked(irq
, handle_level_irq
);
908 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
909 __set_irq_handler_unlocked(irq
, handle_edge_irq
);
914 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
916 void __iomem
*reg
= bank
->base
;
918 switch (bank
->method
) {
919 #ifdef CONFIG_ARCH_OMAP1
921 /* MPUIO irqstatus is reset by reading the status register,
922 * so do nothing here */
925 #ifdef CONFIG_ARCH_OMAP15XX
926 case METHOD_GPIO_1510
:
927 reg
+= OMAP1510_GPIO_INT_STATUS
;
930 #ifdef CONFIG_ARCH_OMAP16XX
931 case METHOD_GPIO_1610
:
932 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
935 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
936 case METHOD_GPIO_7XX
:
937 reg
+= OMAP7XX_GPIO_INT_STATUS
;
940 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
941 case METHOD_GPIO_24XX
:
942 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
945 #if defined(CONFIG_ARCH_OMAP4)
946 case METHOD_GPIO_44XX
:
947 reg
+= OMAP4_GPIO_IRQSTATUS0
;
954 __raw_writel(gpio_mask
, reg
);
956 /* Workaround for clearing DSP GPIO interrupts to allow retention */
957 if (cpu_is_omap24xx() || cpu_is_omap34xx())
958 reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
;
959 else if (cpu_is_omap44xx())
960 reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS1
;
962 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
963 __raw_writel(gpio_mask
, reg
);
965 /* Flush posted write for the irq status to avoid spurious interrupts */
970 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
972 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
975 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
977 void __iomem
*reg
= bank
->base
;
982 switch (bank
->method
) {
983 #ifdef CONFIG_ARCH_OMAP1
985 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
990 #ifdef CONFIG_ARCH_OMAP15XX
991 case METHOD_GPIO_1510
:
992 reg
+= OMAP1510_GPIO_INT_MASK
;
997 #ifdef CONFIG_ARCH_OMAP16XX
998 case METHOD_GPIO_1610
:
999 reg
+= OMAP1610_GPIO_IRQENABLE1
;
1003 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1004 case METHOD_GPIO_7XX
:
1005 reg
+= OMAP7XX_GPIO_INT_MASK
;
1010 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1011 case METHOD_GPIO_24XX
:
1012 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
1016 #if defined(CONFIG_ARCH_OMAP4)
1017 case METHOD_GPIO_44XX
:
1018 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
1027 l
= __raw_readl(reg
);
1034 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
1036 void __iomem
*reg
= bank
->base
;
1039 switch (bank
->method
) {
1040 #ifdef CONFIG_ARCH_OMAP1
1042 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
1043 l
= __raw_readl(reg
);
1050 #ifdef CONFIG_ARCH_OMAP15XX
1051 case METHOD_GPIO_1510
:
1052 reg
+= OMAP1510_GPIO_INT_MASK
;
1053 l
= __raw_readl(reg
);
1060 #ifdef CONFIG_ARCH_OMAP16XX
1061 case METHOD_GPIO_1610
:
1063 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
1065 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
1069 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1070 case METHOD_GPIO_7XX
:
1071 reg
+= OMAP7XX_GPIO_INT_MASK
;
1072 l
= __raw_readl(reg
);
1079 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1080 case METHOD_GPIO_24XX
:
1082 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
1084 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
1088 #ifdef CONFIG_ARCH_OMAP4
1089 case METHOD_GPIO_44XX
:
1091 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
1093 reg
+= OMAP4_GPIO_IRQSTATUSCLR0
;
1101 __raw_writel(l
, reg
);
1104 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
1106 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
1110 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1111 * 1510 does not seem to have a wake-up register. If JTAG is connected
1112 * to the target, system will wake up always on GPIO events. While
1113 * system is running all registered GPIO interrupts need to have wake-up
1114 * enabled. When system is suspended, only selected GPIO interrupts need
1115 * to have wake-up enabled.
1117 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
1119 unsigned long uninitialized_var(flags
);
1121 switch (bank
->method
) {
1122 #ifdef CONFIG_ARCH_OMAP16XX
1124 case METHOD_GPIO_1610
:
1125 spin_lock_irqsave(&bank
->lock
, flags
);
1127 bank
->suspend_wakeup
|= (1 << gpio
);
1129 bank
->suspend_wakeup
&= ~(1 << gpio
);
1130 spin_unlock_irqrestore(&bank
->lock
, flags
);
1133 #ifdef CONFIG_ARCH_OMAP2PLUS
1134 case METHOD_GPIO_24XX
:
1135 case METHOD_GPIO_44XX
:
1136 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
1137 printk(KERN_ERR
"Unable to modify wakeup on "
1138 "non-wakeup GPIO%d\n",
1139 (bank
- gpio_bank
) * 32 + gpio
);
1142 spin_lock_irqsave(&bank
->lock
, flags
);
1144 bank
->suspend_wakeup
|= (1 << gpio
);
1146 bank
->suspend_wakeup
&= ~(1 << gpio
);
1147 spin_unlock_irqrestore(&bank
->lock
, flags
);
1151 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
1157 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
1159 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
1160 _set_gpio_irqenable(bank
, gpio
, 0);
1161 _clear_gpio_irqstatus(bank
, gpio
);
1162 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1165 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1166 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
1168 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1169 struct gpio_bank
*bank
;
1172 if (check_gpio(gpio
) < 0)
1174 bank
= get_irq_chip_data(irq
);
1175 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
1180 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1182 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1183 unsigned long flags
;
1185 spin_lock_irqsave(&bank
->lock
, flags
);
1187 /* Set trigger to none. You need to enable the desired trigger with
1188 * request_irq() or set_irq_type().
1190 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
1192 #ifdef CONFIG_ARCH_OMAP15XX
1193 if (bank
->method
== METHOD_GPIO_1510
) {
1196 /* Claim the pin for MPU */
1197 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
1198 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
1201 if (!cpu_class_is_omap1()) {
1202 if (!bank
->mod_usage
) {
1204 ctrl
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1206 /* Module is enabled, clocks are not gated */
1207 __raw_writel(ctrl
, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1209 bank
->mod_usage
|= 1 << offset
;
1211 spin_unlock_irqrestore(&bank
->lock
, flags
);
1216 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1218 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1219 unsigned long flags
;
1221 spin_lock_irqsave(&bank
->lock
, flags
);
1222 #ifdef CONFIG_ARCH_OMAP16XX
1223 if (bank
->method
== METHOD_GPIO_1610
) {
1224 /* Disable wake-up during idle for dynamic tick */
1225 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1226 __raw_writel(1 << offset
, reg
);
1229 #ifdef CONFIG_ARCH_OMAP2PLUS
1230 if ((bank
->method
== METHOD_GPIO_24XX
) ||
1231 (bank
->method
== METHOD_GPIO_44XX
)) {
1232 /* Disable wake-up during idle for dynamic tick */
1233 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1234 __raw_writel(1 << offset
, reg
);
1237 if (!cpu_class_is_omap1()) {
1238 bank
->mod_usage
&= ~(1 << offset
);
1239 if (!bank
->mod_usage
) {
1241 ctrl
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1242 /* Module is disabled, clocks are gated */
1244 __raw_writel(ctrl
, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1247 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
1248 spin_unlock_irqrestore(&bank
->lock
, flags
);
1252 * We need to unmask the GPIO bank interrupt as soon as possible to
1253 * avoid missing GPIO interrupts for other lines in the bank.
1254 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1255 * in the bank to avoid missing nested interrupts for a GPIO line.
1256 * If we wait to unmask individual GPIO lines in the bank after the
1257 * line's interrupt handler has been run, we may miss some nested
1260 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
1262 void __iomem
*isr_reg
= NULL
;
1264 unsigned int gpio_irq
, gpio_index
;
1265 struct gpio_bank
*bank
;
1269 desc
->chip
->ack(irq
);
1271 bank
= get_irq_data(irq
);
1272 #ifdef CONFIG_ARCH_OMAP1
1273 if (bank
->method
== METHOD_MPUIO
)
1274 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
1276 #ifdef CONFIG_ARCH_OMAP15XX
1277 if (bank
->method
== METHOD_GPIO_1510
)
1278 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1280 #if defined(CONFIG_ARCH_OMAP16XX)
1281 if (bank
->method
== METHOD_GPIO_1610
)
1282 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1284 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1285 if (bank
->method
== METHOD_GPIO_7XX
)
1286 isr_reg
= bank
->base
+ OMAP7XX_GPIO_INT_STATUS
;
1288 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1289 if (bank
->method
== METHOD_GPIO_24XX
)
1290 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1292 #if defined(CONFIG_ARCH_OMAP4)
1293 if (bank
->method
== METHOD_GPIO_44XX
)
1294 isr_reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS0
;
1297 u32 isr_saved
, level_mask
= 0;
1300 enabled
= _get_gpio_irqbank_mask(bank
);
1301 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1303 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1306 if (cpu_class_is_omap2()) {
1307 level_mask
= bank
->level_mask
& enabled
;
1310 /* clear edge sensitive interrupts before handler(s) are
1311 called so that we don't miss any interrupt occurred while
1313 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1314 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1315 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1317 /* if there is only edge sensitive GPIO pin interrupts
1318 configured, we could unmask GPIO bank interrupt immediately */
1319 if (!level_mask
&& !unmasked
) {
1321 desc
->chip
->unmask(irq
);
1329 gpio_irq
= bank
->virtual_irq_start
;
1330 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1331 gpio_index
= get_gpio_index(irq_to_gpio(gpio_irq
));
1336 #ifdef CONFIG_ARCH_OMAP1
1338 * Some chips can't respond to both rising and falling
1339 * at the same time. If this irq was requested with
1340 * both flags, we need to flip the ICR data for the IRQ
1341 * to respond to the IRQ for the opposite direction.
1342 * This will be indicated in the bank toggle_mask.
1344 if (bank
->toggle_mask
& (1 << gpio_index
))
1345 _toggle_gpio_edge_triggering(bank
, gpio_index
);
1348 generic_handle_irq(gpio_irq
);
1351 /* if bank has any level sensitive GPIO pin interrupt
1352 configured, we must unmask the bank interrupt only after
1353 handler(s) are executed in order to avoid spurious bank
1356 desc
->chip
->unmask(irq
);
1360 static void gpio_irq_shutdown(unsigned int irq
)
1362 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1363 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1365 _reset_gpio(bank
, gpio
);
1368 static void gpio_ack_irq(unsigned int irq
)
1370 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1371 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1373 _clear_gpio_irqstatus(bank
, gpio
);
1376 static void gpio_mask_irq(unsigned int irq
)
1378 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1379 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1381 _set_gpio_irqenable(bank
, gpio
, 0);
1382 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1385 static void gpio_unmask_irq(unsigned int irq
)
1387 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1388 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1389 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1390 struct irq_desc
*desc
= irq_to_desc(irq
);
1391 u32 trigger
= desc
->status
& IRQ_TYPE_SENSE_MASK
;
1394 _set_gpio_triggering(bank
, get_gpio_index(gpio
), trigger
);
1396 /* For level-triggered GPIOs, the clearing must be done after
1397 * the HW source is cleared, thus after the handler has run */
1398 if (bank
->level_mask
& irq_mask
) {
1399 _set_gpio_irqenable(bank
, gpio
, 0);
1400 _clear_gpio_irqstatus(bank
, gpio
);
1403 _set_gpio_irqenable(bank
, gpio
, 1);
1406 static struct irq_chip gpio_irq_chip
= {
1408 .shutdown
= gpio_irq_shutdown
,
1409 .ack
= gpio_ack_irq
,
1410 .mask
= gpio_mask_irq
,
1411 .unmask
= gpio_unmask_irq
,
1412 .set_type
= gpio_irq_type
,
1413 .set_wake
= gpio_wake_enable
,
1416 /*---------------------------------------------------------------------*/
1418 #ifdef CONFIG_ARCH_OMAP1
1420 /* MPUIO uses the always-on 32k clock */
1422 static void mpuio_ack_irq(unsigned int irq
)
1424 /* The ISR is reset automatically, so do nothing here. */
1427 static void mpuio_mask_irq(unsigned int irq
)
1429 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1430 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1432 _set_gpio_irqenable(bank
, gpio
, 0);
1435 static void mpuio_unmask_irq(unsigned int irq
)
1437 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1438 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1440 _set_gpio_irqenable(bank
, gpio
, 1);
1443 static struct irq_chip mpuio_irq_chip
= {
1445 .ack
= mpuio_ack_irq
,
1446 .mask
= mpuio_mask_irq
,
1447 .unmask
= mpuio_unmask_irq
,
1448 .set_type
= gpio_irq_type
,
1449 #ifdef CONFIG_ARCH_OMAP16XX
1450 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1451 .set_wake
= gpio_wake_enable
,
1456 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1459 #ifdef CONFIG_ARCH_OMAP16XX
1461 #include <linux/platform_device.h>
1463 static int omap_mpuio_suspend_noirq(struct device
*dev
)
1465 struct platform_device
*pdev
= to_platform_device(dev
);
1466 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1467 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1468 unsigned long flags
;
1470 spin_lock_irqsave(&bank
->lock
, flags
);
1471 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1472 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1473 spin_unlock_irqrestore(&bank
->lock
, flags
);
1478 static int omap_mpuio_resume_noirq(struct device
*dev
)
1480 struct platform_device
*pdev
= to_platform_device(dev
);
1481 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1482 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1483 unsigned long flags
;
1485 spin_lock_irqsave(&bank
->lock
, flags
);
1486 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1487 spin_unlock_irqrestore(&bank
->lock
, flags
);
1492 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
1493 .suspend_noirq
= omap_mpuio_suspend_noirq
,
1494 .resume_noirq
= omap_mpuio_resume_noirq
,
1497 /* use platform_driver for this, now that there's no longer any
1498 * point to sys_device (other than not disturbing old code).
1500 static struct platform_driver omap_mpuio_driver
= {
1503 .pm
= &omap_mpuio_dev_pm_ops
,
1507 static struct platform_device omap_mpuio_device
= {
1511 .driver
= &omap_mpuio_driver
.driver
,
1513 /* could list the /proc/iomem resources */
1516 static inline void mpuio_init(void)
1518 platform_set_drvdata(&omap_mpuio_device
, &gpio_bank_1610
[0]);
1520 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1521 (void) platform_device_register(&omap_mpuio_device
);
1525 static inline void mpuio_init(void) {}
1530 extern struct irq_chip mpuio_irq_chip
;
1532 #define bank_is_mpuio(bank) 0
1533 static inline void mpuio_init(void) {}
1537 /*---------------------------------------------------------------------*/
1539 /* REVISIT these are stupid implementations! replace by ones that
1540 * don't switch on METHOD_* and which mostly avoid spinlocks
1543 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1545 struct gpio_bank
*bank
;
1546 unsigned long flags
;
1548 bank
= container_of(chip
, struct gpio_bank
, chip
);
1549 spin_lock_irqsave(&bank
->lock
, flags
);
1550 _set_gpio_direction(bank
, offset
, 1);
1551 spin_unlock_irqrestore(&bank
->lock
, flags
);
1555 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1557 void __iomem
*reg
= bank
->base
;
1559 switch (bank
->method
) {
1561 reg
+= OMAP_MPUIO_IO_CNTL
;
1563 case METHOD_GPIO_1510
:
1564 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1566 case METHOD_GPIO_1610
:
1567 reg
+= OMAP1610_GPIO_DIRECTION
;
1569 case METHOD_GPIO_7XX
:
1570 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
1572 case METHOD_GPIO_24XX
:
1573 case METHOD_GPIO_44XX
:
1574 reg
+= OMAP24XX_GPIO_OE
;
1577 return __raw_readl(reg
) & mask
;
1580 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1582 struct gpio_bank
*bank
;
1587 gpio
= chip
->base
+ offset
;
1588 bank
= get_gpio_bank(gpio
);
1590 mask
= 1 << get_gpio_index(gpio
);
1592 if (gpio_is_input(bank
, mask
))
1593 return _get_gpio_datain(bank
, gpio
);
1595 return _get_gpio_dataout(bank
, gpio
);
1598 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1600 struct gpio_bank
*bank
;
1601 unsigned long flags
;
1603 bank
= container_of(chip
, struct gpio_bank
, chip
);
1604 spin_lock_irqsave(&bank
->lock
, flags
);
1605 _set_gpio_dataout(bank
, offset
, value
);
1606 _set_gpio_direction(bank
, offset
, 0);
1607 spin_unlock_irqrestore(&bank
->lock
, flags
);
1611 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1613 struct gpio_bank
*bank
;
1614 unsigned long flags
;
1616 bank
= container_of(chip
, struct gpio_bank
, chip
);
1617 spin_lock_irqsave(&bank
->lock
, flags
);
1618 _set_gpio_dataout(bank
, offset
, value
);
1619 spin_unlock_irqrestore(&bank
->lock
, flags
);
1622 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1624 struct gpio_bank
*bank
;
1626 bank
= container_of(chip
, struct gpio_bank
, chip
);
1627 return bank
->virtual_irq_start
+ offset
;
1630 /*---------------------------------------------------------------------*/
1632 static int initialized
;
1633 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1634 static struct clk
* gpio_ick
;
1637 #if defined(CONFIG_ARCH_OMAP2)
1638 static struct clk
* gpio_fck
;
1641 #if defined(CONFIG_ARCH_OMAP2430)
1642 static struct clk
* gpio5_ick
;
1643 static struct clk
* gpio5_fck
;
1646 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1647 static struct clk
*gpio_iclks
[OMAP34XX_NR_GPIOS
];
1650 static void __init
omap_gpio_show_rev(void)
1654 if (cpu_is_omap16xx())
1655 rev
= __raw_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1656 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1657 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1658 else if (cpu_is_omap44xx())
1659 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP4_GPIO_REVISION
);
1663 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1664 (rev
>> 4) & 0x0f, rev
& 0x0f);
1667 /* This lock class tells lockdep that GPIO irqs are in a different
1668 * category than their parents, so it won't report false recursion.
1670 static struct lock_class_key gpio_lock_class
;
1672 static int __init
_omap_gpio_init(void)
1676 struct gpio_bank
*bank
;
1677 int bank_size
= SZ_8K
; /* Module 4KB + L4 4KB except on omap1 */
1682 #if defined(CONFIG_ARCH_OMAP1)
1683 if (cpu_is_omap15xx()) {
1684 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
1685 if (IS_ERR(gpio_ick
))
1686 printk("Could not get arm_gpio_ck\n");
1688 clk_enable(gpio_ick
);
1691 #if defined(CONFIG_ARCH_OMAP2)
1692 if (cpu_class_is_omap2()) {
1693 gpio_ick
= clk_get(NULL
, "gpios_ick");
1694 if (IS_ERR(gpio_ick
))
1695 printk("Could not get gpios_ick\n");
1697 clk_enable(gpio_ick
);
1698 gpio_fck
= clk_get(NULL
, "gpios_fck");
1699 if (IS_ERR(gpio_fck
))
1700 printk("Could not get gpios_fck\n");
1702 clk_enable(gpio_fck
);
1705 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1707 #if defined(CONFIG_ARCH_OMAP2430)
1708 if (cpu_is_omap2430()) {
1709 gpio5_ick
= clk_get(NULL
, "gpio5_ick");
1710 if (IS_ERR(gpio5_ick
))
1711 printk("Could not get gpio5_ick\n");
1713 clk_enable(gpio5_ick
);
1714 gpio5_fck
= clk_get(NULL
, "gpio5_fck");
1715 if (IS_ERR(gpio5_fck
))
1716 printk("Could not get gpio5_fck\n");
1718 clk_enable(gpio5_fck
);
1724 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1725 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1726 for (i
= 0; i
< OMAP34XX_NR_GPIOS
; i
++) {
1727 sprintf(clk_name
, "gpio%d_ick", i
+ 1);
1728 gpio_iclks
[i
] = clk_get(NULL
, clk_name
);
1729 if (IS_ERR(gpio_iclks
[i
]))
1730 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1732 clk_enable(gpio_iclks
[i
]);
1738 #ifdef CONFIG_ARCH_OMAP15XX
1739 if (cpu_is_omap15xx()) {
1740 gpio_bank_count
= 2;
1741 gpio_bank
= gpio_bank_1510
;
1745 #if defined(CONFIG_ARCH_OMAP16XX)
1746 if (cpu_is_omap16xx()) {
1747 gpio_bank_count
= 5;
1748 gpio_bank
= gpio_bank_1610
;
1752 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1753 if (cpu_is_omap7xx()) {
1754 gpio_bank_count
= 7;
1755 gpio_bank
= gpio_bank_7xx
;
1759 #ifdef CONFIG_ARCH_OMAP2
1760 if (cpu_is_omap242x()) {
1761 gpio_bank_count
= 4;
1762 gpio_bank
= gpio_bank_242x
;
1764 if (cpu_is_omap243x()) {
1765 gpio_bank_count
= 5;
1766 gpio_bank
= gpio_bank_243x
;
1769 #ifdef CONFIG_ARCH_OMAP3
1770 if (cpu_is_omap34xx()) {
1771 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1772 gpio_bank
= gpio_bank_34xx
;
1775 #ifdef CONFIG_ARCH_OMAP4
1776 if (cpu_is_omap44xx()) {
1777 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1778 gpio_bank
= gpio_bank_44xx
;
1781 for (i
= 0; i
< gpio_bank_count
; i
++) {
1782 int j
, gpio_count
= 16;
1784 bank
= &gpio_bank
[i
];
1785 spin_lock_init(&bank
->lock
);
1787 /* Static mapping, never released */
1788 bank
->base
= ioremap(bank
->pbase
, bank_size
);
1790 printk(KERN_ERR
"Could not ioremap gpio bank%i\n", i
);
1794 if (bank_is_mpuio(bank
))
1795 __raw_writew(0xffff, bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
);
1796 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1797 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1798 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1800 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1801 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1802 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1803 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1805 if (cpu_is_omap7xx() && bank
->method
== METHOD_GPIO_7XX
) {
1806 __raw_writel(0xffffffff, bank
->base
+ OMAP7XX_GPIO_INT_MASK
);
1807 __raw_writel(0x00000000, bank
->base
+ OMAP7XX_GPIO_INT_STATUS
);
1809 gpio_count
= 32; /* 7xx has 32-bit GPIOs */
1812 #ifdef CONFIG_ARCH_OMAP2PLUS
1813 if ((bank
->method
== METHOD_GPIO_24XX
) ||
1814 (bank
->method
== METHOD_GPIO_44XX
)) {
1815 static const u32 non_wakeup_gpios
[] = {
1816 0xe203ffc0, 0x08700040
1819 if (cpu_is_omap44xx()) {
1820 __raw_writel(0xffffffff, bank
->base
+
1821 OMAP4_GPIO_IRQSTATUSCLR0
);
1822 __raw_writew(0x0015, bank
->base
+
1823 OMAP4_GPIO_SYSCONFIG
);
1824 __raw_writel(0x00000000, bank
->base
+
1825 OMAP4_GPIO_DEBOUNCENABLE
);
1827 * Initialize interface clock ungated,
1830 __raw_writel(0, bank
->base
+ OMAP4_GPIO_CTRL
);
1832 __raw_writel(0x00000000, bank
->base
+
1833 OMAP24XX_GPIO_IRQENABLE1
);
1834 __raw_writel(0xffffffff, bank
->base
+
1835 OMAP24XX_GPIO_IRQSTATUS1
);
1836 __raw_writew(0x0015, bank
->base
+
1837 OMAP24XX_GPIO_SYSCONFIG
);
1838 __raw_writel(0x00000000, bank
->base
+
1839 OMAP24XX_GPIO_DEBOUNCE_EN
);
1842 * Initialize interface clock ungated,
1845 __raw_writel(0, bank
->base
+
1846 OMAP24XX_GPIO_CTRL
);
1848 if (i
< ARRAY_SIZE(non_wakeup_gpios
))
1849 bank
->non_wakeup_gpios
= non_wakeup_gpios
[i
];
1854 bank
->mod_usage
= 0;
1855 /* REVISIT eventually switch from OMAP-specific gpio structs
1856 * over to the generic ones
1858 bank
->chip
.request
= omap_gpio_request
;
1859 bank
->chip
.free
= omap_gpio_free
;
1860 bank
->chip
.direction_input
= gpio_input
;
1861 bank
->chip
.get
= gpio_get
;
1862 bank
->chip
.direction_output
= gpio_output
;
1863 bank
->chip
.set
= gpio_set
;
1864 bank
->chip
.to_irq
= gpio_2irq
;
1865 if (bank_is_mpuio(bank
)) {
1866 bank
->chip
.label
= "mpuio";
1867 #ifdef CONFIG_ARCH_OMAP16XX
1868 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1870 bank
->chip
.base
= OMAP_MPUIO(0);
1872 bank
->chip
.label
= "gpio";
1873 bank
->chip
.base
= gpio
;
1876 bank
->chip
.ngpio
= gpio_count
;
1878 gpiochip_add(&bank
->chip
);
1880 for (j
= bank
->virtual_irq_start
;
1881 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1882 lockdep_set_class(&irq_desc
[j
].lock
, &gpio_lock_class
);
1883 set_irq_chip_data(j
, bank
);
1884 if (bank_is_mpuio(bank
))
1885 set_irq_chip(j
, &mpuio_irq_chip
);
1887 set_irq_chip(j
, &gpio_irq_chip
);
1888 set_irq_handler(j
, handle_simple_irq
);
1889 set_irq_flags(j
, IRQF_VALID
);
1891 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1892 set_irq_data(bank
->irq
, bank
);
1894 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1895 sprintf(clk_name
, "gpio%d_dbck", i
+ 1);
1896 bank
->dbck
= clk_get(NULL
, clk_name
);
1897 if (IS_ERR(bank
->dbck
))
1898 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1902 /* Enable system clock for GPIO module.
1903 * The CAM_CLK_CTRL *is* really the right place. */
1904 if (cpu_is_omap16xx())
1905 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1907 /* Enable autoidle for the OCP interface */
1908 if (cpu_is_omap24xx())
1909 omap_writel(1 << 0, 0x48019010);
1910 if (cpu_is_omap34xx())
1911 omap_writel(1 << 0, 0x48306814);
1913 omap_gpio_show_rev();
1918 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1919 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1923 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1926 for (i
= 0; i
< gpio_bank_count
; i
++) {
1927 struct gpio_bank
*bank
= &gpio_bank
[i
];
1928 void __iomem
*wake_status
;
1929 void __iomem
*wake_clear
;
1930 void __iomem
*wake_set
;
1931 unsigned long flags
;
1933 switch (bank
->method
) {
1934 #ifdef CONFIG_ARCH_OMAP16XX
1935 case METHOD_GPIO_1610
:
1936 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1937 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1938 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1941 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1942 case METHOD_GPIO_24XX
:
1943 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1944 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1945 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1948 #ifdef CONFIG_ARCH_OMAP4
1949 case METHOD_GPIO_44XX
:
1950 wake_status
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1951 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1952 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1959 spin_lock_irqsave(&bank
->lock
, flags
);
1960 bank
->saved_wakeup
= __raw_readl(wake_status
);
1961 __raw_writel(0xffffffff, wake_clear
);
1962 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1963 spin_unlock_irqrestore(&bank
->lock
, flags
);
1969 static int omap_gpio_resume(struct sys_device
*dev
)
1973 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1976 for (i
= 0; i
< gpio_bank_count
; i
++) {
1977 struct gpio_bank
*bank
= &gpio_bank
[i
];
1978 void __iomem
*wake_clear
;
1979 void __iomem
*wake_set
;
1980 unsigned long flags
;
1982 switch (bank
->method
) {
1983 #ifdef CONFIG_ARCH_OMAP16XX
1984 case METHOD_GPIO_1610
:
1985 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1986 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1989 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1990 case METHOD_GPIO_24XX
:
1991 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1992 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1995 #ifdef CONFIG_ARCH_OMAP4
1996 case METHOD_GPIO_44XX
:
1997 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1998 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
2005 spin_lock_irqsave(&bank
->lock
, flags
);
2006 __raw_writel(0xffffffff, wake_clear
);
2007 __raw_writel(bank
->saved_wakeup
, wake_set
);
2008 spin_unlock_irqrestore(&bank
->lock
, flags
);
2014 static struct sysdev_class omap_gpio_sysclass
= {
2016 .suspend
= omap_gpio_suspend
,
2017 .resume
= omap_gpio_resume
,
2020 static struct sys_device omap_gpio_device
= {
2022 .cls
= &omap_gpio_sysclass
,
2027 #ifdef CONFIG_ARCH_OMAP2PLUS
2029 static int workaround_enabled
;
2031 void omap2_gpio_prepare_for_retention(void)
2035 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
2036 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
2037 for (i
= 0; i
< gpio_bank_count
; i
++) {
2038 struct gpio_bank
*bank
= &gpio_bank
[i
];
2041 if (!(bank
->enabled_non_wakeup_gpios
))
2044 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2045 bank
->saved_datain
= __raw_readl(bank
->base
+
2046 OMAP24XX_GPIO_DATAIN
);
2047 l1
= __raw_readl(bank
->base
+
2048 OMAP24XX_GPIO_FALLINGDETECT
);
2049 l2
= __raw_readl(bank
->base
+
2050 OMAP24XX_GPIO_RISINGDETECT
);
2053 if (cpu_is_omap44xx()) {
2054 bank
->saved_datain
= __raw_readl(bank
->base
+
2056 l1
= __raw_readl(bank
->base
+
2057 OMAP4_GPIO_FALLINGDETECT
);
2058 l2
= __raw_readl(bank
->base
+
2059 OMAP4_GPIO_RISINGDETECT
);
2062 bank
->saved_fallingdetect
= l1
;
2063 bank
->saved_risingdetect
= l2
;
2064 l1
&= ~bank
->enabled_non_wakeup_gpios
;
2065 l2
&= ~bank
->enabled_non_wakeup_gpios
;
2067 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2068 __raw_writel(l1
, bank
->base
+
2069 OMAP24XX_GPIO_FALLINGDETECT
);
2070 __raw_writel(l2
, bank
->base
+
2071 OMAP24XX_GPIO_RISINGDETECT
);
2074 if (cpu_is_omap44xx()) {
2075 __raw_writel(l1
, bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
2076 __raw_writel(l2
, bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
2082 workaround_enabled
= 0;
2085 workaround_enabled
= 1;
2088 void omap2_gpio_resume_after_retention(void)
2092 if (!workaround_enabled
)
2094 for (i
= 0; i
< gpio_bank_count
; i
++) {
2095 struct gpio_bank
*bank
= &gpio_bank
[i
];
2096 u32 l
, gen
, gen0
, gen1
;
2098 if (!(bank
->enabled_non_wakeup_gpios
))
2101 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2102 __raw_writel(bank
->saved_fallingdetect
,
2103 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2104 __raw_writel(bank
->saved_risingdetect
,
2105 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2106 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
2109 if (cpu_is_omap44xx()) {
2110 __raw_writel(bank
->saved_fallingdetect
,
2111 bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
2112 __raw_writel(bank
->saved_risingdetect
,
2113 bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
2114 l
= __raw_readl(bank
->base
+ OMAP4_GPIO_DATAIN
);
2117 /* Check if any of the non-wakeup interrupt GPIOs have changed
2118 * state. If so, generate an IRQ by software. This is
2119 * horribly racy, but it's the best we can do to work around
2120 * this silicon bug. */
2121 l
^= bank
->saved_datain
;
2122 l
&= bank
->non_wakeup_gpios
;
2125 * No need to generate IRQs for the rising edge for gpio IRQs
2126 * configured with falling edge only; and vice versa.
2128 gen0
= l
& bank
->saved_fallingdetect
;
2129 gen0
&= bank
->saved_datain
;
2131 gen1
= l
& bank
->saved_risingdetect
;
2132 gen1
&= ~(bank
->saved_datain
);
2134 /* FIXME: Consider GPIO IRQs with level detections properly! */
2135 gen
= l
& (~(bank
->saved_fallingdetect
) &
2136 ~(bank
->saved_risingdetect
));
2137 /* Consider all GPIO IRQs needed to be updated */
2143 if (cpu_is_omap24xx() || cpu_is_omap44xx()) {
2144 old0
= __raw_readl(bank
->base
+
2145 OMAP24XX_GPIO_LEVELDETECT0
);
2146 old1
= __raw_readl(bank
->base
+
2147 OMAP24XX_GPIO_LEVELDETECT1
);
2148 __raw_writel(old0
| gen
, bank
->base
+
2149 OMAP24XX_GPIO_LEVELDETECT0
);
2150 __raw_writel(old1
| gen
, bank
->base
+
2151 OMAP24XX_GPIO_LEVELDETECT1
);
2152 __raw_writel(old0
, bank
->base
+
2153 OMAP24XX_GPIO_LEVELDETECT0
);
2154 __raw_writel(old1
, bank
->base
+
2155 OMAP24XX_GPIO_LEVELDETECT1
);
2158 if (cpu_is_omap44xx()) {
2159 old0
= __raw_readl(bank
->base
+
2160 OMAP4_GPIO_LEVELDETECT0
);
2161 old1
= __raw_readl(bank
->base
+
2162 OMAP4_GPIO_LEVELDETECT1
);
2163 __raw_writel(old0
| l
, bank
->base
+
2164 OMAP4_GPIO_LEVELDETECT0
);
2165 __raw_writel(old1
| l
, bank
->base
+
2166 OMAP4_GPIO_LEVELDETECT1
);
2167 __raw_writel(old0
, bank
->base
+
2168 OMAP4_GPIO_LEVELDETECT0
);
2169 __raw_writel(old1
, bank
->base
+
2170 OMAP4_GPIO_LEVELDETECT1
);
2179 #ifdef CONFIG_ARCH_OMAP3
2180 /* save the registers of bank 2-6 */
2181 void omap_gpio_save_context(void)
2185 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2186 for (i
= 1; i
< gpio_bank_count
; i
++) {
2187 struct gpio_bank
*bank
= &gpio_bank
[i
];
2188 gpio_context
[i
].sysconfig
=
2189 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2190 gpio_context
[i
].irqenable1
=
2191 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2192 gpio_context
[i
].irqenable2
=
2193 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2194 gpio_context
[i
].wake_en
=
2195 __raw_readl(bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2196 gpio_context
[i
].ctrl
=
2197 __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
2198 gpio_context
[i
].oe
=
2199 __raw_readl(bank
->base
+ OMAP24XX_GPIO_OE
);
2200 gpio_context
[i
].leveldetect0
=
2201 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2202 gpio_context
[i
].leveldetect1
=
2203 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2204 gpio_context
[i
].risingdetect
=
2205 __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2206 gpio_context
[i
].fallingdetect
=
2207 __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2208 gpio_context
[i
].dataout
=
2209 __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2210 gpio_context
[i
].setwkuena
=
2211 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2212 gpio_context
[i
].setdataout
=
2213 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2217 /* restore the required registers of bank 2-6 */
2218 void omap_gpio_restore_context(void)
2222 for (i
= 1; i
< gpio_bank_count
; i
++) {
2223 struct gpio_bank
*bank
= &gpio_bank
[i
];
2224 __raw_writel(gpio_context
[i
].sysconfig
,
2225 bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2226 __raw_writel(gpio_context
[i
].irqenable1
,
2227 bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2228 __raw_writel(gpio_context
[i
].irqenable2
,
2229 bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2230 __raw_writel(gpio_context
[i
].wake_en
,
2231 bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2232 __raw_writel(gpio_context
[i
].ctrl
,
2233 bank
->base
+ OMAP24XX_GPIO_CTRL
);
2234 __raw_writel(gpio_context
[i
].oe
,
2235 bank
->base
+ OMAP24XX_GPIO_OE
);
2236 __raw_writel(gpio_context
[i
].leveldetect0
,
2237 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2238 __raw_writel(gpio_context
[i
].leveldetect1
,
2239 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2240 __raw_writel(gpio_context
[i
].risingdetect
,
2241 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2242 __raw_writel(gpio_context
[i
].fallingdetect
,
2243 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2244 __raw_writel(gpio_context
[i
].dataout
,
2245 bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2246 __raw_writel(gpio_context
[i
].setwkuena
,
2247 bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2248 __raw_writel(gpio_context
[i
].setdataout
,
2249 bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2255 * This may get called early from board specific init
2256 * for boards that have interrupts routed via FPGA.
2258 int __init
omap_gpio_init(void)
2261 return _omap_gpio_init();
2266 static int __init
omap_gpio_sysinit(void)
2271 ret
= _omap_gpio_init();
2275 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2276 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2278 ret
= sysdev_class_register(&omap_gpio_sysclass
);
2280 ret
= sysdev_register(&omap_gpio_device
);
2288 arch_initcall(omap_gpio_sysinit
);
2291 #ifdef CONFIG_DEBUG_FS
2293 #include <linux/debugfs.h>
2294 #include <linux/seq_file.h>
2296 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
2298 unsigned i
, j
, gpio
;
2300 for (i
= 0, gpio
= 0; i
< gpio_bank_count
; i
++) {
2301 struct gpio_bank
*bank
= gpio_bank
+ i
;
2302 unsigned bankwidth
= 16;
2305 if (bank_is_mpuio(bank
))
2306 gpio
= OMAP_MPUIO(0);
2307 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2310 for (j
= 0; j
< bankwidth
; j
++, gpio
++, mask
<<= 1) {
2311 unsigned irq
, value
, is_in
, irqstat
;
2314 label
= gpiochip_is_requested(&bank
->chip
, j
);
2318 irq
= bank
->virtual_irq_start
+ j
;
2319 value
= gpio_get_value(gpio
);
2320 is_in
= gpio_is_input(bank
, mask
);
2322 if (bank_is_mpuio(bank
))
2323 seq_printf(s
, "MPUIO %2d ", j
);
2325 seq_printf(s
, "GPIO %3d ", gpio
);
2326 seq_printf(s
, "(%-20.20s): %s %s",
2328 is_in
? "in " : "out",
2329 value
? "hi" : "lo");
2331 /* FIXME for at least omap2, show pullup/pulldown state */
2333 irqstat
= irq_desc
[irq
].status
;
2334 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2335 if (is_in
&& ((bank
->suspend_wakeup
& mask
)
2336 || irqstat
& IRQ_TYPE_SENSE_MASK
)) {
2337 char *trigger
= NULL
;
2339 switch (irqstat
& IRQ_TYPE_SENSE_MASK
) {
2340 case IRQ_TYPE_EDGE_FALLING
:
2341 trigger
= "falling";
2343 case IRQ_TYPE_EDGE_RISING
:
2346 case IRQ_TYPE_EDGE_BOTH
:
2347 trigger
= "bothedge";
2349 case IRQ_TYPE_LEVEL_LOW
:
2352 case IRQ_TYPE_LEVEL_HIGH
:
2359 seq_printf(s
, ", irq-%d %-8s%s",
2361 (bank
->suspend_wakeup
& mask
)
2365 seq_printf(s
, "\n");
2368 if (bank_is_mpuio(bank
)) {
2369 seq_printf(s
, "\n");
2376 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
2378 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
2381 static const struct file_operations debug_fops
= {
2382 .open
= dbg_gpio_open
,
2384 .llseek
= seq_lseek
,
2385 .release
= single_release
,
2388 static int __init
omap_gpio_debuginit(void)
2390 (void) debugfs_create_file("omap_gpio", S_IRUGO
,
2391 NULL
, NULL
, &debug_fops
);
2394 late_initcall(omap_gpio_debuginit
);