2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
137 u16 virtual_irq_start
;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios
;
145 u32 enabled_non_wakeup_gpios
;
148 u32 saved_fallingdetect
;
149 u32 saved_risingdetect
;
152 struct gpio_chip chip
;
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610
[5] = {
163 { OMAP_MPUIO_BASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
164 { OMAP1610_GPIO1_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1610
},
165 { OMAP1610_GPIO2_BASE
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16, METHOD_GPIO_1610
},
166 { OMAP1610_GPIO3_BASE
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32, METHOD_GPIO_1610
},
167 { OMAP1610_GPIO4_BASE
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48, METHOD_GPIO_1610
},
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510
[2] = {
173 { OMAP_MPUIO_BASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
174 { OMAP1510_GPIO_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1510
}
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730
[7] = {
180 { OMAP_MPUIO_BASE
, INT_730_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
181 { OMAP730_GPIO1_BASE
, INT_730_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_730
},
182 { OMAP730_GPIO2_BASE
, INT_730_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_730
},
183 { OMAP730_GPIO3_BASE
, INT_730_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_730
},
184 { OMAP730_GPIO4_BASE
, INT_730_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_730
},
185 { OMAP730_GPIO5_BASE
, INT_730_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_730
},
186 { OMAP730_GPIO6_BASE
, INT_730_GPIO_BANK6
, IH_GPIO_BASE
+ 160, METHOD_GPIO_730
},
190 #ifdef CONFIG_ARCH_OMAP24XX
192 static struct gpio_bank gpio_bank_242x
[4] = {
193 { OMAP242X_GPIO1_BASE
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
194 { OMAP242X_GPIO2_BASE
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
195 { OMAP242X_GPIO3_BASE
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
196 { OMAP242X_GPIO4_BASE
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
199 static struct gpio_bank gpio_bank_243x
[5] = {
200 { OMAP243X_GPIO1_BASE
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
201 { OMAP243X_GPIO2_BASE
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
202 { OMAP243X_GPIO3_BASE
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
203 { OMAP243X_GPIO4_BASE
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
204 { OMAP243X_GPIO5_BASE
, INT_24XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_24XX
},
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx
[6] = {
211 { OMAP34XX_GPIO1_BASE
, INT_34XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
212 { OMAP34XX_GPIO2_BASE
, INT_34XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
213 { OMAP34XX_GPIO3_BASE
, INT_34XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
214 { OMAP34XX_GPIO4_BASE
, INT_34XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
215 { OMAP34XX_GPIO5_BASE
, INT_34XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_24XX
},
216 { OMAP34XX_GPIO6_BASE
, INT_34XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160, METHOD_GPIO_24XX
},
221 static struct gpio_bank
*gpio_bank
;
222 static int gpio_bank_count
;
224 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio
))
228 return &gpio_bank
[0];
229 return &gpio_bank
[1];
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio
))
233 return &gpio_bank
[0];
234 return &gpio_bank
[1 + (gpio
>> 4)];
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio
))
238 return &gpio_bank
[0];
239 return &gpio_bank
[1 + (gpio
>> 5)];
241 if (cpu_is_omap24xx())
242 return &gpio_bank
[gpio
>> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank
[gpio
>> 5];
247 static inline int get_gpio_index(int gpio
)
249 if (cpu_is_omap730())
251 if (cpu_is_omap24xx())
253 if (cpu_is_omap34xx())
258 static inline int gpio_valid(int gpio
)
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
263 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
267 if (cpu_is_omap15xx() && gpio
< 16)
269 if ((cpu_is_omap16xx()) && gpio
< 64)
271 if (cpu_is_omap730() && gpio
< 192)
273 if (cpu_is_omap24xx() && gpio
< 128)
275 if (cpu_is_omap34xx() && gpio
< 160)
280 static int check_gpio(int gpio
)
282 if (unlikely(gpio_valid(gpio
)) < 0) {
283 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
290 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
292 void __iomem
*reg
= bank
->base
;
295 switch (bank
->method
) {
296 #ifdef CONFIG_ARCH_OMAP1
298 reg
+= OMAP_MPUIO_IO_CNTL
;
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510
:
303 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610
:
308 reg
+= OMAP1610_GPIO_DIRECTION
;
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730
:
313 reg
+= OMAP730_GPIO_DIR_CONTROL
;
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX
:
318 reg
+= OMAP24XX_GPIO_OE
;
325 l
= __raw_readl(reg
);
330 __raw_writel(l
, reg
);
333 void omap_set_gpio_direction(int gpio
, int is_input
)
335 struct gpio_bank
*bank
;
338 if (check_gpio(gpio
) < 0)
340 bank
= get_gpio_bank(gpio
);
341 spin_lock_irqsave(&bank
->lock
, flags
);
342 _set_gpio_direction(bank
, get_gpio_index(gpio
), is_input
);
343 spin_unlock_irqrestore(&bank
->lock
, flags
);
346 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
348 void __iomem
*reg
= bank
->base
;
351 switch (bank
->method
) {
352 #ifdef CONFIG_ARCH_OMAP1
354 reg
+= OMAP_MPUIO_OUTPUT
;
355 l
= __raw_readl(reg
);
362 #ifdef CONFIG_ARCH_OMAP15XX
363 case METHOD_GPIO_1510
:
364 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
365 l
= __raw_readl(reg
);
372 #ifdef CONFIG_ARCH_OMAP16XX
373 case METHOD_GPIO_1610
:
375 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
377 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
381 #ifdef CONFIG_ARCH_OMAP730
382 case METHOD_GPIO_730
:
383 reg
+= OMAP730_GPIO_DATA_OUTPUT
;
384 l
= __raw_readl(reg
);
391 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
392 case METHOD_GPIO_24XX
:
394 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
396 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
404 __raw_writel(l
, reg
);
407 void omap_set_gpio_dataout(int gpio
, int enable
)
409 struct gpio_bank
*bank
;
412 if (check_gpio(gpio
) < 0)
414 bank
= get_gpio_bank(gpio
);
415 spin_lock_irqsave(&bank
->lock
, flags
);
416 _set_gpio_dataout(bank
, get_gpio_index(gpio
), enable
);
417 spin_unlock_irqrestore(&bank
->lock
, flags
);
420 int omap_get_gpio_datain(int gpio
)
422 struct gpio_bank
*bank
;
425 if (check_gpio(gpio
) < 0)
427 bank
= get_gpio_bank(gpio
);
429 switch (bank
->method
) {
430 #ifdef CONFIG_ARCH_OMAP1
432 reg
+= OMAP_MPUIO_INPUT_LATCH
;
435 #ifdef CONFIG_ARCH_OMAP15XX
436 case METHOD_GPIO_1510
:
437 reg
+= OMAP1510_GPIO_DATA_INPUT
;
440 #ifdef CONFIG_ARCH_OMAP16XX
441 case METHOD_GPIO_1610
:
442 reg
+= OMAP1610_GPIO_DATAIN
;
445 #ifdef CONFIG_ARCH_OMAP730
446 case METHOD_GPIO_730
:
447 reg
+= OMAP730_GPIO_DATA_INPUT
;
450 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
451 case METHOD_GPIO_24XX
:
452 reg
+= OMAP24XX_GPIO_DATAIN
;
458 return (__raw_readl(reg
)
459 & (1 << get_gpio_index(gpio
))) != 0;
462 #define MOD_REG_BIT(reg, bit_mask, set) \
464 int l = __raw_readl(base + reg); \
465 if (set) l |= bit_mask; \
466 else l &= ~bit_mask; \
467 __raw_writel(l, base + reg); \
470 void omap_set_gpio_debounce(int gpio
, int enable
)
472 struct gpio_bank
*bank
;
474 u32 val
, l
= 1 << get_gpio_index(gpio
);
476 if (cpu_class_is_omap1())
479 bank
= get_gpio_bank(gpio
);
482 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
483 val
= __raw_readl(reg
);
490 __raw_writel(val
, reg
);
492 EXPORT_SYMBOL(omap_set_gpio_debounce
);
494 void omap_set_gpio_debounce_time(int gpio
, int enc_time
)
496 struct gpio_bank
*bank
;
499 if (cpu_class_is_omap1())
502 bank
= get_gpio_bank(gpio
);
506 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
507 __raw_writel(enc_time
, reg
);
509 EXPORT_SYMBOL(omap_set_gpio_debounce_time
);
511 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
512 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
515 void __iomem
*base
= bank
->base
;
516 u32 gpio_bit
= 1 << gpio
;
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
519 trigger
& __IRQT_LOWLVL
);
520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
521 trigger
& __IRQT_HIGHLVL
);
522 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
523 trigger
& __IRQT_RISEDGE
);
524 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
525 trigger
& __IRQT_FALEDGE
);
527 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
529 __raw_writel(1 << gpio
, bank
->base
530 + OMAP24XX_GPIO_SETWKUENA
);
532 __raw_writel(1 << gpio
, bank
->base
533 + OMAP24XX_GPIO_CLEARWKUENA
);
536 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
538 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
542 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
543 * level triggering requested.
548 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
550 void __iomem
*reg
= bank
->base
;
553 switch (bank
->method
) {
554 #ifdef CONFIG_ARCH_OMAP1
556 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
557 l
= __raw_readl(reg
);
558 if (trigger
& __IRQT_RISEDGE
)
560 else if (trigger
& __IRQT_FALEDGE
)
566 #ifdef CONFIG_ARCH_OMAP15XX
567 case METHOD_GPIO_1510
:
568 reg
+= OMAP1510_GPIO_INT_CONTROL
;
569 l
= __raw_readl(reg
);
570 if (trigger
& __IRQT_RISEDGE
)
572 else if (trigger
& __IRQT_FALEDGE
)
578 #ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610
:
581 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
583 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
585 l
= __raw_readl(reg
);
586 l
&= ~(3 << (gpio
<< 1));
587 if (trigger
& __IRQT_RISEDGE
)
588 l
|= 2 << (gpio
<< 1);
589 if (trigger
& __IRQT_FALEDGE
)
590 l
|= 1 << (gpio
<< 1);
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
595 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
598 #ifdef CONFIG_ARCH_OMAP730
599 case METHOD_GPIO_730
:
600 reg
+= OMAP730_GPIO_INT_CONTROL
;
601 l
= __raw_readl(reg
);
602 if (trigger
& __IRQT_RISEDGE
)
604 else if (trigger
& __IRQT_FALEDGE
)
610 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
611 case METHOD_GPIO_24XX
:
612 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
618 __raw_writel(l
, reg
);
624 static int gpio_irq_type(unsigned irq
, unsigned type
)
626 struct gpio_bank
*bank
;
631 if (!cpu_class_is_omap2() && irq
> IH_MPUIO_BASE
)
632 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
634 gpio
= irq
- IH_GPIO_BASE
;
636 if (check_gpio(gpio
) < 0)
639 if (type
& ~IRQ_TYPE_SENSE_MASK
)
642 /* OMAP1 allows only only edge triggering */
643 if (!cpu_class_is_omap2()
644 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
647 bank
= get_irq_chip_data(irq
);
648 spin_lock_irqsave(&bank
->lock
, flags
);
649 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
651 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
652 irq_desc
[irq
].status
|= type
;
654 spin_unlock_irqrestore(&bank
->lock
, flags
);
658 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
660 void __iomem
*reg
= bank
->base
;
662 switch (bank
->method
) {
663 #ifdef CONFIG_ARCH_OMAP1
665 /* MPUIO irqstatus is reset by reading the status register,
666 * so do nothing here */
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510
:
671 reg
+= OMAP1510_GPIO_INT_STATUS
;
674 #ifdef CONFIG_ARCH_OMAP16XX
675 case METHOD_GPIO_1610
:
676 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
679 #ifdef CONFIG_ARCH_OMAP730
680 case METHOD_GPIO_730
:
681 reg
+= OMAP730_GPIO_INT_STATUS
;
684 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
685 case METHOD_GPIO_24XX
:
686 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
693 __raw_writel(gpio_mask
, reg
);
695 /* Workaround for clearing DSP GPIO interrupts to allow retention */
696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 if (cpu_is_omap24xx() || cpu_is_omap34xx())
698 __raw_writel(gpio_mask
, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
);
702 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
704 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
707 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
709 void __iomem
*reg
= bank
->base
;
714 switch (bank
->method
) {
715 #ifdef CONFIG_ARCH_OMAP1
717 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
722 #ifdef CONFIG_ARCH_OMAP15XX
723 case METHOD_GPIO_1510
:
724 reg
+= OMAP1510_GPIO_INT_MASK
;
729 #ifdef CONFIG_ARCH_OMAP16XX
730 case METHOD_GPIO_1610
:
731 reg
+= OMAP1610_GPIO_IRQENABLE1
;
735 #ifdef CONFIG_ARCH_OMAP730
736 case METHOD_GPIO_730
:
737 reg
+= OMAP730_GPIO_INT_MASK
;
742 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
743 case METHOD_GPIO_24XX
:
744 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
753 l
= __raw_readl(reg
);
760 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
762 void __iomem
*reg
= bank
->base
;
765 switch (bank
->method
) {
766 #ifdef CONFIG_ARCH_OMAP1
768 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
769 l
= __raw_readl(reg
);
776 #ifdef CONFIG_ARCH_OMAP15XX
777 case METHOD_GPIO_1510
:
778 reg
+= OMAP1510_GPIO_INT_MASK
;
779 l
= __raw_readl(reg
);
786 #ifdef CONFIG_ARCH_OMAP16XX
787 case METHOD_GPIO_1610
:
789 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
791 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
795 #ifdef CONFIG_ARCH_OMAP730
796 case METHOD_GPIO_730
:
797 reg
+= OMAP730_GPIO_INT_MASK
;
798 l
= __raw_readl(reg
);
805 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
806 case METHOD_GPIO_24XX
:
808 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
810 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
818 __raw_writel(l
, reg
);
821 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
823 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
827 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
828 * 1510 does not seem to have a wake-up register. If JTAG is connected
829 * to the target, system will wake up always on GPIO events. While
830 * system is running all registered GPIO interrupts need to have wake-up
831 * enabled. When system is suspended, only selected GPIO interrupts need
832 * to have wake-up enabled.
834 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
838 switch (bank
->method
) {
839 #ifdef CONFIG_ARCH_OMAP16XX
841 case METHOD_GPIO_1610
:
842 spin_lock_irqsave(&bank
->lock
, flags
);
844 bank
->suspend_wakeup
|= (1 << gpio
);
845 enable_irq_wake(bank
->irq
);
847 disable_irq_wake(bank
->irq
);
848 bank
->suspend_wakeup
&= ~(1 << gpio
);
850 spin_unlock_irqrestore(&bank
->lock
, flags
);
853 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
854 case METHOD_GPIO_24XX
:
855 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
856 printk(KERN_ERR
"Unable to modify wakeup on "
857 "non-wakeup GPIO%d\n",
858 (bank
- gpio_bank
) * 32 + gpio
);
861 spin_lock_irqsave(&bank
->lock
, flags
);
863 bank
->suspend_wakeup
|= (1 << gpio
);
864 enable_irq_wake(bank
->irq
);
866 disable_irq_wake(bank
->irq
);
867 bank
->suspend_wakeup
&= ~(1 << gpio
);
869 spin_unlock_irqrestore(&bank
->lock
, flags
);
873 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
879 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
881 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
882 _set_gpio_irqenable(bank
, gpio
, 0);
883 _clear_gpio_irqstatus(bank
, gpio
);
884 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQT_NOEDGE
);
887 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
888 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
890 unsigned int gpio
= irq
- IH_GPIO_BASE
;
891 struct gpio_bank
*bank
;
894 if (check_gpio(gpio
) < 0)
896 bank
= get_irq_chip_data(irq
);
897 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
902 int omap_request_gpio(int gpio
)
904 struct gpio_bank
*bank
;
908 if (check_gpio(gpio
) < 0)
911 status
= gpio_request(gpio
, NULL
);
915 bank
= get_gpio_bank(gpio
);
916 spin_lock_irqsave(&bank
->lock
, flags
);
918 /* Set trigger to none. You need to enable the desired trigger with
919 * request_irq() or set_irq_type().
921 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQT_NOEDGE
);
923 #ifdef CONFIG_ARCH_OMAP15XX
924 if (bank
->method
== METHOD_GPIO_1510
) {
927 /* Claim the pin for MPU */
928 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
929 __raw_writel(__raw_readl(reg
) | (1 << get_gpio_index(gpio
)), reg
);
932 spin_unlock_irqrestore(&bank
->lock
, flags
);
937 void omap_free_gpio(int gpio
)
939 struct gpio_bank
*bank
;
942 if (check_gpio(gpio
) < 0)
944 bank
= get_gpio_bank(gpio
);
945 spin_lock_irqsave(&bank
->lock
, flags
);
946 if (unlikely(!gpiochip_is_requested(&bank
->chip
,
947 get_gpio_index(gpio
)))) {
948 spin_unlock_irqrestore(&bank
->lock
, flags
);
949 printk(KERN_ERR
"omap-gpio: GPIO %d wasn't reserved!\n", gpio
);
953 #ifdef CONFIG_ARCH_OMAP16XX
954 if (bank
->method
== METHOD_GPIO_1610
) {
955 /* Disable wake-up during idle for dynamic tick */
956 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
957 __raw_writel(1 << get_gpio_index(gpio
), reg
);
960 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
961 if (bank
->method
== METHOD_GPIO_24XX
) {
962 /* Disable wake-up during idle for dynamic tick */
963 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
964 __raw_writel(1 << get_gpio_index(gpio
), reg
);
967 _reset_gpio(bank
, gpio
);
968 spin_unlock_irqrestore(&bank
->lock
, flags
);
973 * We need to unmask the GPIO bank interrupt as soon as possible to
974 * avoid missing GPIO interrupts for other lines in the bank.
975 * Then we need to mask-read-clear-unmask the triggered GPIO lines
976 * in the bank to avoid missing nested interrupts for a GPIO line.
977 * If we wait to unmask individual GPIO lines in the bank after the
978 * line's interrupt handler has been run, we may miss some nested
981 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
983 void __iomem
*isr_reg
= NULL
;
985 unsigned int gpio_irq
;
986 struct gpio_bank
*bank
;
990 desc
->chip
->ack(irq
);
992 bank
= get_irq_data(irq
);
993 #ifdef CONFIG_ARCH_OMAP1
994 if (bank
->method
== METHOD_MPUIO
)
995 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
997 #ifdef CONFIG_ARCH_OMAP15XX
998 if (bank
->method
== METHOD_GPIO_1510
)
999 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1001 #if defined(CONFIG_ARCH_OMAP16XX)
1002 if (bank
->method
== METHOD_GPIO_1610
)
1003 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1005 #ifdef CONFIG_ARCH_OMAP730
1006 if (bank
->method
== METHOD_GPIO_730
)
1007 isr_reg
= bank
->base
+ OMAP730_GPIO_INT_STATUS
;
1009 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1010 if (bank
->method
== METHOD_GPIO_24XX
)
1011 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1014 u32 isr_saved
, level_mask
= 0;
1017 enabled
= _get_gpio_irqbank_mask(bank
);
1018 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1020 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1023 if (cpu_class_is_omap2()) {
1025 __raw_readl(bank
->base
+
1026 OMAP24XX_GPIO_LEVELDETECT0
) |
1027 __raw_readl(bank
->base
+
1028 OMAP24XX_GPIO_LEVELDETECT1
);
1029 level_mask
&= enabled
;
1032 /* clear edge sensitive interrupts before handler(s) are
1033 called so that we don't miss any interrupt occurred while
1035 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1036 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1037 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1039 /* if there is only edge sensitive GPIO pin interrupts
1040 configured, we could unmask GPIO bank interrupt immediately */
1041 if (!level_mask
&& !unmasked
) {
1043 desc
->chip
->unmask(irq
);
1051 gpio_irq
= bank
->virtual_irq_start
;
1052 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1057 d
= irq_desc
+ gpio_irq
;
1058 /* Don't run the handler if it's already running
1059 * or was disabled lazely.
1061 if (unlikely((d
->depth
||
1062 (d
->status
& IRQ_INPROGRESS
)))) {
1064 (gpio_irq
- bank
->virtual_irq_start
);
1065 /* The unmasking will be done by
1066 * enable_irq in case it is disabled or
1067 * after returning from the handler if
1068 * it's already running.
1070 _enable_gpio_irqbank(bank
, irq_mask
, 0);
1072 /* Level triggered interrupts
1073 * won't ever be reentered
1075 BUG_ON(level_mask
& irq_mask
);
1076 d
->status
|= IRQ_PENDING
;
1081 desc_handle_irq(gpio_irq
, d
);
1083 if (unlikely((d
->status
& IRQ_PENDING
) && !d
->depth
)) {
1085 (gpio_irq
- bank
->virtual_irq_start
);
1086 d
->status
&= ~IRQ_PENDING
;
1087 _enable_gpio_irqbank(bank
, irq_mask
, 1);
1088 retrigger
|= irq_mask
;
1092 if (cpu_class_is_omap2()) {
1093 /* clear level sensitive interrupts after handler(s) */
1094 _enable_gpio_irqbank(bank
, isr_saved
& level_mask
, 0);
1095 _clear_gpio_irqbank(bank
, isr_saved
& level_mask
);
1096 _enable_gpio_irqbank(bank
, isr_saved
& level_mask
, 1);
1100 /* if bank has any level sensitive GPIO pin interrupt
1101 configured, we must unmask the bank interrupt only after
1102 handler(s) are executed in order to avoid spurious bank
1105 desc
->chip
->unmask(irq
);
1109 static void gpio_irq_shutdown(unsigned int irq
)
1111 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1112 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1114 _reset_gpio(bank
, gpio
);
1117 static void gpio_ack_irq(unsigned int irq
)
1119 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1120 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1122 _clear_gpio_irqstatus(bank
, gpio
);
1125 static void gpio_mask_irq(unsigned int irq
)
1127 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1128 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1130 _set_gpio_irqenable(bank
, gpio
, 0);
1133 static void gpio_unmask_irq(unsigned int irq
)
1135 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1136 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1138 _set_gpio_irqenable(bank
, gpio
, 1);
1141 static struct irq_chip gpio_irq_chip
= {
1143 .shutdown
= gpio_irq_shutdown
,
1144 .ack
= gpio_ack_irq
,
1145 .mask
= gpio_mask_irq
,
1146 .unmask
= gpio_unmask_irq
,
1147 .set_type
= gpio_irq_type
,
1148 .set_wake
= gpio_wake_enable
,
1151 /*---------------------------------------------------------------------*/
1153 #ifdef CONFIG_ARCH_OMAP1
1155 /* MPUIO uses the always-on 32k clock */
1157 static void mpuio_ack_irq(unsigned int irq
)
1159 /* The ISR is reset automatically, so do nothing here. */
1162 static void mpuio_mask_irq(unsigned int irq
)
1164 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1165 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1167 _set_gpio_irqenable(bank
, gpio
, 0);
1170 static void mpuio_unmask_irq(unsigned int irq
)
1172 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1173 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1175 _set_gpio_irqenable(bank
, gpio
, 1);
1178 static struct irq_chip mpuio_irq_chip
= {
1180 .ack
= mpuio_ack_irq
,
1181 .mask
= mpuio_mask_irq
,
1182 .unmask
= mpuio_unmask_irq
,
1183 .set_type
= gpio_irq_type
,
1184 #ifdef CONFIG_ARCH_OMAP16XX
1185 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1186 .set_wake
= gpio_wake_enable
,
1191 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1194 #ifdef CONFIG_ARCH_OMAP16XX
1196 #include <linux/platform_device.h>
1198 static int omap_mpuio_suspend_late(struct platform_device
*pdev
, pm_message_t mesg
)
1200 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1201 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1202 unsigned long flags
;
1204 spin_lock_irqsave(&bank
->lock
, flags
);
1205 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1206 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1207 spin_unlock_irqrestore(&bank
->lock
, flags
);
1212 static int omap_mpuio_resume_early(struct platform_device
*pdev
)
1214 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1215 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1216 unsigned long flags
;
1218 spin_lock_irqsave(&bank
->lock
, flags
);
1219 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1220 spin_unlock_irqrestore(&bank
->lock
, flags
);
1225 /* use platform_driver for this, now that there's no longer any
1226 * point to sys_device (other than not disturbing old code).
1228 static struct platform_driver omap_mpuio_driver
= {
1229 .suspend_late
= omap_mpuio_suspend_late
,
1230 .resume_early
= omap_mpuio_resume_early
,
1236 static struct platform_device omap_mpuio_device
= {
1240 .driver
= &omap_mpuio_driver
.driver
,
1242 /* could list the /proc/iomem resources */
1245 static inline void mpuio_init(void)
1247 platform_set_drvdata(&omap_mpuio_device
, &gpio_bank_1610
[0]);
1249 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1250 (void) platform_device_register(&omap_mpuio_device
);
1254 static inline void mpuio_init(void) {}
1259 extern struct irq_chip mpuio_irq_chip
;
1261 #define bank_is_mpuio(bank) 0
1262 static inline void mpuio_init(void) {}
1266 /*---------------------------------------------------------------------*/
1268 /* REVISIT these are stupid implementations! replace by ones that
1269 * don't switch on METHOD_* and which mostly avoid spinlocks
1272 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1274 struct gpio_bank
*bank
;
1275 unsigned long flags
;
1277 bank
= container_of(chip
, struct gpio_bank
, chip
);
1278 spin_lock_irqsave(&bank
->lock
, flags
);
1279 _set_gpio_direction(bank
, offset
, 1);
1280 spin_unlock_irqrestore(&bank
->lock
, flags
);
1284 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1286 return omap_get_gpio_datain(chip
->base
+ offset
);
1289 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1291 struct gpio_bank
*bank
;
1292 unsigned long flags
;
1294 bank
= container_of(chip
, struct gpio_bank
, chip
);
1295 spin_lock_irqsave(&bank
->lock
, flags
);
1296 _set_gpio_dataout(bank
, offset
, value
);
1297 _set_gpio_direction(bank
, offset
, 0);
1298 spin_unlock_irqrestore(&bank
->lock
, flags
);
1302 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1304 struct gpio_bank
*bank
;
1305 unsigned long flags
;
1307 bank
= container_of(chip
, struct gpio_bank
, chip
);
1308 spin_lock_irqsave(&bank
->lock
, flags
);
1309 _set_gpio_dataout(bank
, offset
, value
);
1310 spin_unlock_irqrestore(&bank
->lock
, flags
);
1313 /*---------------------------------------------------------------------*/
1315 static int initialized
;
1316 #if !defined(CONFIG_ARCH_OMAP3)
1317 static struct clk
* gpio_ick
;
1320 #if defined(CONFIG_ARCH_OMAP2)
1321 static struct clk
* gpio_fck
;
1324 #if defined(CONFIG_ARCH_OMAP2430)
1325 static struct clk
* gpio5_ick
;
1326 static struct clk
* gpio5_fck
;
1329 #if defined(CONFIG_ARCH_OMAP3)
1330 static struct clk
*gpio_fclks
[OMAP34XX_NR_GPIOS
];
1331 static struct clk
*gpio_iclks
[OMAP34XX_NR_GPIOS
];
1334 /* This lock class tells lockdep that GPIO irqs are in a different
1335 * category than their parents, so it won't report false recursion.
1337 static struct lock_class_key gpio_lock_class
;
1339 static int __init
_omap_gpio_init(void)
1343 struct gpio_bank
*bank
;
1344 #if defined(CONFIG_ARCH_OMAP3)
1350 #if defined(CONFIG_ARCH_OMAP1)
1351 if (cpu_is_omap15xx()) {
1352 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
1353 if (IS_ERR(gpio_ick
))
1354 printk("Could not get arm_gpio_ck\n");
1356 clk_enable(gpio_ick
);
1359 #if defined(CONFIG_ARCH_OMAP2)
1360 if (cpu_class_is_omap2()) {
1361 gpio_ick
= clk_get(NULL
, "gpios_ick");
1362 if (IS_ERR(gpio_ick
))
1363 printk("Could not get gpios_ick\n");
1365 clk_enable(gpio_ick
);
1366 gpio_fck
= clk_get(NULL
, "gpios_fck");
1367 if (IS_ERR(gpio_fck
))
1368 printk("Could not get gpios_fck\n");
1370 clk_enable(gpio_fck
);
1373 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1375 #if defined(CONFIG_ARCH_OMAP2430)
1376 if (cpu_is_omap2430()) {
1377 gpio5_ick
= clk_get(NULL
, "gpio5_ick");
1378 if (IS_ERR(gpio5_ick
))
1379 printk("Could not get gpio5_ick\n");
1381 clk_enable(gpio5_ick
);
1382 gpio5_fck
= clk_get(NULL
, "gpio5_fck");
1383 if (IS_ERR(gpio5_fck
))
1384 printk("Could not get gpio5_fck\n");
1386 clk_enable(gpio5_fck
);
1392 #if defined(CONFIG_ARCH_OMAP3)
1393 if (cpu_is_omap34xx()) {
1394 for (i
= 0; i
< OMAP34XX_NR_GPIOS
; i
++) {
1395 sprintf(clk_name
, "gpio%d_ick", i
+ 1);
1396 gpio_iclks
[i
] = clk_get(NULL
, clk_name
);
1397 if (IS_ERR(gpio_iclks
[i
]))
1398 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1400 clk_enable(gpio_iclks
[i
]);
1401 sprintf(clk_name
, "gpio%d_fck", i
+ 1);
1402 gpio_fclks
[i
] = clk_get(NULL
, clk_name
);
1403 if (IS_ERR(gpio_fclks
[i
]))
1404 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1406 clk_enable(gpio_fclks
[i
]);
1412 #ifdef CONFIG_ARCH_OMAP15XX
1413 if (cpu_is_omap15xx()) {
1414 printk(KERN_INFO
"OMAP1510 GPIO hardware\n");
1415 gpio_bank_count
= 2;
1416 gpio_bank
= gpio_bank_1510
;
1419 #if defined(CONFIG_ARCH_OMAP16XX)
1420 if (cpu_is_omap16xx()) {
1423 gpio_bank_count
= 5;
1424 gpio_bank
= gpio_bank_1610
;
1425 rev
= omap_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1426 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1427 (rev
>> 4) & 0x0f, rev
& 0x0f);
1430 #ifdef CONFIG_ARCH_OMAP730
1431 if (cpu_is_omap730()) {
1432 printk(KERN_INFO
"OMAP730 GPIO hardware\n");
1433 gpio_bank_count
= 7;
1434 gpio_bank
= gpio_bank_730
;
1438 #ifdef CONFIG_ARCH_OMAP24XX
1439 if (cpu_is_omap242x()) {
1442 gpio_bank_count
= 4;
1443 gpio_bank
= gpio_bank_242x
;
1444 rev
= omap_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1445 printk(KERN_INFO
"OMAP242x GPIO hardware version %d.%d\n",
1446 (rev
>> 4) & 0x0f, rev
& 0x0f);
1448 if (cpu_is_omap243x()) {
1451 gpio_bank_count
= 5;
1452 gpio_bank
= gpio_bank_243x
;
1453 rev
= omap_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1454 printk(KERN_INFO
"OMAP243x GPIO hardware version %d.%d\n",
1455 (rev
>> 4) & 0x0f, rev
& 0x0f);
1458 #ifdef CONFIG_ARCH_OMAP34XX
1459 if (cpu_is_omap34xx()) {
1462 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1463 gpio_bank
= gpio_bank_34xx
;
1464 rev
= omap_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1465 printk(KERN_INFO
"OMAP34xx GPIO hardware version %d.%d\n",
1466 (rev
>> 4) & 0x0f, rev
& 0x0f);
1469 for (i
= 0; i
< gpio_bank_count
; i
++) {
1470 int j
, gpio_count
= 16;
1472 bank
= &gpio_bank
[i
];
1473 bank
->base
= IO_ADDRESS(bank
->base
);
1474 spin_lock_init(&bank
->lock
);
1475 if (bank_is_mpuio(bank
))
1476 omap_writew(0xFFFF, OMAP_MPUIO_BASE
+ OMAP_MPUIO_GPIO_MASKIT
);
1477 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1478 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1479 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1481 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1482 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1483 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1484 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1486 if (cpu_is_omap730() && bank
->method
== METHOD_GPIO_730
) {
1487 __raw_writel(0xffffffff, bank
->base
+ OMAP730_GPIO_INT_MASK
);
1488 __raw_writel(0x00000000, bank
->base
+ OMAP730_GPIO_INT_STATUS
);
1490 gpio_count
= 32; /* 730 has 32-bit GPIOs */
1493 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1494 if (bank
->method
== METHOD_GPIO_24XX
) {
1495 static const u32 non_wakeup_gpios
[] = {
1496 0xe203ffc0, 0x08700040
1499 __raw_writel(0x00000000, bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1500 __raw_writel(0xffffffff, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
);
1501 __raw_writew(0x0015, bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
1503 /* Initialize interface clock ungated, module enabled */
1504 __raw_writel(0, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1505 if (i
< ARRAY_SIZE(non_wakeup_gpios
))
1506 bank
->non_wakeup_gpios
= non_wakeup_gpios
[i
];
1511 /* REVISIT eventually switch from OMAP-specific gpio structs
1512 * over to the generic ones
1514 bank
->chip
.direction_input
= gpio_input
;
1515 bank
->chip
.get
= gpio_get
;
1516 bank
->chip
.direction_output
= gpio_output
;
1517 bank
->chip
.set
= gpio_set
;
1518 if (bank_is_mpuio(bank
)) {
1519 bank
->chip
.label
= "mpuio";
1520 bank
->chip
.base
= OMAP_MPUIO(0);
1522 bank
->chip
.label
= "gpio";
1523 bank
->chip
.base
= gpio
;
1526 bank
->chip
.ngpio
= gpio_count
;
1528 gpiochip_add(&bank
->chip
);
1530 for (j
= bank
->virtual_irq_start
;
1531 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1532 lockdep_set_class(&irq_desc
[j
].lock
, &gpio_lock_class
);
1533 set_irq_chip_data(j
, bank
);
1534 if (bank_is_mpuio(bank
))
1535 set_irq_chip(j
, &mpuio_irq_chip
);
1537 set_irq_chip(j
, &gpio_irq_chip
);
1538 set_irq_handler(j
, handle_simple_irq
);
1539 set_irq_flags(j
, IRQF_VALID
);
1541 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1542 set_irq_data(bank
->irq
, bank
);
1545 /* Enable system clock for GPIO module.
1546 * The CAM_CLK_CTRL *is* really the right place. */
1547 if (cpu_is_omap16xx())
1548 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1550 /* Enable autoidle for the OCP interface */
1551 if (cpu_is_omap24xx())
1552 omap_writel(1 << 0, 0x48019010);
1553 if (cpu_is_omap34xx())
1554 omap_writel(1 << 0, 0x48306814);
1559 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1560 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1564 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1567 for (i
= 0; i
< gpio_bank_count
; i
++) {
1568 struct gpio_bank
*bank
= &gpio_bank
[i
];
1569 void __iomem
*wake_status
;
1570 void __iomem
*wake_clear
;
1571 void __iomem
*wake_set
;
1572 unsigned long flags
;
1574 switch (bank
->method
) {
1575 #ifdef CONFIG_ARCH_OMAP16XX
1576 case METHOD_GPIO_1610
:
1577 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1578 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1579 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1582 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1583 case METHOD_GPIO_24XX
:
1584 wake_status
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1585 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1586 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1593 spin_lock_irqsave(&bank
->lock
, flags
);
1594 bank
->saved_wakeup
= __raw_readl(wake_status
);
1595 __raw_writel(0xffffffff, wake_clear
);
1596 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1597 spin_unlock_irqrestore(&bank
->lock
, flags
);
1603 static int omap_gpio_resume(struct sys_device
*dev
)
1607 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1610 for (i
= 0; i
< gpio_bank_count
; i
++) {
1611 struct gpio_bank
*bank
= &gpio_bank
[i
];
1612 void __iomem
*wake_clear
;
1613 void __iomem
*wake_set
;
1614 unsigned long flags
;
1616 switch (bank
->method
) {
1617 #ifdef CONFIG_ARCH_OMAP16XX
1618 case METHOD_GPIO_1610
:
1619 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1620 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1623 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1624 case METHOD_GPIO_24XX
:
1625 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1626 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1633 spin_lock_irqsave(&bank
->lock
, flags
);
1634 __raw_writel(0xffffffff, wake_clear
);
1635 __raw_writel(bank
->saved_wakeup
, wake_set
);
1636 spin_unlock_irqrestore(&bank
->lock
, flags
);
1642 static struct sysdev_class omap_gpio_sysclass
= {
1644 .suspend
= omap_gpio_suspend
,
1645 .resume
= omap_gpio_resume
,
1648 static struct sys_device omap_gpio_device
= {
1650 .cls
= &omap_gpio_sysclass
,
1655 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1657 static int workaround_enabled
;
1659 void omap2_gpio_prepare_for_retention(void)
1663 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1664 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1665 for (i
= 0; i
< gpio_bank_count
; i
++) {
1666 struct gpio_bank
*bank
= &gpio_bank
[i
];
1669 if (!(bank
->enabled_non_wakeup_gpios
))
1671 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1672 bank
->saved_datain
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1673 l1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1674 l2
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1676 bank
->saved_fallingdetect
= l1
;
1677 bank
->saved_risingdetect
= l2
;
1678 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1679 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1680 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1681 __raw_writel(l1
, bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1682 __raw_writel(l2
, bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1687 workaround_enabled
= 0;
1690 workaround_enabled
= 1;
1693 void omap2_gpio_resume_after_retention(void)
1697 if (!workaround_enabled
)
1699 for (i
= 0; i
< gpio_bank_count
; i
++) {
1700 struct gpio_bank
*bank
= &gpio_bank
[i
];
1703 if (!(bank
->enabled_non_wakeup_gpios
))
1705 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1706 __raw_writel(bank
->saved_fallingdetect
,
1707 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1708 __raw_writel(bank
->saved_risingdetect
,
1709 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1711 /* Check if any of the non-wakeup interrupt GPIOs have changed
1712 * state. If so, generate an IRQ by software. This is
1713 * horribly racy, but it's the best we can do to work around
1714 * this silicon bug. */
1715 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1716 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1718 l
^= bank
->saved_datain
;
1719 l
&= bank
->non_wakeup_gpios
;
1722 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1723 old0
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1724 old1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1725 __raw_writel(old0
| l
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1726 __raw_writel(old1
| l
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1727 __raw_writel(old0
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1728 __raw_writel(old1
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1738 * This may get called early from board specific init
1739 * for boards that have interrupts routed via FPGA.
1741 int __init
omap_gpio_init(void)
1744 return _omap_gpio_init();
1749 static int __init
omap_gpio_sysinit(void)
1754 ret
= _omap_gpio_init();
1758 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1759 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1761 ret
= sysdev_class_register(&omap_gpio_sysclass
);
1763 ret
= sysdev_register(&omap_gpio_device
);
1771 EXPORT_SYMBOL(omap_request_gpio
);
1772 EXPORT_SYMBOL(omap_free_gpio
);
1773 EXPORT_SYMBOL(omap_set_gpio_direction
);
1774 EXPORT_SYMBOL(omap_set_gpio_dataout
);
1775 EXPORT_SYMBOL(omap_get_gpio_datain
);
1777 arch_initcall(omap_gpio_sysinit
);
1780 #ifdef CONFIG_DEBUG_FS
1782 #include <linux/debugfs.h>
1783 #include <linux/seq_file.h>
1785 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1787 void __iomem
*reg
= bank
->base
;
1789 switch (bank
->method
) {
1791 reg
+= OMAP_MPUIO_IO_CNTL
;
1793 case METHOD_GPIO_1510
:
1794 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1796 case METHOD_GPIO_1610
:
1797 reg
+= OMAP1610_GPIO_DIRECTION
;
1799 case METHOD_GPIO_730
:
1800 reg
+= OMAP730_GPIO_DIR_CONTROL
;
1802 case METHOD_GPIO_24XX
:
1803 reg
+= OMAP24XX_GPIO_OE
;
1806 return __raw_readl(reg
) & mask
;
1810 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
1812 unsigned i
, j
, gpio
;
1814 for (i
= 0, gpio
= 0; i
< gpio_bank_count
; i
++) {
1815 struct gpio_bank
*bank
= gpio_bank
+ i
;
1816 unsigned bankwidth
= 16;
1819 if (bank_is_mpuio(bank
))
1820 gpio
= OMAP_MPUIO(0);
1821 else if (cpu_class_is_omap2() || cpu_is_omap730())
1824 for (j
= 0; j
< bankwidth
; j
++, gpio
++, mask
<<= 1) {
1825 unsigned irq
, value
, is_in
, irqstat
;
1828 label
= gpiochip_is_requested(&bank
->chip
, j
);
1832 irq
= bank
->virtual_irq_start
+ j
;
1833 value
= omap_get_gpio_datain(gpio
);
1834 is_in
= gpio_is_input(bank
, mask
);
1836 if (bank_is_mpuio(bank
))
1837 seq_printf(s
, "MPUIO %2d ", j
);
1839 seq_printf(s
, "GPIO %3d ", gpio
);
1840 seq_printf(s
, "(%10s): %s %s",
1842 is_in
? "in " : "out",
1843 value
? "hi" : "lo");
1845 /* FIXME for at least omap2, show pullup/pulldown state */
1847 irqstat
= irq_desc
[irq
].status
;
1848 if (is_in
&& ((bank
->suspend_wakeup
& mask
)
1849 || irqstat
& IRQ_TYPE_SENSE_MASK
)) {
1850 char *trigger
= NULL
;
1852 switch (irqstat
& IRQ_TYPE_SENSE_MASK
) {
1853 case IRQ_TYPE_EDGE_FALLING
:
1854 trigger
= "falling";
1856 case IRQ_TYPE_EDGE_RISING
:
1859 case IRQ_TYPE_EDGE_BOTH
:
1860 trigger
= "bothedge";
1862 case IRQ_TYPE_LEVEL_LOW
:
1865 case IRQ_TYPE_LEVEL_HIGH
:
1872 seq_printf(s
, ", irq-%d %-8s%s",
1874 (bank
->suspend_wakeup
& mask
)
1877 seq_printf(s
, "\n");
1880 if (bank_is_mpuio(bank
)) {
1881 seq_printf(s
, "\n");
1888 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
1890 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
1893 static const struct file_operations debug_fops
= {
1894 .open
= dbg_gpio_open
,
1896 .llseek
= seq_lseek
,
1897 .release
= single_release
,
1900 static int __init
omap_gpio_debuginit(void)
1902 (void) debugfs_create_file("omap_gpio", S_IRUGO
,
1903 NULL
, NULL
, &debug_fops
);
1906 late_initcall(omap_gpio_debuginit
);