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Merge trivial low-risk suspend hotkey bugzilla-5918 into release
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22
23 #include <asm/hardware.h>
24 #include <asm/irq.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
28
29 #include <asm/io.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP730 specific GPIO registers
72 */
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
85
86 /*
87 * omap24xx specific GPIO registers
88 */
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
98 #define OMAP24XX_GPIO_CTRL 0x0030
99 #define OMAP24XX_GPIO_OE 0x0034
100 #define OMAP24XX_GPIO_DATAIN 0x0038
101 #define OMAP24XX_GPIO_DATAOUT 0x003c
102 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
103 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
104 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
105 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
106 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
107 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
108 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
109 #define OMAP24XX_GPIO_SETWKUENA 0x0084
110 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
111 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
112
113 #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
114
115 struct gpio_bank {
116 void __iomem *base;
117 u16 irq;
118 u16 virtual_irq_start;
119 int method;
120 u32 reserved_map;
121 u32 suspend_wakeup;
122 u32 saved_wakeup;
123 spinlock_t lock;
124 };
125
126 #define METHOD_MPUIO 0
127 #define METHOD_GPIO_1510 1
128 #define METHOD_GPIO_1610 2
129 #define METHOD_GPIO_730 3
130 #define METHOD_GPIO_24XX 4
131
132 #ifdef CONFIG_ARCH_OMAP16XX
133 static struct gpio_bank gpio_bank_1610[5] = {
134 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
135 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
136 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
138 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
139 };
140 #endif
141
142 #ifdef CONFIG_ARCH_OMAP15XX
143 static struct gpio_bank gpio_bank_1510[2] = {
144 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
145 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
146 };
147 #endif
148
149 #ifdef CONFIG_ARCH_OMAP730
150 static struct gpio_bank gpio_bank_730[7] = {
151 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
152 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
153 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
154 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
155 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
156 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
157 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
158 };
159 #endif
160
161 #ifdef CONFIG_ARCH_OMAP24XX
162 static struct gpio_bank gpio_bank_24xx[4] = {
163 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
166 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
167 };
168 #endif
169
170 static struct gpio_bank *gpio_bank;
171 static int gpio_bank_count;
172
173 static inline struct gpio_bank *get_gpio_bank(int gpio)
174 {
175 #ifdef CONFIG_ARCH_OMAP15XX
176 if (cpu_is_omap15xx()) {
177 if (OMAP_GPIO_IS_MPUIO(gpio))
178 return &gpio_bank[0];
179 return &gpio_bank[1];
180 }
181 #endif
182 #if defined(CONFIG_ARCH_OMAP16XX)
183 if (cpu_is_omap16xx()) {
184 if (OMAP_GPIO_IS_MPUIO(gpio))
185 return &gpio_bank[0];
186 return &gpio_bank[1 + (gpio >> 4)];
187 }
188 #endif
189 #ifdef CONFIG_ARCH_OMAP730
190 if (cpu_is_omap730()) {
191 if (OMAP_GPIO_IS_MPUIO(gpio))
192 return &gpio_bank[0];
193 return &gpio_bank[1 + (gpio >> 5)];
194 }
195 #endif
196 #ifdef CONFIG_ARCH_OMAP24XX
197 if (cpu_is_omap24xx())
198 return &gpio_bank[gpio >> 5];
199 #endif
200 }
201
202 static inline int get_gpio_index(int gpio)
203 {
204 #ifdef CONFIG_ARCH_OMAP730
205 if (cpu_is_omap730())
206 return gpio & 0x1f;
207 #endif
208 #ifdef CONFIG_ARCH_OMAP24XX
209 if (cpu_is_omap24xx())
210 return gpio & 0x1f;
211 #endif
212 return gpio & 0x0f;
213 }
214
215 static inline int gpio_valid(int gpio)
216 {
217 if (gpio < 0)
218 return -1;
219 if (OMAP_GPIO_IS_MPUIO(gpio)) {
220 if ((gpio & OMAP_MPUIO_MASK) > 16)
221 return -1;
222 return 0;
223 }
224 #ifdef CONFIG_ARCH_OMAP15XX
225 if (cpu_is_omap15xx() && gpio < 16)
226 return 0;
227 #endif
228 #if defined(CONFIG_ARCH_OMAP16XX)
229 if ((cpu_is_omap16xx()) && gpio < 64)
230 return 0;
231 #endif
232 #ifdef CONFIG_ARCH_OMAP730
233 if (cpu_is_omap730() && gpio < 192)
234 return 0;
235 #endif
236 #ifdef CONFIG_ARCH_OMAP24XX
237 if (cpu_is_omap24xx() && gpio < 128)
238 return 0;
239 #endif
240 return -1;
241 }
242
243 static int check_gpio(int gpio)
244 {
245 if (unlikely(gpio_valid(gpio)) < 0) {
246 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
247 dump_stack();
248 return -1;
249 }
250 return 0;
251 }
252
253 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
254 {
255 void __iomem *reg = bank->base;
256 u32 l;
257
258 switch (bank->method) {
259 case METHOD_MPUIO:
260 reg += OMAP_MPUIO_IO_CNTL;
261 break;
262 case METHOD_GPIO_1510:
263 reg += OMAP1510_GPIO_DIR_CONTROL;
264 break;
265 case METHOD_GPIO_1610:
266 reg += OMAP1610_GPIO_DIRECTION;
267 break;
268 case METHOD_GPIO_730:
269 reg += OMAP730_GPIO_DIR_CONTROL;
270 break;
271 case METHOD_GPIO_24XX:
272 reg += OMAP24XX_GPIO_OE;
273 break;
274 }
275 l = __raw_readl(reg);
276 if (is_input)
277 l |= 1 << gpio;
278 else
279 l &= ~(1 << gpio);
280 __raw_writel(l, reg);
281 }
282
283 void omap_set_gpio_direction(int gpio, int is_input)
284 {
285 struct gpio_bank *bank;
286
287 if (check_gpio(gpio) < 0)
288 return;
289 bank = get_gpio_bank(gpio);
290 spin_lock(&bank->lock);
291 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
292 spin_unlock(&bank->lock);
293 }
294
295 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
296 {
297 void __iomem *reg = bank->base;
298 u32 l = 0;
299
300 switch (bank->method) {
301 case METHOD_MPUIO:
302 reg += OMAP_MPUIO_OUTPUT;
303 l = __raw_readl(reg);
304 if (enable)
305 l |= 1 << gpio;
306 else
307 l &= ~(1 << gpio);
308 break;
309 case METHOD_GPIO_1510:
310 reg += OMAP1510_GPIO_DATA_OUTPUT;
311 l = __raw_readl(reg);
312 if (enable)
313 l |= 1 << gpio;
314 else
315 l &= ~(1 << gpio);
316 break;
317 case METHOD_GPIO_1610:
318 if (enable)
319 reg += OMAP1610_GPIO_SET_DATAOUT;
320 else
321 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
322 l = 1 << gpio;
323 break;
324 case METHOD_GPIO_730:
325 reg += OMAP730_GPIO_DATA_OUTPUT;
326 l = __raw_readl(reg);
327 if (enable)
328 l |= 1 << gpio;
329 else
330 l &= ~(1 << gpio);
331 break;
332 case METHOD_GPIO_24XX:
333 if (enable)
334 reg += OMAP24XX_GPIO_SETDATAOUT;
335 else
336 reg += OMAP24XX_GPIO_CLEARDATAOUT;
337 l = 1 << gpio;
338 break;
339 default:
340 BUG();
341 return;
342 }
343 __raw_writel(l, reg);
344 }
345
346 void omap_set_gpio_dataout(int gpio, int enable)
347 {
348 struct gpio_bank *bank;
349
350 if (check_gpio(gpio) < 0)
351 return;
352 bank = get_gpio_bank(gpio);
353 spin_lock(&bank->lock);
354 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
355 spin_unlock(&bank->lock);
356 }
357
358 int omap_get_gpio_datain(int gpio)
359 {
360 struct gpio_bank *bank;
361 void __iomem *reg;
362
363 if (check_gpio(gpio) < 0)
364 return -1;
365 bank = get_gpio_bank(gpio);
366 reg = bank->base;
367 switch (bank->method) {
368 case METHOD_MPUIO:
369 reg += OMAP_MPUIO_INPUT_LATCH;
370 break;
371 case METHOD_GPIO_1510:
372 reg += OMAP1510_GPIO_DATA_INPUT;
373 break;
374 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_DATAIN;
376 break;
377 case METHOD_GPIO_730:
378 reg += OMAP730_GPIO_DATA_INPUT;
379 break;
380 case METHOD_GPIO_24XX:
381 reg += OMAP24XX_GPIO_DATAIN;
382 break;
383 default:
384 BUG();
385 return -1;
386 }
387 return (__raw_readl(reg)
388 & (1 << get_gpio_index(gpio))) != 0;
389 }
390
391 #define MOD_REG_BIT(reg, bit_mask, set) \
392 do { \
393 int l = __raw_readl(base + reg); \
394 if (set) l |= bit_mask; \
395 else l &= ~bit_mask; \
396 __raw_writel(l, base + reg); \
397 } while(0)
398
399 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
400 {
401 u32 gpio_bit = 1 << gpio;
402
403 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
404 trigger & __IRQT_LOWLVL);
405 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
406 trigger & __IRQT_HIGHLVL);
407 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
408 trigger & __IRQT_RISEDGE);
409 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
410 trigger & __IRQT_FALEDGE);
411 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
412 * triggering requested. */
413 }
414
415 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
416 {
417 void __iomem *reg = bank->base;
418 u32 l = 0;
419
420 switch (bank->method) {
421 case METHOD_MPUIO:
422 reg += OMAP_MPUIO_GPIO_INT_EDGE;
423 l = __raw_readl(reg);
424 if (trigger & __IRQT_RISEDGE)
425 l |= 1 << gpio;
426 else if (trigger & __IRQT_FALEDGE)
427 l &= ~(1 << gpio);
428 else
429 goto bad;
430 break;
431 case METHOD_GPIO_1510:
432 reg += OMAP1510_GPIO_INT_CONTROL;
433 l = __raw_readl(reg);
434 if (trigger & __IRQT_RISEDGE)
435 l |= 1 << gpio;
436 else if (trigger & __IRQT_FALEDGE)
437 l &= ~(1 << gpio);
438 else
439 goto bad;
440 break;
441 case METHOD_GPIO_1610:
442 if (gpio & 0x08)
443 reg += OMAP1610_GPIO_EDGE_CTRL2;
444 else
445 reg += OMAP1610_GPIO_EDGE_CTRL1;
446 gpio &= 0x07;
447 /* We allow only edge triggering, i.e. two lowest bits */
448 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
449 BUG();
450 l = __raw_readl(reg);
451 l &= ~(3 << (gpio << 1));
452 if (trigger & __IRQT_RISEDGE)
453 l |= 2 << (gpio << 1);
454 if (trigger & __IRQT_FALEDGE)
455 l |= 1 << (gpio << 1);
456 break;
457 case METHOD_GPIO_730:
458 reg += OMAP730_GPIO_INT_CONTROL;
459 l = __raw_readl(reg);
460 if (trigger & __IRQT_RISEDGE)
461 l |= 1 << gpio;
462 else if (trigger & __IRQT_FALEDGE)
463 l &= ~(1 << gpio);
464 else
465 goto bad;
466 break;
467 case METHOD_GPIO_24XX:
468 set_24xx_gpio_triggering(reg, gpio, trigger);
469 break;
470 default:
471 BUG();
472 goto bad;
473 }
474 __raw_writel(l, reg);
475 return 0;
476 bad:
477 return -EINVAL;
478 }
479
480 static int gpio_irq_type(unsigned irq, unsigned type)
481 {
482 struct gpio_bank *bank;
483 unsigned gpio;
484 int retval;
485
486 if (irq > IH_MPUIO_BASE)
487 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
488 else
489 gpio = irq - IH_GPIO_BASE;
490
491 if (check_gpio(gpio) < 0)
492 return -EINVAL;
493
494 if (type & IRQT_PROBE)
495 return -EINVAL;
496 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
497 return -EINVAL;
498
499 bank = get_gpio_bank(gpio);
500 spin_lock(&bank->lock);
501 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
502 spin_unlock(&bank->lock);
503 return retval;
504 }
505
506 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
507 {
508 void __iomem *reg = bank->base;
509
510 switch (bank->method) {
511 case METHOD_MPUIO:
512 /* MPUIO irqstatus is reset by reading the status register,
513 * so do nothing here */
514 return;
515 case METHOD_GPIO_1510:
516 reg += OMAP1510_GPIO_INT_STATUS;
517 break;
518 case METHOD_GPIO_1610:
519 reg += OMAP1610_GPIO_IRQSTATUS1;
520 break;
521 case METHOD_GPIO_730:
522 reg += OMAP730_GPIO_INT_STATUS;
523 break;
524 case METHOD_GPIO_24XX:
525 reg += OMAP24XX_GPIO_IRQSTATUS1;
526 break;
527 default:
528 BUG();
529 return;
530 }
531 __raw_writel(gpio_mask, reg);
532 }
533
534 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
535 {
536 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
537 }
538
539 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
540 {
541 void __iomem *reg = bank->base;
542 int inv = 0;
543 u32 l;
544 u32 mask;
545
546 switch (bank->method) {
547 case METHOD_MPUIO:
548 reg += OMAP_MPUIO_GPIO_MASKIT;
549 mask = 0xffff;
550 inv = 1;
551 break;
552 case METHOD_GPIO_1510:
553 reg += OMAP1510_GPIO_INT_MASK;
554 mask = 0xffff;
555 inv = 1;
556 break;
557 case METHOD_GPIO_1610:
558 reg += OMAP1610_GPIO_IRQENABLE1;
559 mask = 0xffff;
560 break;
561 case METHOD_GPIO_730:
562 reg += OMAP730_GPIO_INT_MASK;
563 mask = 0xffffffff;
564 inv = 1;
565 break;
566 case METHOD_GPIO_24XX:
567 reg += OMAP24XX_GPIO_IRQENABLE1;
568 mask = 0xffffffff;
569 break;
570 default:
571 BUG();
572 return 0;
573 }
574
575 l = __raw_readl(reg);
576 if (inv)
577 l = ~l;
578 l &= mask;
579 return l;
580 }
581
582 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
583 {
584 void __iomem *reg = bank->base;
585 u32 l;
586
587 switch (bank->method) {
588 case METHOD_MPUIO:
589 reg += OMAP_MPUIO_GPIO_MASKIT;
590 l = __raw_readl(reg);
591 if (enable)
592 l &= ~(gpio_mask);
593 else
594 l |= gpio_mask;
595 break;
596 case METHOD_GPIO_1510:
597 reg += OMAP1510_GPIO_INT_MASK;
598 l = __raw_readl(reg);
599 if (enable)
600 l &= ~(gpio_mask);
601 else
602 l |= gpio_mask;
603 break;
604 case METHOD_GPIO_1610:
605 if (enable)
606 reg += OMAP1610_GPIO_SET_IRQENABLE1;
607 else
608 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
609 l = gpio_mask;
610 break;
611 case METHOD_GPIO_730:
612 reg += OMAP730_GPIO_INT_MASK;
613 l = __raw_readl(reg);
614 if (enable)
615 l &= ~(gpio_mask);
616 else
617 l |= gpio_mask;
618 break;
619 case METHOD_GPIO_24XX:
620 if (enable)
621 reg += OMAP24XX_GPIO_SETIRQENABLE1;
622 else
623 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
624 l = gpio_mask;
625 break;
626 default:
627 BUG();
628 return;
629 }
630 __raw_writel(l, reg);
631 }
632
633 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
634 {
635 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
636 }
637
638 /*
639 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
640 * 1510 does not seem to have a wake-up register. If JTAG is connected
641 * to the target, system will wake up always on GPIO events. While
642 * system is running all registered GPIO interrupts need to have wake-up
643 * enabled. When system is suspended, only selected GPIO interrupts need
644 * to have wake-up enabled.
645 */
646 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
647 {
648 switch (bank->method) {
649 case METHOD_GPIO_1610:
650 case METHOD_GPIO_24XX:
651 spin_lock(&bank->lock);
652 if (enable)
653 bank->suspend_wakeup |= (1 << gpio);
654 else
655 bank->suspend_wakeup &= ~(1 << gpio);
656 spin_unlock(&bank->lock);
657 return 0;
658 default:
659 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
660 bank->method);
661 return -EINVAL;
662 }
663 }
664
665 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
666 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
667 {
668 unsigned int gpio = irq - IH_GPIO_BASE;
669 struct gpio_bank *bank;
670 int retval;
671
672 if (check_gpio(gpio) < 0)
673 return -ENODEV;
674 bank = get_gpio_bank(gpio);
675 spin_lock(&bank->lock);
676 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
677 spin_unlock(&bank->lock);
678
679 return retval;
680 }
681
682 int omap_request_gpio(int gpio)
683 {
684 struct gpio_bank *bank;
685
686 if (check_gpio(gpio) < 0)
687 return -EINVAL;
688
689 bank = get_gpio_bank(gpio);
690 spin_lock(&bank->lock);
691 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
692 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
693 dump_stack();
694 spin_unlock(&bank->lock);
695 return -1;
696 }
697 bank->reserved_map |= (1 << get_gpio_index(gpio));
698
699 /* Set trigger to none. You need to enable the trigger after request_irq */
700 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
701
702 #ifdef CONFIG_ARCH_OMAP15XX
703 if (bank->method == METHOD_GPIO_1510) {
704 void __iomem *reg;
705
706 /* Claim the pin for MPU */
707 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
708 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
709 }
710 #endif
711 #ifdef CONFIG_ARCH_OMAP16XX
712 if (bank->method == METHOD_GPIO_1610) {
713 /* Enable wake-up during idle for dynamic tick */
714 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
715 __raw_writel(1 << get_gpio_index(gpio), reg);
716 }
717 #endif
718 #ifdef CONFIG_ARCH_OMAP24XX
719 if (bank->method == METHOD_GPIO_24XX) {
720 /* Enable wake-up during idle for dynamic tick */
721 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
722 __raw_writel(1 << get_gpio_index(gpio), reg);
723 }
724 #endif
725 spin_unlock(&bank->lock);
726
727 return 0;
728 }
729
730 void omap_free_gpio(int gpio)
731 {
732 struct gpio_bank *bank;
733
734 if (check_gpio(gpio) < 0)
735 return;
736 bank = get_gpio_bank(gpio);
737 spin_lock(&bank->lock);
738 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
739 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
740 dump_stack();
741 spin_unlock(&bank->lock);
742 return;
743 }
744 #ifdef CONFIG_ARCH_OMAP16XX
745 if (bank->method == METHOD_GPIO_1610) {
746 /* Disable wake-up during idle for dynamic tick */
747 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
748 __raw_writel(1 << get_gpio_index(gpio), reg);
749 }
750 #endif
751 #ifdef CONFIG_ARCH_OMAP24XX
752 if (bank->method == METHOD_GPIO_24XX) {
753 /* Disable wake-up during idle for dynamic tick */
754 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
755 __raw_writel(1 << get_gpio_index(gpio), reg);
756 }
757 #endif
758 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
759 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
760 _set_gpio_irqenable(bank, gpio, 0);
761 _clear_gpio_irqstatus(bank, gpio);
762 spin_unlock(&bank->lock);
763 }
764
765 /*
766 * We need to unmask the GPIO bank interrupt as soon as possible to
767 * avoid missing GPIO interrupts for other lines in the bank.
768 * Then we need to mask-read-clear-unmask the triggered GPIO lines
769 * in the bank to avoid missing nested interrupts for a GPIO line.
770 * If we wait to unmask individual GPIO lines in the bank after the
771 * line's interrupt handler has been run, we may miss some nested
772 * interrupts.
773 */
774 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
775 struct pt_regs *regs)
776 {
777 void __iomem *isr_reg = NULL;
778 u32 isr;
779 unsigned int gpio_irq;
780 struct gpio_bank *bank;
781 u32 retrigger = 0;
782 int unmasked = 0;
783
784 desc->chip->ack(irq);
785
786 bank = get_irq_data(irq);
787 if (bank->method == METHOD_MPUIO)
788 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
789 #ifdef CONFIG_ARCH_OMAP15XX
790 if (bank->method == METHOD_GPIO_1510)
791 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
792 #endif
793 #if defined(CONFIG_ARCH_OMAP16XX)
794 if (bank->method == METHOD_GPIO_1610)
795 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
796 #endif
797 #ifdef CONFIG_ARCH_OMAP730
798 if (bank->method == METHOD_GPIO_730)
799 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
800 #endif
801 #ifdef CONFIG_ARCH_OMAP24XX
802 if (bank->method == METHOD_GPIO_24XX)
803 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
804 #endif
805 while(1) {
806 u32 isr_saved, level_mask = 0;
807 u32 enabled;
808
809 enabled = _get_gpio_irqbank_mask(bank);
810 isr_saved = isr = __raw_readl(isr_reg) & enabled;
811
812 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
813 isr &= 0x0000ffff;
814
815 if (cpu_is_omap24xx()) {
816 level_mask =
817 __raw_readl(bank->base +
818 OMAP24XX_GPIO_LEVELDETECT0) |
819 __raw_readl(bank->base +
820 OMAP24XX_GPIO_LEVELDETECT1);
821 level_mask &= enabled;
822 }
823
824 /* clear edge sensitive interrupts before handler(s) are
825 called so that we don't miss any interrupt occurred while
826 executing them */
827 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
828 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
829 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
830
831 /* if there is only edge sensitive GPIO pin interrupts
832 configured, we could unmask GPIO bank interrupt immediately */
833 if (!level_mask && !unmasked) {
834 unmasked = 1;
835 desc->chip->unmask(irq);
836 }
837
838 isr |= retrigger;
839 retrigger = 0;
840 if (!isr)
841 break;
842
843 gpio_irq = bank->virtual_irq_start;
844 for (; isr != 0; isr >>= 1, gpio_irq++) {
845 struct irqdesc *d;
846 int irq_mask;
847 if (!(isr & 1))
848 continue;
849 d = irq_desc + gpio_irq;
850 /* Don't run the handler if it's already running
851 * or was disabled lazely.
852 */
853 if (unlikely((d->depth ||
854 (d->status & IRQ_INPROGRESS)))) {
855 irq_mask = 1 <<
856 (gpio_irq - bank->virtual_irq_start);
857 /* The unmasking will be done by
858 * enable_irq in case it is disabled or
859 * after returning from the handler if
860 * it's already running.
861 */
862 _enable_gpio_irqbank(bank, irq_mask, 0);
863 if (!d->depth) {
864 /* Level triggered interrupts
865 * won't ever be reentered
866 */
867 BUG_ON(level_mask & irq_mask);
868 d->status |= IRQ_PENDING;
869 }
870 continue;
871 }
872
873 desc_handle_irq(gpio_irq, d, regs);
874
875 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
876 irq_mask = 1 <<
877 (gpio_irq - bank->virtual_irq_start);
878 d->status &= ~IRQ_PENDING;
879 _enable_gpio_irqbank(bank, irq_mask, 1);
880 retrigger |= irq_mask;
881 }
882 }
883
884 if (cpu_is_omap24xx()) {
885 /* clear level sensitive interrupts after handler(s) */
886 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
887 _clear_gpio_irqbank(bank, isr_saved & level_mask);
888 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
889 }
890
891 }
892 /* if bank has any level sensitive GPIO pin interrupt
893 configured, we must unmask the bank interrupt only after
894 handler(s) are executed in order to avoid spurious bank
895 interrupt */
896 if (!unmasked)
897 desc->chip->unmask(irq);
898
899 }
900
901 static void gpio_ack_irq(unsigned int irq)
902 {
903 unsigned int gpio = irq - IH_GPIO_BASE;
904 struct gpio_bank *bank = get_gpio_bank(gpio);
905
906 _clear_gpio_irqstatus(bank, gpio);
907 }
908
909 static void gpio_mask_irq(unsigned int irq)
910 {
911 unsigned int gpio = irq - IH_GPIO_BASE;
912 struct gpio_bank *bank = get_gpio_bank(gpio);
913
914 _set_gpio_irqenable(bank, gpio, 0);
915 }
916
917 static void gpio_unmask_irq(unsigned int irq)
918 {
919 unsigned int gpio = irq - IH_GPIO_BASE;
920 unsigned int gpio_idx = get_gpio_index(gpio);
921 struct gpio_bank *bank = get_gpio_bank(gpio);
922
923 _set_gpio_irqenable(bank, gpio_idx, 1);
924 }
925
926 static void mpuio_ack_irq(unsigned int irq)
927 {
928 /* The ISR is reset automatically, so do nothing here. */
929 }
930
931 static void mpuio_mask_irq(unsigned int irq)
932 {
933 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
934 struct gpio_bank *bank = get_gpio_bank(gpio);
935
936 _set_gpio_irqenable(bank, gpio, 0);
937 }
938
939 static void mpuio_unmask_irq(unsigned int irq)
940 {
941 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
942 struct gpio_bank *bank = get_gpio_bank(gpio);
943
944 _set_gpio_irqenable(bank, gpio, 1);
945 }
946
947 static struct irq_chip gpio_irq_chip = {
948 .name = "GPIO",
949 .ack = gpio_ack_irq,
950 .mask = gpio_mask_irq,
951 .unmask = gpio_unmask_irq,
952 .set_type = gpio_irq_type,
953 .set_wake = gpio_wake_enable,
954 };
955
956 static struct irq_chip mpuio_irq_chip = {
957 .name = "MPUIO",
958 .ack = mpuio_ack_irq,
959 .mask = mpuio_mask_irq,
960 .unmask = mpuio_unmask_irq
961 };
962
963 static int initialized;
964 static struct clk * gpio_ick;
965 static struct clk * gpio_fck;
966
967 static int __init _omap_gpio_init(void)
968 {
969 int i;
970 struct gpio_bank *bank;
971
972 initialized = 1;
973
974 if (cpu_is_omap15xx()) {
975 gpio_ick = clk_get(NULL, "arm_gpio_ck");
976 if (IS_ERR(gpio_ick))
977 printk("Could not get arm_gpio_ck\n");
978 else
979 clk_enable(gpio_ick);
980 }
981 if (cpu_is_omap24xx()) {
982 gpio_ick = clk_get(NULL, "gpios_ick");
983 if (IS_ERR(gpio_ick))
984 printk("Could not get gpios_ick\n");
985 else
986 clk_enable(gpio_ick);
987 gpio_fck = clk_get(NULL, "gpios_fck");
988 if (IS_ERR(gpio_ick))
989 printk("Could not get gpios_fck\n");
990 else
991 clk_enable(gpio_fck);
992 }
993
994 #ifdef CONFIG_ARCH_OMAP15XX
995 if (cpu_is_omap15xx()) {
996 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
997 gpio_bank_count = 2;
998 gpio_bank = gpio_bank_1510;
999 }
1000 #endif
1001 #if defined(CONFIG_ARCH_OMAP16XX)
1002 if (cpu_is_omap16xx()) {
1003 u32 rev;
1004
1005 gpio_bank_count = 5;
1006 gpio_bank = gpio_bank_1610;
1007 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1008 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1009 (rev >> 4) & 0x0f, rev & 0x0f);
1010 }
1011 #endif
1012 #ifdef CONFIG_ARCH_OMAP730
1013 if (cpu_is_omap730()) {
1014 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1015 gpio_bank_count = 7;
1016 gpio_bank = gpio_bank_730;
1017 }
1018 #endif
1019 #ifdef CONFIG_ARCH_OMAP24XX
1020 if (cpu_is_omap24xx()) {
1021 int rev;
1022
1023 gpio_bank_count = 4;
1024 gpio_bank = gpio_bank_24xx;
1025 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1026 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1027 (rev >> 4) & 0x0f, rev & 0x0f);
1028 }
1029 #endif
1030 for (i = 0; i < gpio_bank_count; i++) {
1031 int j, gpio_count = 16;
1032
1033 bank = &gpio_bank[i];
1034 bank->reserved_map = 0;
1035 bank->base = IO_ADDRESS(bank->base);
1036 spin_lock_init(&bank->lock);
1037 if (bank->method == METHOD_MPUIO) {
1038 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1039 }
1040 #ifdef CONFIG_ARCH_OMAP15XX
1041 if (bank->method == METHOD_GPIO_1510) {
1042 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1043 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1044 }
1045 #endif
1046 #if defined(CONFIG_ARCH_OMAP16XX)
1047 if (bank->method == METHOD_GPIO_1610) {
1048 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1049 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1050 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1051 }
1052 #endif
1053 #ifdef CONFIG_ARCH_OMAP730
1054 if (bank->method == METHOD_GPIO_730) {
1055 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1056 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1057
1058 gpio_count = 32; /* 730 has 32-bit GPIOs */
1059 }
1060 #endif
1061 #ifdef CONFIG_ARCH_OMAP24XX
1062 if (bank->method == METHOD_GPIO_24XX) {
1063 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1064 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1065
1066 gpio_count = 32;
1067 }
1068 #endif
1069 for (j = bank->virtual_irq_start;
1070 j < bank->virtual_irq_start + gpio_count; j++) {
1071 if (bank->method == METHOD_MPUIO)
1072 set_irq_chip(j, &mpuio_irq_chip);
1073 else
1074 set_irq_chip(j, &gpio_irq_chip);
1075 set_irq_handler(j, do_simple_IRQ);
1076 set_irq_flags(j, IRQF_VALID);
1077 }
1078 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1079 set_irq_data(bank->irq, bank);
1080 }
1081
1082 /* Enable system clock for GPIO module.
1083 * The CAM_CLK_CTRL *is* really the right place. */
1084 if (cpu_is_omap16xx())
1085 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1086
1087 return 0;
1088 }
1089
1090 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1091 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1092 {
1093 int i;
1094
1095 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1096 return 0;
1097
1098 for (i = 0; i < gpio_bank_count; i++) {
1099 struct gpio_bank *bank = &gpio_bank[i];
1100 void __iomem *wake_status;
1101 void __iomem *wake_clear;
1102 void __iomem *wake_set;
1103
1104 switch (bank->method) {
1105 case METHOD_GPIO_1610:
1106 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1107 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1108 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1109 break;
1110 case METHOD_GPIO_24XX:
1111 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1112 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1113 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1114 break;
1115 default:
1116 continue;
1117 }
1118
1119 spin_lock(&bank->lock);
1120 bank->saved_wakeup = __raw_readl(wake_status);
1121 __raw_writel(0xffffffff, wake_clear);
1122 __raw_writel(bank->suspend_wakeup, wake_set);
1123 spin_unlock(&bank->lock);
1124 }
1125
1126 return 0;
1127 }
1128
1129 static int omap_gpio_resume(struct sys_device *dev)
1130 {
1131 int i;
1132
1133 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1134 return 0;
1135
1136 for (i = 0; i < gpio_bank_count; i++) {
1137 struct gpio_bank *bank = &gpio_bank[i];
1138 void __iomem *wake_clear;
1139 void __iomem *wake_set;
1140
1141 switch (bank->method) {
1142 case METHOD_GPIO_1610:
1143 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1144 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1145 break;
1146 case METHOD_GPIO_24XX:
1147 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1148 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1149 break;
1150 default:
1151 continue;
1152 }
1153
1154 spin_lock(&bank->lock);
1155 __raw_writel(0xffffffff, wake_clear);
1156 __raw_writel(bank->saved_wakeup, wake_set);
1157 spin_unlock(&bank->lock);
1158 }
1159
1160 return 0;
1161 }
1162
1163 static struct sysdev_class omap_gpio_sysclass = {
1164 set_kset_name("gpio"),
1165 .suspend = omap_gpio_suspend,
1166 .resume = omap_gpio_resume,
1167 };
1168
1169 static struct sys_device omap_gpio_device = {
1170 .id = 0,
1171 .cls = &omap_gpio_sysclass,
1172 };
1173 #endif
1174
1175 /*
1176 * This may get called early from board specific init
1177 * for boards that have interrupts routed via FPGA.
1178 */
1179 int omap_gpio_init(void)
1180 {
1181 if (!initialized)
1182 return _omap_gpio_init();
1183 else
1184 return 0;
1185 }
1186
1187 static int __init omap_gpio_sysinit(void)
1188 {
1189 int ret = 0;
1190
1191 if (!initialized)
1192 ret = _omap_gpio_init();
1193
1194 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1195 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1196 if (ret == 0) {
1197 ret = sysdev_class_register(&omap_gpio_sysclass);
1198 if (ret == 0)
1199 ret = sysdev_register(&omap_gpio_device);
1200 }
1201 }
1202 #endif
1203
1204 return ret;
1205 }
1206
1207 EXPORT_SYMBOL(omap_request_gpio);
1208 EXPORT_SYMBOL(omap_free_gpio);
1209 EXPORT_SYMBOL(omap_set_gpio_direction);
1210 EXPORT_SYMBOL(omap_set_gpio_dataout);
1211 EXPORT_SYMBOL(omap_get_gpio_datain);
1212
1213 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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