arch/arm/plat-omap/include/plat/sdrc.h

   1 #ifndef ____ASM_ARCH_SDRC_H
   2 #define ____ASM_ARCH_SDRC_H
   3
   4 /*
   5  * OMAP2/3 SDRC/SMS register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Tony Lindgren
  11  * Paul Walmsley
  12  * Richard Woodruff
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19
  20 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
  21
  22 #define SDRC_SYSCONFIG          0x010
  23 #define SDRC_CS_CFG             0x040
  24 #define SDRC_SHARING            0x044
  25 #define SDRC_ERR_TYPE           0x04C
  26 #define SDRC_DLLA_CTRL          0x060
  27 #define SDRC_DLLA_STATUS        0x064
  28 #define SDRC_DLLB_CTRL          0x068
  29 #define SDRC_DLLB_STATUS        0x06C
  30 #define SDRC_POWER              0x070
  31 #define SDRC_MCFG_0             0x080
  32 #define SDRC_MR_0               0x084
  33 #define SDRC_EMR2_0             0x08c
  34 #define SDRC_ACTIM_CTRL_A_0     0x09c
  35 #define SDRC_ACTIM_CTRL_B_0     0x0a0
  36 #define SDRC_RFR_CTRL_0         0x0a4
  37 #define SDRC_MANUAL_0           0x0a8
  38 #define SDRC_MCFG_1             0x0B0
  39 #define SDRC_MR_1               0x0B4
  40 #define SDRC_EMR2_1             0x0BC
  41 #define SDRC_ACTIM_CTRL_A_1     0x0C4
  42 #define SDRC_ACTIM_CTRL_B_1     0x0C8
  43 #define SDRC_RFR_CTRL_1         0x0D4
  44 #define SDRC_MANUAL_1           0x0D8
  45
  46 #define SDRC_POWER_AUTOCOUNT_SHIFT      8
  47 #define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
  48 #define SDRC_POWER_CLKCTRL_SHIFT        4
  49 #define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
  50 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
  51
  52 /*
  53  * These values represent the number of memory clock cycles between
  54  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
  55  * rows per device, and include a subtraction of a 50 cycle window in the
  56  * event that the autorefresh command is delayed due to other SDRC activity.
  57  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
  58  * counter reaches 0.
  59  *
  60  * These represent optimal values for common parts, it won't work for all.
  61  * As long as you scale down, most parameters are still work, they just
  62  * become sub-optimal. The RFR value goes in the opposite direction. If you
  63  * don't adjust it down as your clock period increases the refresh interval
  64  * will not be met. Setting all parameters for complete worst case may work,
  65  * but may cut memory performance by 2x. Due to errata the DLLs need to be
  66  * unlocked and their value needs run time calibration. A dynamic call is
  67  * need for that as no single right value exists acorss production samples.
  68  *
  69  * Only the FULL speed values are given. Current code is such that rate
  70  * changes must be made at DPLLoutx2. The actual value adjustment for low
  71  * frequency operation will be handled by omap_set_performance()
  72  *
  73  * By having the boot loader boot up in the fastest L4 speed available likely
  74  * will result in something which you can switch between.
  75  */
  76 #define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
  77 #define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
  78 #define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
  79 #define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
  80 #define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
  81
  82
  83 /*
  84  * SMS register access
  85  */
  86
  87 #define OMAP242X_SMS_REGADDR(reg)                                       \
  88                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
  89 #define OMAP243X_SMS_REGADDR(reg)                                       \
  90                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
  91 #define OMAP343X_SMS_REGADDR(reg)                                       \
  92                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
  93
  94 /* SMS register offsets - read/write with sms_{read,write}_reg() */
  95
  96 #define SMS_SYSCONFIG                   0x010
  97 #define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
  98 #define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
  99 #define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
 100 /* REVISIT: fill in other SMS registers here */
 101
 102
 103 #ifndef __ASSEMBLER__
 104
 105 /**
 106  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
 107  * @rate: SDRC clock rate (in Hz)
 108  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
 109  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
 110  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
 111  * @mr: Value to program to SDRC_MR for this rate
 112  *
 113  * This structure holds a pre-computed set of register values for the
 114  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
 115  * intended to be pre-computed and specified in an array in the board-*.c
 116  * files.  The structure is keyed off the 'rate' field.
 117  */
 118 struct omap_sdrc_params {
 119         unsigned long rate;
 120         u32 actim_ctrla;
 121         u32 actim_ctrlb;
 122         u32 rfr_ctrl;
 123         u32 mr;
 124 };
 125
 126 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
 127 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 128                             struct omap_sdrc_params *sdrc_cs1);
 129 #else
 130 static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 131                                           struct omap_sdrc_params *sdrc_cs1) {};
 132 #endif
 133
 134 int omap2_sdrc_get_params(unsigned long r,
 135                           struct omap_sdrc_params **sdrc_cs0,
 136                           struct omap_sdrc_params **sdrc_cs1);
 137 void omap2_sms_save_context(void);
 138 void omap2_sms_restore_context(void);
 139
 140 void omap2_sms_write_rot_control(u32 val, unsigned ctx);
 141 void omap2_sms_write_rot_size(u32 val, unsigned ctx);
 142 void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
 143
 144 #ifdef CONFIG_ARCH_OMAP2
 145
 146 struct memory_timings {
 147         u32 m_type;             /* ddr = 1, sdr = 0 */
 148         u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
 149         u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
 150         u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
 151         u32 base_cs;            /* base chip select to use for calculations */
 152 };
 153
 154 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
 155 struct omap_sdrc_params *rx51_get_sdram_timings(void);
 156
 157 u32 omap2xxx_sdrc_dll_is_unlocked(void);
 158 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
 159
 160 #endif  /* CONFIG_ARCH_OMAP2 */
 161
 162 #endif  /* __ASSEMBLER__ */
 163
 164 #endif