arch/arm/plat-omap/include/plat/usb.h

   1 // include/asm-arm/mach-omap/usb.h
   2
   3 #ifndef __ASM_ARCH_OMAP_USB_H
   4 #define __ASM_ARCH_OMAP_USB_H
   5
   6 #include <linux/io.h>
   7 #include <linux/usb/musb.h>
   8 #include <plat/board.h>
   9
  10 #define OMAP3_HS_USB_PORTS      3
  11
  12 enum usbhs_omap_port_mode {
  13         OMAP_USBHS_PORT_MODE_UNUSED,
  14         OMAP_EHCI_PORT_MODE_PHY,
  15         OMAP_EHCI_PORT_MODE_TLL,
  16         OMAP_EHCI_PORT_MODE_HSIC,
  17         OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
  18         OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
  19         OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
  20         OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
  21         OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
  22         OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
  23         OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
  24         OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
  25         OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
  26         OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
  27 };
  28
  29 struct usbhs_omap_board_data {
  30         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  31
  32         /* have to be valid if phy_reset is true and portx is in phy mode */
  33         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
  34
  35         /* Set this to true for ES2.x silicon */
  36         unsigned                        es2_compatibility:1;
  37
  38         unsigned                        phy_reset:1;
  39
  40         /*
  41          * Regulators for USB PHYs.
  42          * Each PHY can have a separate regulator.
  43          */
  44         struct regulator                *regulator[OMAP3_HS_USB_PORTS];
  45 };
  46
  47 struct ehci_hcd_omap_platform_data {
  48         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  49         int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
  50         struct regulator                *regulator[OMAP3_HS_USB_PORTS];
  51         unsigned                        phy_reset:1;
  52 };
  53
  54 struct ohci_hcd_omap_platform_data {
  55         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  56         unsigned                        es2_compatibility:1;
  57 };
  58
  59 struct usbhs_omap_platform_data {
  60         enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
  61
  62         struct ehci_hcd_omap_platform_data      *ehci_data;
  63         struct ohci_hcd_omap_platform_data      *ohci_data;
  64 };
  65 /*-------------------------------------------------------------------------*/
  66
  67 #define OMAP1_OTG_BASE                  0xfffb0400
  68 #define OMAP1_UDC_BASE                  0xfffb4000
  69 #define OMAP1_OHCI_BASE                 0xfffba000
  70
  71 #define OMAP2_OHCI_BASE                 0x4805e000
  72 #define OMAP2_UDC_BASE                  0x4805e200
  73 #define OMAP2_OTG_BASE                  0x4805e300
  74
  75 #ifdef CONFIG_ARCH_OMAP1
  76
  77 #define OTG_BASE                        OMAP1_OTG_BASE
  78 #define UDC_BASE                        OMAP1_UDC_BASE
  79 #define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
  80
  81 #else
  82
  83 #define OTG_BASE                        OMAP2_OTG_BASE
  84 #define UDC_BASE                        OMAP2_UDC_BASE
  85 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
  86
  87 struct omap_musb_board_data {
  88         u8      interface_type;
  89         u8      mode;
  90         u16     power;
  91         unsigned extvbus:1;
  92         void    (*set_phy_power)(u8 on);
  93         void    (*clear_irq)(void);
  94         void    (*set_mode)(u8 mode);
  95         void    (*reset)(void);
  96 };
  97
  98 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
  99
 100 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 101
 102 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
 103
 104 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 105 extern int omap4430_phy_set_clk(struct device *dev, int on);
 106 extern int omap4430_phy_init(struct device *dev);
 107 extern int omap4430_phy_exit(struct device *dev);
 108 extern int omap4430_phy_suspend(struct device *dev, int suspend);
 109
 110 /*
 111  * NOTE: Please update omap USB drivers to use ioremap + read/write
 112  */
 113
 114 #define OMAP2_L4_IO_OFFSET      0xb2000000
 115 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
 116
 117 static inline u8 omap_readb(u32 pa)
 118 {
 119         return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
 120 }
 121
 122 static inline u16 omap_readw(u32 pa)
 123 {
 124         return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
 125 }
 126
 127 static inline u32 omap_readl(u32 pa)
 128 {
 129         return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
 130 }
 131
 132 static inline void omap_writeb(u8 v, u32 pa)
 133 {
 134         __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
 135 }
 136
 137
 138 static inline void omap_writew(u16 v, u32 pa)
 139 {
 140         __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
 141 }
 142
 143 static inline void omap_writel(u32 v, u32 pa)
 144 {
 145         __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 146 }
 147
 148 #endif
 149
 150 extern void am35x_musb_reset(void);
 151 extern void am35x_musb_phy_power(u8 on);
 152 extern void am35x_musb_clear_irq(void);
 153 extern void am35x_set_mode(u8 musb_mode);
 154 extern void ti81xx_musb_phy_power(u8 on);
 155
 156 /*
 157  * FIXME correct answer depends on hmc_mode,
 158  * as does (on omap1) any nonzero value for config->otg port number
 159  */
 160 #ifdef  CONFIG_USB_GADGET_OMAP
 161 #define is_usb0_device(config)  1
 162 #else
 163 #define is_usb0_device(config)  0
 164 #endif
 165
 166 void omap_otg_init(struct omap_usb_config *config);
 167
 168 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
 169 void omap1_usb_init(struct omap_usb_config *pdata);
 170 #else
 171 static inline void omap1_usb_init(struct omap_usb_config *pdata)
 172 {
 173 }
 174 #endif
 175
 176 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 177 void omap2_usbfs_init(struct omap_usb_config *pdata);
 178 #else
 179 static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 180 {
 181 }
 182 #endif
 183
 184 /*-------------------------------------------------------------------------*/
 185
 186 /*
 187  * OTG and transceiver registers, for OMAPs starting with ARM926
 188  */
 189 #define OTG_REV                         (OTG_BASE + 0x00)
 190 #define OTG_SYSCON_1                    (OTG_BASE + 0x04)
 191 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 192 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 193 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
 194 #       define   OTG_IDLE_EN            (1 << 15)
 195 #       define   HST_IDLE_EN            (1 << 14)
 196 #       define   DEV_IDLE_EN            (1 << 13)
 197 #       define   OTG_RESET_DONE         (1 << 2)
 198 #       define   OTG_SOFT_RESET         (1 << 1)
 199 #define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 200 #       define   OTG_EN                 (1 << 31)
 201 #       define   USBX_SYNCHRO           (1 << 30)
 202 #       define   OTG_MST16              (1 << 29)
 203 #       define   SRP_GPDATA             (1 << 28)
 204 #       define   SRP_GPDVBUS            (1 << 27)
 205 #       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
 206 #       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
 207 #       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
 208 #       define   SRP_DPW                (1 << 14)
 209 #       define   SRP_DATA               (1 << 13)
 210 #       define   SRP_VBUS               (1 << 12)
 211 #       define   OTG_PADEN              (1 << 10)
 212 #       define   HMC_PADEN              (1 << 9)
 213 #       define   UHOST_EN               (1 << 8)
 214 #       define   HMC_TLLSPEED           (1 << 7)
 215 #       define   HMC_TLLATTACH          (1 << 6)
 216 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
 217 #define OTG_CTRL                        (OTG_BASE + 0x0c)
 218 #       define   OTG_USB2_EN            (1 << 29)
 219 #       define   OTG_USB2_DP            (1 << 28)
 220 #       define   OTG_USB2_DM            (1 << 27)
 221 #       define   OTG_USB1_EN            (1 << 26)
 222 #       define   OTG_USB1_DP            (1 << 25)
 223 #       define   OTG_USB1_DM            (1 << 24)
 224 #       define   OTG_USB0_EN            (1 << 23)
 225 #       define   OTG_USB0_DP            (1 << 22)
 226 #       define   OTG_USB0_DM            (1 << 21)
 227 #       define   OTG_ASESSVLD           (1 << 20)
 228 #       define   OTG_BSESSEND           (1 << 19)
 229 #       define   OTG_BSESSVLD           (1 << 18)
 230 #       define   OTG_VBUSVLD            (1 << 17)
 231 #       define   OTG_ID                 (1 << 16)
 232 #       define   OTG_DRIVER_SEL         (1 << 15)
 233 #       define   OTG_A_SETB_HNPEN       (1 << 12)
 234 #       define   OTG_A_BUSREQ           (1 << 11)
 235 #       define   OTG_B_HNPEN            (1 << 9)
 236 #       define   OTG_B_BUSREQ           (1 << 8)
 237 #       define   OTG_BUSDROP            (1 << 7)
 238 #       define   OTG_PULLDOWN           (1 << 5)
 239 #       define   OTG_PULLUP             (1 << 4)
 240 #       define   OTG_DRV_VBUS           (1 << 3)
 241 #       define   OTG_PD_VBUS            (1 << 2)
 242 #       define   OTG_PU_VBUS            (1 << 1)
 243 #       define   OTG_PU_ID              (1 << 0)
 244 #define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 245 #       define   DRIVER_SWITCH          (1 << 15)
 246 #       define   A_VBUS_ERR             (1 << 13)
 247 #       define   A_REQ_TMROUT           (1 << 12)
 248 #       define   A_SRP_DETECT           (1 << 11)
 249 #       define   B_HNP_FAIL             (1 << 10)
 250 #       define   B_SRP_TMROUT           (1 << 9)
 251 #       define   B_SRP_DONE             (1 << 8)
 252 #       define   B_SRP_STARTED          (1 << 7)
 253 #       define   OPRT_CHG               (1 << 0)
 254 #define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
 255         // same bits as in IRQ_EN
 256 #define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 257 #       define   OTGVPD                 (1 << 14)
 258 #       define   OTGVPU                 (1 << 13)
 259 #       define   OTGPUID                (1 << 12)
 260 #       define   USB2VDR                (1 << 10)
 261 #       define   USB2PDEN               (1 << 9)
 262 #       define   USB2PUEN               (1 << 8)
 263 #       define   USB1VDR                (1 << 6)
 264 #       define   USB1PDEN               (1 << 5)
 265 #       define   USB1PUEN               (1 << 4)
 266 #       define   USB0VDR                (1 << 2)
 267 #       define   USB0PDEN               (1 << 1)
 268 #       define   USB0PUEN               (1 << 0)
 269 #define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
 270 #define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 271
 272 /*-------------------------------------------------------------------------*/
 273
 274 /* OMAP1 */
 275 #define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 276 #       define  CONF_USB2_UNI_R         (1 << 8)
 277 #       define  CONF_USB1_UNI_R         (1 << 7)
 278 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
 279 #       define  CONF_USB0_ISOLATE_R     (1 << 3)
 280 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 281 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
 282
 283 /* OMAP2 */
 284 #       define  USB_UNIDIR                      0x0
 285 #       define  USB_UNIDIR_TLL                  0x1
 286 #       define  USB_BIDIR                       0x2
 287 #       define  USB_BIDIR_TLL                   0x3
 288 #       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
 289 #       define  USBT2TLL5PI             (1 << 17)
 290 #       define  USB0PUENACTLOI          (1 << 16)
 291 #       define  USBSTANDBYCTRL          (1 << 15)
 292 /* AM35x */
 293 /* USB 2.0 PHY Control */
 294 #define CONF2_PHY_GPIOMODE      (1 << 23)
 295 #define CONF2_OTGMODE           (3 << 14)
 296 #define CONF2_NO_OVERRIDE       (0 << 14)
 297 #define CONF2_FORCE_HOST        (1 << 14)
 298 #define CONF2_FORCE_DEVICE      (2 << 14)
 299 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
 300 #define CONF2_SESENDEN          (1 << 13)
 301 #define CONF2_VBDTCTEN          (1 << 12)
 302 #define CONF2_REFFREQ_24MHZ     (2 << 8)
 303 #define CONF2_REFFREQ_26MHZ     (7 << 8)
 304 #define CONF2_REFFREQ_13MHZ     (6 << 8)
 305 #define CONF2_REFFREQ           (0xf << 8)
 306 #define CONF2_PHYCLKGD          (1 << 7)
 307 #define CONF2_VBUSSENSE         (1 << 6)
 308 #define CONF2_PHY_PLLON         (1 << 5)
 309 #define CONF2_RESET             (1 << 4)
 310 #define CONF2_PHYPWRDN          (1 << 3)
 311 #define CONF2_OTGPWRDN          (1 << 2)
 312 #define CONF2_DATPOL            (1 << 1)
 313
 314 /* TI81XX specific definitions */
 315 #define USBCTRL0        0x620
 316 #define USBSTAT0        0x624
 317
 318 /* TI816X PHY controls bits */
 319 #define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
 320 #define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
 321
 322 /* TI814X PHY controls bits */
 323 #define USBPHY_CM_PWRDN         (1 << 0)
 324 #define USBPHY_OTG_PWRDN        (1 << 1)
 325 #define USBPHY_CHGDET_DIS       (1 << 2)
 326 #define USBPHY_CHGDET_RSTRT     (1 << 3)
 327 #define USBPHY_SRCONDM          (1 << 4)
 328 #define USBPHY_SINKONDP         (1 << 5)
 329 #define USBPHY_CHGISINK_EN      (1 << 6)
 330 #define USBPHY_CHGVSRC_EN       (1 << 7)
 331 #define USBPHY_DMPULLUP         (1 << 8)
 332 #define USBPHY_DPPULLUP         (1 << 9)
 333 #define USBPHY_CDET_EXTCTL      (1 << 10)
 334 #define USBPHY_GPIO_MODE        (1 << 12)
 335 #define USBPHY_DPOPBUFCTL       (1 << 13)
 336 #define USBPHY_DMOPBUFCTL       (1 << 14)
 337 #define USBPHY_DPINPUT          (1 << 15)
 338 #define USBPHY_DMINPUT          (1 << 16)
 339 #define USBPHY_DPGPIO_PD        (1 << 17)
 340 #define USBPHY_DMGPIO_PD        (1 << 18)
 341 #define USBPHY_OTGVDET_EN       (1 << 19)
 342 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 343 #define USBPHY_DATA_POLARITY    (1 << 23)
 344
 345 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 346 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
 347 u32 omap1_usb1_init(unsigned nwires);
 348 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
 349 #else
 350 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
 351 {
 352         return 0;
 353 }
 354 static inline u32 omap1_usb1_init(unsigned nwires)
 355 {
 356         return 0;
 357
 358 }
 359 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
 360 {
 361         return 0;
 362 }
 363 #endif
 364
 365 #endif  /* __ASM_ARCH_OMAP_USB_H */