2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
29 #include <plat/mcbsp.h>
31 #include "../mach-omap2/cm-regbits-34xx.h"
33 struct omap_mcbsp
**mcbsp_ptr
;
34 int omap_mcbsp_count
, omap_mcbsp_cache_size
;
36 void omap_mcbsp_write(struct omap_mcbsp
*mcbsp
, u16 reg
, u32 val
)
38 if (cpu_class_is_omap1()) {
39 ((u16
*)mcbsp
->reg_cache
)[reg
/ sizeof(u16
)] = (u16
)val
;
40 __raw_writew((u16
)val
, mcbsp
->io_base
+ reg
);
41 } else if (cpu_is_omap2420()) {
42 ((u16
*)mcbsp
->reg_cache
)[reg
/ sizeof(u32
)] = (u16
)val
;
43 __raw_writew((u16
)val
, mcbsp
->io_base
+ reg
);
45 ((u32
*)mcbsp
->reg_cache
)[reg
/ sizeof(u32
)] = val
;
46 __raw_writel(val
, mcbsp
->io_base
+ reg
);
50 int omap_mcbsp_read(struct omap_mcbsp
*mcbsp
, u16 reg
, bool from_cache
)
52 if (cpu_class_is_omap1()) {
53 return !from_cache
? __raw_readw(mcbsp
->io_base
+ reg
) :
54 ((u16
*)mcbsp
->reg_cache
)[reg
/ sizeof(u16
)];
55 } else if (cpu_is_omap2420()) {
56 return !from_cache
? __raw_readw(mcbsp
->io_base
+ reg
) :
57 ((u16
*)mcbsp
->reg_cache
)[reg
/ sizeof(u32
)];
59 return !from_cache
? __raw_readl(mcbsp
->io_base
+ reg
) :
60 ((u32
*)mcbsp
->reg_cache
)[reg
/ sizeof(u32
)];
64 #ifdef CONFIG_ARCH_OMAP3
65 void omap_mcbsp_st_write(struct omap_mcbsp
*mcbsp
, u16 reg
, u32 val
)
67 __raw_writel(val
, mcbsp
->st_data
->io_base_st
+ reg
);
70 int omap_mcbsp_st_read(struct omap_mcbsp
*mcbsp
, u16 reg
)
72 return __raw_readl(mcbsp
->st_data
->io_base_st
+ reg
);
76 #define MCBSP_READ(mcbsp, reg) \
77 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
78 #define MCBSP_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
80 #define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
83 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
86 #define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
89 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
91 static void omap_mcbsp_dump_reg(u8 id
)
93 struct omap_mcbsp
*mcbsp
= id_to_mcbsp_ptr(id
);
95 dev_dbg(mcbsp
->dev
, "**** McBSP%d regs ****\n", mcbsp
->id
);
96 dev_dbg(mcbsp
->dev
, "DRR2: 0x%04x\n",
97 MCBSP_READ(mcbsp
, DRR2
));
98 dev_dbg(mcbsp
->dev
, "DRR1: 0x%04x\n",
99 MCBSP_READ(mcbsp
, DRR1
));
100 dev_dbg(mcbsp
->dev
, "DXR2: 0x%04x\n",
101 MCBSP_READ(mcbsp
, DXR2
));
102 dev_dbg(mcbsp
->dev
, "DXR1: 0x%04x\n",
103 MCBSP_READ(mcbsp
, DXR1
));
104 dev_dbg(mcbsp
->dev
, "SPCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp
, SPCR2
));
106 dev_dbg(mcbsp
->dev
, "SPCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp
, SPCR1
));
108 dev_dbg(mcbsp
->dev
, "RCR2: 0x%04x\n",
109 MCBSP_READ(mcbsp
, RCR2
));
110 dev_dbg(mcbsp
->dev
, "RCR1: 0x%04x\n",
111 MCBSP_READ(mcbsp
, RCR1
));
112 dev_dbg(mcbsp
->dev
, "XCR2: 0x%04x\n",
113 MCBSP_READ(mcbsp
, XCR2
));
114 dev_dbg(mcbsp
->dev
, "XCR1: 0x%04x\n",
115 MCBSP_READ(mcbsp
, XCR1
));
116 dev_dbg(mcbsp
->dev
, "SRGR2: 0x%04x\n",
117 MCBSP_READ(mcbsp
, SRGR2
));
118 dev_dbg(mcbsp
->dev
, "SRGR1: 0x%04x\n",
119 MCBSP_READ(mcbsp
, SRGR1
));
120 dev_dbg(mcbsp
->dev
, "PCR0: 0x%04x\n",
121 MCBSP_READ(mcbsp
, PCR0
));
122 dev_dbg(mcbsp
->dev
, "***********************\n");
125 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
127 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
130 irqst_spcr2
= MCBSP_READ(mcbsp_tx
, SPCR2
);
131 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n", irqst_spcr2
);
133 if (irqst_spcr2
& XSYNC_ERR
) {
134 dev_err(mcbsp_tx
->dev
, "TX Frame Sync Error! : 0x%x\n",
136 /* Writing zero to XSYNC_ERR clears the IRQ */
137 MCBSP_WRITE(mcbsp_tx
, SPCR2
, MCBSP_READ_CACHE(mcbsp_tx
, SPCR2
));
139 complete(&mcbsp_tx
->tx_irq_completion
);
145 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
147 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
150 irqst_spcr1
= MCBSP_READ(mcbsp_rx
, SPCR1
);
151 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n", irqst_spcr1
);
153 if (irqst_spcr1
& RSYNC_ERR
) {
154 dev_err(mcbsp_rx
->dev
, "RX Frame Sync Error! : 0x%x\n",
156 /* Writing zero to RSYNC_ERR clears the IRQ */
157 MCBSP_WRITE(mcbsp_rx
, SPCR1
, MCBSP_READ_CACHE(mcbsp_rx
, SPCR1
));
159 complete(&mcbsp_rx
->tx_irq_completion
);
165 static void omap_mcbsp_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
167 struct omap_mcbsp
*mcbsp_dma_tx
= data
;
169 dev_dbg(mcbsp_dma_tx
->dev
, "TX DMA callback : 0x%x\n",
170 MCBSP_READ(mcbsp_dma_tx
, SPCR2
));
172 /* We can free the channels */
173 omap_free_dma(mcbsp_dma_tx
->dma_tx_lch
);
174 mcbsp_dma_tx
->dma_tx_lch
= -1;
176 complete(&mcbsp_dma_tx
->tx_dma_completion
);
179 static void omap_mcbsp_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
181 struct omap_mcbsp
*mcbsp_dma_rx
= data
;
183 dev_dbg(mcbsp_dma_rx
->dev
, "RX DMA callback : 0x%x\n",
184 MCBSP_READ(mcbsp_dma_rx
, SPCR2
));
186 /* We can free the channels */
187 omap_free_dma(mcbsp_dma_rx
->dma_rx_lch
);
188 mcbsp_dma_rx
->dma_rx_lch
= -1;
190 complete(&mcbsp_dma_rx
->rx_dma_completion
);
194 * omap_mcbsp_config simply write a config to the
196 * You either call this function or set the McBSP registers
197 * by yourself before calling omap_mcbsp_start().
199 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
201 struct omap_mcbsp
*mcbsp
;
203 if (!omap_mcbsp_check_valid_id(id
)) {
204 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
207 mcbsp
= id_to_mcbsp_ptr(id
);
209 dev_dbg(mcbsp
->dev
, "Configuring McBSP%d phys_base: 0x%08lx\n",
210 mcbsp
->id
, mcbsp
->phys_base
);
212 /* We write the given config */
213 MCBSP_WRITE(mcbsp
, SPCR2
, config
->spcr2
);
214 MCBSP_WRITE(mcbsp
, SPCR1
, config
->spcr1
);
215 MCBSP_WRITE(mcbsp
, RCR2
, config
->rcr2
);
216 MCBSP_WRITE(mcbsp
, RCR1
, config
->rcr1
);
217 MCBSP_WRITE(mcbsp
, XCR2
, config
->xcr2
);
218 MCBSP_WRITE(mcbsp
, XCR1
, config
->xcr1
);
219 MCBSP_WRITE(mcbsp
, SRGR2
, config
->srgr2
);
220 MCBSP_WRITE(mcbsp
, SRGR1
, config
->srgr1
);
221 MCBSP_WRITE(mcbsp
, MCR2
, config
->mcr2
);
222 MCBSP_WRITE(mcbsp
, MCR1
, config
->mcr1
);
223 MCBSP_WRITE(mcbsp
, PCR0
, config
->pcr0
);
224 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
225 MCBSP_WRITE(mcbsp
, XCCR
, config
->xccr
);
226 MCBSP_WRITE(mcbsp
, RCCR
, config
->rccr
);
229 EXPORT_SYMBOL(omap_mcbsp_config
);
231 #ifdef CONFIG_ARCH_OMAP3
232 static void omap_st_on(struct omap_mcbsp
*mcbsp
)
237 * Sidetone uses McBSP ICLK - which must not idle when sidetones
238 * are enabled or sidetones start sounding ugly.
240 w
= cm_read_mod_reg(OMAP3430_PER_MOD
, CM_AUTOIDLE
);
241 w
&= ~(1 << (mcbsp
->id
- 2));
242 cm_write_mod_reg(w
, OMAP3430_PER_MOD
, CM_AUTOIDLE
);
244 /* Enable McBSP Sidetone */
245 w
= MCBSP_READ(mcbsp
, SSELCR
);
246 MCBSP_WRITE(mcbsp
, SSELCR
, w
| SIDETONEEN
);
248 w
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
249 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, w
& ~(ST_AUTOIDLE
));
251 /* Enable Sidetone from Sidetone Core */
252 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
253 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
| ST_SIDETONEEN
);
256 static void omap_st_off(struct omap_mcbsp
*mcbsp
)
260 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
261 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
& ~(ST_SIDETONEEN
));
263 w
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
264 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, w
| ST_AUTOIDLE
);
266 w
= MCBSP_READ(mcbsp
, SSELCR
);
267 MCBSP_WRITE(mcbsp
, SSELCR
, w
& ~(SIDETONEEN
));
269 w
= cm_read_mod_reg(OMAP3430_PER_MOD
, CM_AUTOIDLE
);
270 w
|= 1 << (mcbsp
->id
- 2);
271 cm_write_mod_reg(w
, OMAP3430_PER_MOD
, CM_AUTOIDLE
);
274 static void omap_st_fir_write(struct omap_mcbsp
*mcbsp
, s16
*fir
)
278 val
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
279 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, val
& ~(ST_AUTOIDLE
));
281 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
283 if (val
& ST_COEFFWREN
)
284 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
286 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
| ST_COEFFWREN
);
288 for (i
= 0; i
< 128; i
++)
289 MCBSP_ST_WRITE(mcbsp
, SFIRCR
, fir
[i
]);
293 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
294 while (!(val
& ST_COEFFWRDONE
) && (++i
< 1000))
295 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
297 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
300 dev_err(mcbsp
->dev
, "McBSP FIR load error!\n");
303 static void omap_st_chgain(struct omap_mcbsp
*mcbsp
)
306 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
308 w
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
309 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, w
& ~(ST_AUTOIDLE
));
311 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
313 MCBSP_ST_WRITE(mcbsp
, SGAINCR
, ST_CH0GAIN(st_data
->ch0gain
) | \
314 ST_CH1GAIN(st_data
->ch1gain
));
317 int omap_st_set_chgain(unsigned int id
, int channel
, s16 chgain
)
319 struct omap_mcbsp
*mcbsp
;
320 struct omap_mcbsp_st_data
*st_data
;
323 if (!omap_mcbsp_check_valid_id(id
)) {
324 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
328 mcbsp
= id_to_mcbsp_ptr(id
);
329 st_data
= mcbsp
->st_data
;
334 spin_lock_irq(&mcbsp
->lock
);
336 st_data
->ch0gain
= chgain
;
337 else if (channel
== 1)
338 st_data
->ch1gain
= chgain
;
342 if (st_data
->enabled
)
343 omap_st_chgain(mcbsp
);
344 spin_unlock_irq(&mcbsp
->lock
);
348 EXPORT_SYMBOL(omap_st_set_chgain
);
350 int omap_st_get_chgain(unsigned int id
, int channel
, s16
*chgain
)
352 struct omap_mcbsp
*mcbsp
;
353 struct omap_mcbsp_st_data
*st_data
;
356 if (!omap_mcbsp_check_valid_id(id
)) {
357 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
361 mcbsp
= id_to_mcbsp_ptr(id
);
362 st_data
= mcbsp
->st_data
;
367 spin_lock_irq(&mcbsp
->lock
);
369 *chgain
= st_data
->ch0gain
;
370 else if (channel
== 1)
371 *chgain
= st_data
->ch1gain
;
374 spin_unlock_irq(&mcbsp
->lock
);
378 EXPORT_SYMBOL(omap_st_get_chgain
);
380 static int omap_st_start(struct omap_mcbsp
*mcbsp
)
382 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
384 if (st_data
&& st_data
->enabled
&& !st_data
->running
) {
385 omap_st_fir_write(mcbsp
, st_data
->taps
);
386 omap_st_chgain(mcbsp
);
390 st_data
->running
= 1;
397 int omap_st_enable(unsigned int id
)
399 struct omap_mcbsp
*mcbsp
;
400 struct omap_mcbsp_st_data
*st_data
;
402 if (!omap_mcbsp_check_valid_id(id
)) {
403 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
407 mcbsp
= id_to_mcbsp_ptr(id
);
408 st_data
= mcbsp
->st_data
;
413 spin_lock_irq(&mcbsp
->lock
);
414 st_data
->enabled
= 1;
415 omap_st_start(mcbsp
);
416 spin_unlock_irq(&mcbsp
->lock
);
420 EXPORT_SYMBOL(omap_st_enable
);
422 static int omap_st_stop(struct omap_mcbsp
*mcbsp
)
424 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
426 if (st_data
&& st_data
->running
) {
429 st_data
->running
= 0;
436 int omap_st_disable(unsigned int id
)
438 struct omap_mcbsp
*mcbsp
;
439 struct omap_mcbsp_st_data
*st_data
;
442 if (!omap_mcbsp_check_valid_id(id
)) {
443 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
447 mcbsp
= id_to_mcbsp_ptr(id
);
448 st_data
= mcbsp
->st_data
;
453 spin_lock_irq(&mcbsp
->lock
);
455 st_data
->enabled
= 0;
456 spin_unlock_irq(&mcbsp
->lock
);
460 EXPORT_SYMBOL(omap_st_disable
);
462 int omap_st_is_enabled(unsigned int id
)
464 struct omap_mcbsp
*mcbsp
;
465 struct omap_mcbsp_st_data
*st_data
;
467 if (!omap_mcbsp_check_valid_id(id
)) {
468 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
472 mcbsp
= id_to_mcbsp_ptr(id
);
473 st_data
= mcbsp
->st_data
;
479 return st_data
->enabled
;
481 EXPORT_SYMBOL(omap_st_is_enabled
);
484 * omap_mcbsp_set_tx_threshold configures how to deal
485 * with transmit threshold. the threshold value and handler can be
488 void omap_mcbsp_set_tx_threshold(unsigned int id
, u16 threshold
)
490 struct omap_mcbsp
*mcbsp
;
492 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
495 if (!omap_mcbsp_check_valid_id(id
)) {
496 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
499 mcbsp
= id_to_mcbsp_ptr(id
);
501 MCBSP_WRITE(mcbsp
, THRSH2
, threshold
);
503 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold
);
506 * omap_mcbsp_set_rx_threshold configures how to deal
507 * with receive threshold. the threshold value and handler can be
510 void omap_mcbsp_set_rx_threshold(unsigned int id
, u16 threshold
)
512 struct omap_mcbsp
*mcbsp
;
514 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
517 if (!omap_mcbsp_check_valid_id(id
)) {
518 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
521 mcbsp
= id_to_mcbsp_ptr(id
);
523 MCBSP_WRITE(mcbsp
, THRSH1
, threshold
);
525 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold
);
528 * omap_mcbsp_get_max_tx_thres just return the current configured
529 * maximum threshold for transmission
531 u16
omap_mcbsp_get_max_tx_threshold(unsigned int id
)
533 struct omap_mcbsp
*mcbsp
;
535 if (!omap_mcbsp_check_valid_id(id
)) {
536 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
539 mcbsp
= id_to_mcbsp_ptr(id
);
541 return mcbsp
->max_tx_thres
;
543 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold
);
546 * omap_mcbsp_get_max_rx_thres just return the current configured
547 * maximum threshold for reception
549 u16
omap_mcbsp_get_max_rx_threshold(unsigned int id
)
551 struct omap_mcbsp
*mcbsp
;
553 if (!omap_mcbsp_check_valid_id(id
)) {
554 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
557 mcbsp
= id_to_mcbsp_ptr(id
);
559 return mcbsp
->max_rx_thres
;
561 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold
);
563 #define MCBSP2_FIFO_SIZE 0x500 /* 1024 + 256 locations */
564 #define MCBSP1345_FIFO_SIZE 0x80 /* 128 locations */
566 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
568 u16
omap_mcbsp_get_tx_delay(unsigned int id
)
570 struct omap_mcbsp
*mcbsp
;
573 if (!omap_mcbsp_check_valid_id(id
)) {
574 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
577 mcbsp
= id_to_mcbsp_ptr(id
);
579 /* Returns the number of free locations in the buffer */
580 buffstat
= MCBSP_READ(mcbsp
, XBUFFSTAT
);
582 /* Number of slots are different in McBSP ports */
584 return MCBSP2_FIFO_SIZE
- buffstat
;
586 return MCBSP1345_FIFO_SIZE
- buffstat
;
588 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay
);
591 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
592 * to reach the threshold value (when the DMA will be triggered to read it)
594 u16
omap_mcbsp_get_rx_delay(unsigned int id
)
596 struct omap_mcbsp
*mcbsp
;
597 u16 buffstat
, threshold
;
599 if (!omap_mcbsp_check_valid_id(id
)) {
600 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
603 mcbsp
= id_to_mcbsp_ptr(id
);
605 /* Returns the number of used locations in the buffer */
606 buffstat
= MCBSP_READ(mcbsp
, RBUFFSTAT
);
608 threshold
= MCBSP_READ(mcbsp
, THRSH1
);
610 /* Return the number of location till we reach the threshold limit */
611 if (threshold
<= buffstat
)
614 return threshold
- buffstat
;
616 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay
);
619 * omap_mcbsp_get_dma_op_mode just return the current configured
620 * operating mode for the mcbsp channel
622 int omap_mcbsp_get_dma_op_mode(unsigned int id
)
624 struct omap_mcbsp
*mcbsp
;
627 if (!omap_mcbsp_check_valid_id(id
)) {
628 printk(KERN_ERR
"%s: Invalid id (%u)\n", __func__
, id
+ 1);
631 mcbsp
= id_to_mcbsp_ptr(id
);
633 dma_op_mode
= mcbsp
->dma_op_mode
;
637 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode
);
639 static inline void omap34xx_mcbsp_request(struct omap_mcbsp
*mcbsp
)
642 * Enable wakup behavior, smart idle and all wakeups
643 * REVISIT: some wakeups may be unnecessary
645 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
648 syscon
= MCBSP_READ(mcbsp
, SYSCON
);
649 syscon
&= ~(ENAWAKEUP
| SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
651 if (mcbsp
->dma_op_mode
== MCBSP_DMA_MODE_THRESHOLD
) {
652 syscon
|= (ENAWAKEUP
| SIDLEMODE(0x02) |
653 CLOCKACTIVITY(0x02));
654 MCBSP_WRITE(mcbsp
, WAKEUPEN
, XRDYEN
| RRDYEN
);
656 syscon
|= SIDLEMODE(0x01);
659 MCBSP_WRITE(mcbsp
, SYSCON
, syscon
);
663 static inline void omap34xx_mcbsp_free(struct omap_mcbsp
*mcbsp
)
666 * Disable wakup behavior, smart idle and all wakeups
668 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
671 syscon
= MCBSP_READ(mcbsp
, SYSCON
);
672 syscon
&= ~(ENAWAKEUP
| SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
674 * HW bug workaround - If no_idle mode is taken, we need to
675 * go to smart_idle before going to always_idle, or the
676 * device will not hit retention anymore.
678 syscon
|= SIDLEMODE(0x02);
679 MCBSP_WRITE(mcbsp
, SYSCON
, syscon
);
681 syscon
&= ~(SIDLEMODE(0x03));
682 MCBSP_WRITE(mcbsp
, SYSCON
, syscon
);
684 MCBSP_WRITE(mcbsp
, WAKEUPEN
, 0);
688 static inline void omap34xx_mcbsp_request(struct omap_mcbsp
*mcbsp
) {}
689 static inline void omap34xx_mcbsp_free(struct omap_mcbsp
*mcbsp
) {}
690 static inline void omap_st_start(struct omap_mcbsp
*mcbsp
) {}
691 static inline void omap_st_stop(struct omap_mcbsp
*mcbsp
) {}
695 * We can choose between IRQ based or polled IO.
696 * This needs to be called before omap_mcbsp_request().
698 int omap_mcbsp_set_io_type(unsigned int id
, omap_mcbsp_io_type_t io_type
)
700 struct omap_mcbsp
*mcbsp
;
702 if (!omap_mcbsp_check_valid_id(id
)) {
703 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
706 mcbsp
= id_to_mcbsp_ptr(id
);
708 spin_lock(&mcbsp
->lock
);
711 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
713 spin_unlock(&mcbsp
->lock
);
717 mcbsp
->io_type
= io_type
;
719 spin_unlock(&mcbsp
->lock
);
723 EXPORT_SYMBOL(omap_mcbsp_set_io_type
);
725 int omap_mcbsp_request(unsigned int id
)
727 struct omap_mcbsp
*mcbsp
;
731 if (!omap_mcbsp_check_valid_id(id
)) {
732 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
735 mcbsp
= id_to_mcbsp_ptr(id
);
737 reg_cache
= kzalloc(omap_mcbsp_cache_size
, GFP_KERNEL
);
742 spin_lock(&mcbsp
->lock
);
744 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
751 mcbsp
->reg_cache
= reg_cache
;
752 spin_unlock(&mcbsp
->lock
);
754 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->request
)
755 mcbsp
->pdata
->ops
->request(id
);
757 clk_enable(mcbsp
->iclk
);
758 clk_enable(mcbsp
->fclk
);
760 /* Do procedure specific to omap34xx arch, if applicable */
761 omap34xx_mcbsp_request(mcbsp
);
764 * Make sure that transmitter, receiver and sample-rate generator are
765 * not running before activating IRQs.
767 MCBSP_WRITE(mcbsp
, SPCR1
, 0);
768 MCBSP_WRITE(mcbsp
, SPCR2
, 0);
770 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
771 /* We need to get IRQs here */
772 init_completion(&mcbsp
->tx_irq_completion
);
773 err
= request_irq(mcbsp
->tx_irq
, omap_mcbsp_tx_irq_handler
,
774 0, "McBSP", (void *)mcbsp
);
776 dev_err(mcbsp
->dev
, "Unable to request TX IRQ %d "
777 "for McBSP%d\n", mcbsp
->tx_irq
,
779 goto err_clk_disable
;
783 init_completion(&mcbsp
->rx_irq_completion
);
784 err
= request_irq(mcbsp
->rx_irq
,
785 omap_mcbsp_rx_irq_handler
,
786 0, "McBSP", (void *)mcbsp
);
788 dev_err(mcbsp
->dev
, "Unable to request RX IRQ %d "
789 "for McBSP%d\n", mcbsp
->rx_irq
,
798 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
800 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
801 mcbsp
->pdata
->ops
->free(id
);
803 /* Do procedure specific to omap34xx arch, if applicable */
804 omap34xx_mcbsp_free(mcbsp
);
806 clk_disable(mcbsp
->fclk
);
807 clk_disable(mcbsp
->iclk
);
809 spin_lock(&mcbsp
->lock
);
811 mcbsp
->reg_cache
= NULL
;
813 spin_unlock(&mcbsp
->lock
);
818 EXPORT_SYMBOL(omap_mcbsp_request
);
820 void omap_mcbsp_free(unsigned int id
)
822 struct omap_mcbsp
*mcbsp
;
825 if (!omap_mcbsp_check_valid_id(id
)) {
826 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
829 mcbsp
= id_to_mcbsp_ptr(id
);
831 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
832 mcbsp
->pdata
->ops
->free(id
);
834 /* Do procedure specific to omap34xx arch, if applicable */
835 omap34xx_mcbsp_free(mcbsp
);
837 clk_disable(mcbsp
->fclk
);
838 clk_disable(mcbsp
->iclk
);
840 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
843 free_irq(mcbsp
->rx_irq
, (void *)mcbsp
);
844 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
847 reg_cache
= mcbsp
->reg_cache
;
849 spin_lock(&mcbsp
->lock
);
851 dev_err(mcbsp
->dev
, "McBSP%d was not reserved\n", mcbsp
->id
);
854 mcbsp
->reg_cache
= NULL
;
855 spin_unlock(&mcbsp
->lock
);
860 EXPORT_SYMBOL(omap_mcbsp_free
);
863 * Here we start the McBSP, by enabling transmitter, receiver or both.
864 * If no transmitter or receiver is active prior calling, then sample-rate
865 * generator and frame sync are started.
867 void omap_mcbsp_start(unsigned int id
, int tx
, int rx
)
869 struct omap_mcbsp
*mcbsp
;
873 if (!omap_mcbsp_check_valid_id(id
)) {
874 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
877 mcbsp
= id_to_mcbsp_ptr(id
);
879 if (cpu_is_omap34xx())
880 omap_st_start(mcbsp
);
882 mcbsp
->rx_word_length
= (MCBSP_READ_CACHE(mcbsp
, RCR1
) >> 5) & 0x7;
883 mcbsp
->tx_word_length
= (MCBSP_READ_CACHE(mcbsp
, XCR1
) >> 5) & 0x7;
885 idle
= !((MCBSP_READ_CACHE(mcbsp
, SPCR2
) |
886 MCBSP_READ_CACHE(mcbsp
, SPCR1
)) & 1);
889 /* Start the sample generator */
890 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
891 MCBSP_WRITE(mcbsp
, SPCR2
, w
| (1 << 6));
894 /* Enable transmitter and receiver */
896 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
897 MCBSP_WRITE(mcbsp
, SPCR2
, w
| tx
);
900 w
= MCBSP_READ_CACHE(mcbsp
, SPCR1
);
901 MCBSP_WRITE(mcbsp
, SPCR1
, w
| rx
);
904 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
905 * REVISIT: 100us may give enough time for two CLKSRG, however
906 * due to some unknown PM related, clock gating etc. reason it
912 /* Start frame sync */
913 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
914 MCBSP_WRITE(mcbsp
, SPCR2
, w
| (1 << 7));
917 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
918 /* Release the transmitter and receiver */
919 w
= MCBSP_READ_CACHE(mcbsp
, XCCR
);
920 w
&= ~(tx
? XDISABLE
: 0);
921 MCBSP_WRITE(mcbsp
, XCCR
, w
);
922 w
= MCBSP_READ_CACHE(mcbsp
, RCCR
);
923 w
&= ~(rx
? RDISABLE
: 0);
924 MCBSP_WRITE(mcbsp
, RCCR
, w
);
927 /* Dump McBSP Regs */
928 omap_mcbsp_dump_reg(id
);
930 EXPORT_SYMBOL(omap_mcbsp_start
);
932 void omap_mcbsp_stop(unsigned int id
, int tx
, int rx
)
934 struct omap_mcbsp
*mcbsp
;
938 if (!omap_mcbsp_check_valid_id(id
)) {
939 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
943 mcbsp
= id_to_mcbsp_ptr(id
);
945 /* Reset transmitter */
947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
948 w
= MCBSP_READ_CACHE(mcbsp
, XCCR
);
949 w
|= (tx
? XDISABLE
: 0);
950 MCBSP_WRITE(mcbsp
, XCCR
, w
);
952 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
953 MCBSP_WRITE(mcbsp
, SPCR2
, w
& ~tx
);
957 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
958 w
= MCBSP_READ_CACHE(mcbsp
, RCCR
);
959 w
|= (rx
? RDISABLE
: 0);
960 MCBSP_WRITE(mcbsp
, RCCR
, w
);
962 w
= MCBSP_READ_CACHE(mcbsp
, SPCR1
);
963 MCBSP_WRITE(mcbsp
, SPCR1
, w
& ~rx
);
965 idle
= !((MCBSP_READ_CACHE(mcbsp
, SPCR2
) |
966 MCBSP_READ_CACHE(mcbsp
, SPCR1
)) & 1);
969 /* Reset the sample rate generator */
970 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
971 MCBSP_WRITE(mcbsp
, SPCR2
, w
& ~(1 << 6));
974 if (cpu_is_omap34xx())
977 EXPORT_SYMBOL(omap_mcbsp_stop
);
979 /* polled mcbsp i/o operations */
980 int omap_mcbsp_pollwrite(unsigned int id
, u16 buf
)
982 struct omap_mcbsp
*mcbsp
;
984 if (!omap_mcbsp_check_valid_id(id
)) {
985 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
989 mcbsp
= id_to_mcbsp_ptr(id
);
991 MCBSP_WRITE(mcbsp
, DXR1
, buf
);
992 /* if frame sync error - clear the error */
993 if (MCBSP_READ(mcbsp
, SPCR2
) & XSYNC_ERR
) {
995 MCBSP_WRITE(mcbsp
, SPCR2
, MCBSP_READ_CACHE(mcbsp
, SPCR2
));
999 /* wait for transmit confirmation */
1001 while (!(MCBSP_READ(mcbsp
, SPCR2
) & XRDY
)) {
1002 if (attemps
++ > 1000) {
1003 MCBSP_WRITE(mcbsp
, SPCR2
,
1004 MCBSP_READ_CACHE(mcbsp
, SPCR2
) &
1007 MCBSP_WRITE(mcbsp
, SPCR2
,
1008 MCBSP_READ_CACHE(mcbsp
, SPCR2
) |
1011 dev_err(mcbsp
->dev
, "Could not write to"
1012 " McBSP%d Register\n", mcbsp
->id
);
1020 EXPORT_SYMBOL(omap_mcbsp_pollwrite
);
1022 int omap_mcbsp_pollread(unsigned int id
, u16
*buf
)
1024 struct omap_mcbsp
*mcbsp
;
1026 if (!omap_mcbsp_check_valid_id(id
)) {
1027 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1030 mcbsp
= id_to_mcbsp_ptr(id
);
1032 /* if frame sync error - clear the error */
1033 if (MCBSP_READ(mcbsp
, SPCR1
) & RSYNC_ERR
) {
1035 MCBSP_WRITE(mcbsp
, SPCR1
, MCBSP_READ_CACHE(mcbsp
, SPCR1
));
1039 /* wait for recieve confirmation */
1041 while (!(MCBSP_READ(mcbsp
, SPCR1
) & RRDY
)) {
1042 if (attemps
++ > 1000) {
1043 MCBSP_WRITE(mcbsp
, SPCR1
,
1044 MCBSP_READ_CACHE(mcbsp
, SPCR1
) &
1047 MCBSP_WRITE(mcbsp
, SPCR1
,
1048 MCBSP_READ_CACHE(mcbsp
, SPCR1
) |
1051 dev_err(mcbsp
->dev
, "Could not read from"
1052 " McBSP%d Register\n", mcbsp
->id
);
1057 *buf
= MCBSP_READ(mcbsp
, DRR1
);
1061 EXPORT_SYMBOL(omap_mcbsp_pollread
);
1064 * IRQ based word transmission.
1066 void omap_mcbsp_xmit_word(unsigned int id
, u32 word
)
1068 struct omap_mcbsp
*mcbsp
;
1069 omap_mcbsp_word_length word_length
;
1071 if (!omap_mcbsp_check_valid_id(id
)) {
1072 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1076 mcbsp
= id_to_mcbsp_ptr(id
);
1077 word_length
= mcbsp
->tx_word_length
;
1079 wait_for_completion(&mcbsp
->tx_irq_completion
);
1081 if (word_length
> OMAP_MCBSP_WORD_16
)
1082 MCBSP_WRITE(mcbsp
, DXR2
, word
>> 16);
1083 MCBSP_WRITE(mcbsp
, DXR1
, word
& 0xffff);
1085 EXPORT_SYMBOL(omap_mcbsp_xmit_word
);
1087 u32
omap_mcbsp_recv_word(unsigned int id
)
1089 struct omap_mcbsp
*mcbsp
;
1090 u16 word_lsb
, word_msb
= 0;
1091 omap_mcbsp_word_length word_length
;
1093 if (!omap_mcbsp_check_valid_id(id
)) {
1094 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1097 mcbsp
= id_to_mcbsp_ptr(id
);
1099 word_length
= mcbsp
->rx_word_length
;
1101 wait_for_completion(&mcbsp
->rx_irq_completion
);
1103 if (word_length
> OMAP_MCBSP_WORD_16
)
1104 word_msb
= MCBSP_READ(mcbsp
, DRR2
);
1105 word_lsb
= MCBSP_READ(mcbsp
, DRR1
);
1107 return (word_lsb
| (word_msb
<< 16));
1109 EXPORT_SYMBOL(omap_mcbsp_recv_word
);
1111 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id
, u32 word
)
1113 struct omap_mcbsp
*mcbsp
;
1114 omap_mcbsp_word_length tx_word_length
;
1115 omap_mcbsp_word_length rx_word_length
;
1116 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
1118 if (!omap_mcbsp_check_valid_id(id
)) {
1119 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1122 mcbsp
= id_to_mcbsp_ptr(id
);
1123 tx_word_length
= mcbsp
->tx_word_length
;
1124 rx_word_length
= mcbsp
->rx_word_length
;
1126 if (tx_word_length
!= rx_word_length
)
1129 /* First we wait for the transmitter to be ready */
1130 spcr2
= MCBSP_READ(mcbsp
, SPCR2
);
1131 while (!(spcr2
& XRDY
)) {
1132 spcr2
= MCBSP_READ(mcbsp
, SPCR2
);
1133 if (attempts
++ > 1000) {
1134 /* We must reset the transmitter */
1135 MCBSP_WRITE(mcbsp
, SPCR2
,
1136 MCBSP_READ_CACHE(mcbsp
, SPCR2
) & (~XRST
));
1138 MCBSP_WRITE(mcbsp
, SPCR2
,
1139 MCBSP_READ_CACHE(mcbsp
, SPCR2
) | XRST
);
1141 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
1142 "ready\n", mcbsp
->id
);
1147 /* Now we can push the data */
1148 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
1149 MCBSP_WRITE(mcbsp
, DXR2
, word
>> 16);
1150 MCBSP_WRITE(mcbsp
, DXR1
, word
& 0xffff);
1152 /* We wait for the receiver to be ready */
1153 spcr1
= MCBSP_READ(mcbsp
, SPCR1
);
1154 while (!(spcr1
& RRDY
)) {
1155 spcr1
= MCBSP_READ(mcbsp
, SPCR1
);
1156 if (attempts
++ > 1000) {
1157 /* We must reset the receiver */
1158 MCBSP_WRITE(mcbsp
, SPCR1
,
1159 MCBSP_READ_CACHE(mcbsp
, SPCR1
) & (~RRST
));
1161 MCBSP_WRITE(mcbsp
, SPCR1
,
1162 MCBSP_READ_CACHE(mcbsp
, SPCR1
) | RRST
);
1164 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
1165 "ready\n", mcbsp
->id
);
1170 /* Receiver is ready, let's read the dummy data */
1171 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
1172 word_msb
= MCBSP_READ(mcbsp
, DRR2
);
1173 word_lsb
= MCBSP_READ(mcbsp
, DRR1
);
1177 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll
);
1179 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id
, u32
*word
)
1181 struct omap_mcbsp
*mcbsp
;
1183 omap_mcbsp_word_length tx_word_length
;
1184 omap_mcbsp_word_length rx_word_length
;
1185 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
1187 if (!omap_mcbsp_check_valid_id(id
)) {
1188 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1192 mcbsp
= id_to_mcbsp_ptr(id
);
1194 tx_word_length
= mcbsp
->tx_word_length
;
1195 rx_word_length
= mcbsp
->rx_word_length
;
1197 if (tx_word_length
!= rx_word_length
)
1200 /* First we wait for the transmitter to be ready */
1201 spcr2
= MCBSP_READ(mcbsp
, SPCR2
);
1202 while (!(spcr2
& XRDY
)) {
1203 spcr2
= MCBSP_READ(mcbsp
, SPCR2
);
1204 if (attempts
++ > 1000) {
1205 /* We must reset the transmitter */
1206 MCBSP_WRITE(mcbsp
, SPCR2
,
1207 MCBSP_READ_CACHE(mcbsp
, SPCR2
) & (~XRST
));
1209 MCBSP_WRITE(mcbsp
, SPCR2
,
1210 MCBSP_READ_CACHE(mcbsp
, SPCR2
) | XRST
);
1212 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
1213 "ready\n", mcbsp
->id
);
1218 /* We first need to enable the bus clock */
1219 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
1220 MCBSP_WRITE(mcbsp
, DXR2
, clock_word
>> 16);
1221 MCBSP_WRITE(mcbsp
, DXR1
, clock_word
& 0xffff);
1223 /* We wait for the receiver to be ready */
1224 spcr1
= MCBSP_READ(mcbsp
, SPCR1
);
1225 while (!(spcr1
& RRDY
)) {
1226 spcr1
= MCBSP_READ(mcbsp
, SPCR1
);
1227 if (attempts
++ > 1000) {
1228 /* We must reset the receiver */
1229 MCBSP_WRITE(mcbsp
, SPCR1
,
1230 MCBSP_READ_CACHE(mcbsp
, SPCR1
) & (~RRST
));
1232 MCBSP_WRITE(mcbsp
, SPCR1
,
1233 MCBSP_READ_CACHE(mcbsp
, SPCR1
) | RRST
);
1235 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
1236 "ready\n", mcbsp
->id
);
1241 /* Receiver is ready, there is something for us */
1242 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
1243 word_msb
= MCBSP_READ(mcbsp
, DRR2
);
1244 word_lsb
= MCBSP_READ(mcbsp
, DRR1
);
1246 word
[0] = (word_lsb
| (word_msb
<< 16));
1250 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll
);
1253 * Simple DMA based buffer rx/tx routines.
1254 * Nothing fancy, just a single buffer tx/rx through DMA.
1255 * The DMA resources are released once the transfer is done.
1256 * For anything fancier, you should use your own customized DMA
1257 * routines and callbacks.
1259 int omap_mcbsp_xmit_buffer(unsigned int id
, dma_addr_t buffer
,
1260 unsigned int length
)
1262 struct omap_mcbsp
*mcbsp
;
1268 if (!omap_mcbsp_check_valid_id(id
)) {
1269 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1272 mcbsp
= id_to_mcbsp_ptr(id
);
1274 if (omap_request_dma(mcbsp
->dma_tx_sync
, "McBSP TX",
1275 omap_mcbsp_tx_dma_callback
,
1278 dev_err(mcbsp
->dev
, " Unable to request DMA channel for "
1279 "McBSP%d TX. Trying IRQ based TX\n",
1283 mcbsp
->dma_tx_lch
= dma_tx_ch
;
1285 dev_err(mcbsp
->dev
, "McBSP%d TX DMA on channel %d\n", mcbsp
->id
,
1288 init_completion(&mcbsp
->tx_dma_completion
);
1290 if (cpu_class_is_omap1()) {
1291 src_port
= OMAP_DMA_PORT_TIPB
;
1292 dest_port
= OMAP_DMA_PORT_EMIFF
;
1294 if (cpu_class_is_omap2())
1295 sync_dev
= mcbsp
->dma_tx_sync
;
1297 omap_set_dma_transfer_params(mcbsp
->dma_tx_lch
,
1298 OMAP_DMA_DATA_TYPE_S16
,
1300 OMAP_DMA_SYNC_ELEMENT
,
1303 omap_set_dma_dest_params(mcbsp
->dma_tx_lch
,
1305 OMAP_DMA_AMODE_CONSTANT
,
1306 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DXR1
,
1309 omap_set_dma_src_params(mcbsp
->dma_tx_lch
,
1311 OMAP_DMA_AMODE_POST_INC
,
1315 omap_start_dma(mcbsp
->dma_tx_lch
);
1316 wait_for_completion(&mcbsp
->tx_dma_completion
);
1320 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer
);
1322 int omap_mcbsp_recv_buffer(unsigned int id
, dma_addr_t buffer
,
1323 unsigned int length
)
1325 struct omap_mcbsp
*mcbsp
;
1331 if (!omap_mcbsp_check_valid_id(id
)) {
1332 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1335 mcbsp
= id_to_mcbsp_ptr(id
);
1337 if (omap_request_dma(mcbsp
->dma_rx_sync
, "McBSP RX",
1338 omap_mcbsp_rx_dma_callback
,
1341 dev_err(mcbsp
->dev
, "Unable to request DMA channel for "
1342 "McBSP%d RX. Trying IRQ based RX\n",
1346 mcbsp
->dma_rx_lch
= dma_rx_ch
;
1348 dev_err(mcbsp
->dev
, "McBSP%d RX DMA on channel %d\n", mcbsp
->id
,
1351 init_completion(&mcbsp
->rx_dma_completion
);
1353 if (cpu_class_is_omap1()) {
1354 src_port
= OMAP_DMA_PORT_TIPB
;
1355 dest_port
= OMAP_DMA_PORT_EMIFF
;
1357 if (cpu_class_is_omap2())
1358 sync_dev
= mcbsp
->dma_rx_sync
;
1360 omap_set_dma_transfer_params(mcbsp
->dma_rx_lch
,
1361 OMAP_DMA_DATA_TYPE_S16
,
1363 OMAP_DMA_SYNC_ELEMENT
,
1366 omap_set_dma_src_params(mcbsp
->dma_rx_lch
,
1368 OMAP_DMA_AMODE_CONSTANT
,
1369 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DRR1
,
1372 omap_set_dma_dest_params(mcbsp
->dma_rx_lch
,
1374 OMAP_DMA_AMODE_POST_INC
,
1378 omap_start_dma(mcbsp
->dma_rx_lch
);
1379 wait_for_completion(&mcbsp
->rx_dma_completion
);
1383 EXPORT_SYMBOL(omap_mcbsp_recv_buffer
);
1387 * Since SPI setup is much simpler than the generic McBSP one,
1388 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1389 * Once this is done, you can call omap_mcbsp_start().
1391 void omap_mcbsp_set_spi_mode(unsigned int id
,
1392 const struct omap_mcbsp_spi_cfg
*spi_cfg
)
1394 struct omap_mcbsp
*mcbsp
;
1395 struct omap_mcbsp_reg_cfg mcbsp_cfg
;
1397 if (!omap_mcbsp_check_valid_id(id
)) {
1398 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1401 mcbsp
= id_to_mcbsp_ptr(id
);
1403 memset(&mcbsp_cfg
, 0, sizeof(struct omap_mcbsp_reg_cfg
));
1405 /* SPI has only one frame */
1406 mcbsp_cfg
.rcr1
|= (RWDLEN1(spi_cfg
->word_length
) | RFRLEN1(0));
1407 mcbsp_cfg
.xcr1
|= (XWDLEN1(spi_cfg
->word_length
) | XFRLEN1(0));
1409 /* Clock stop mode */
1410 if (spi_cfg
->clk_stp_mode
== OMAP_MCBSP_CLK_STP_MODE_NO_DELAY
)
1411 mcbsp_cfg
.spcr1
|= (1 << 12);
1413 mcbsp_cfg
.spcr1
|= (3 << 11);
1415 /* Set clock parities */
1416 if (spi_cfg
->rx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
1417 mcbsp_cfg
.pcr0
|= CLKRP
;
1419 mcbsp_cfg
.pcr0
&= ~CLKRP
;
1421 if (spi_cfg
->tx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
1422 mcbsp_cfg
.pcr0
&= ~CLKXP
;
1424 mcbsp_cfg
.pcr0
|= CLKXP
;
1426 /* Set SCLKME to 0 and CLKSM to 1 */
1427 mcbsp_cfg
.pcr0
&= ~SCLKME
;
1428 mcbsp_cfg
.srgr2
|= CLKSM
;
1431 if (spi_cfg
->fsx_polarity
== OMAP_MCBSP_FS_ACTIVE_HIGH
)
1432 mcbsp_cfg
.pcr0
&= ~FSXP
;
1434 mcbsp_cfg
.pcr0
|= FSXP
;
1436 if (spi_cfg
->spi_mode
== OMAP_MCBSP_SPI_MASTER
) {
1437 mcbsp_cfg
.pcr0
|= CLKXM
;
1438 mcbsp_cfg
.srgr1
|= CLKGDV(spi_cfg
->clk_div
- 1);
1439 mcbsp_cfg
.pcr0
|= FSXM
;
1440 mcbsp_cfg
.srgr2
&= ~FSGM
;
1441 mcbsp_cfg
.xcr2
|= XDATDLY(1);
1442 mcbsp_cfg
.rcr2
|= RDATDLY(1);
1444 mcbsp_cfg
.pcr0
&= ~CLKXM
;
1445 mcbsp_cfg
.srgr1
|= CLKGDV(1);
1446 mcbsp_cfg
.pcr0
&= ~FSXM
;
1447 mcbsp_cfg
.xcr2
&= ~XDATDLY(3);
1448 mcbsp_cfg
.rcr2
&= ~RDATDLY(3);
1451 mcbsp_cfg
.xcr2
&= ~XPHASE
;
1452 mcbsp_cfg
.rcr2
&= ~RPHASE
;
1454 omap_mcbsp_config(id
, &mcbsp_cfg
);
1456 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode
);
1458 #ifdef CONFIG_ARCH_OMAP3
1459 #define max_thres(m) (mcbsp->pdata->buffer_size)
1460 #define valid_threshold(m, val) ((val) <= max_thres(m))
1461 #define THRESHOLD_PROP_BUILDER(prop) \
1462 static ssize_t prop##_show(struct device *dev, \
1463 struct device_attribute *attr, char *buf) \
1465 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1467 return sprintf(buf, "%u\n", mcbsp->prop); \
1470 static ssize_t prop##_store(struct device *dev, \
1471 struct device_attribute *attr, \
1472 const char *buf, size_t size) \
1474 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1475 unsigned long val; \
1478 status = strict_strtoul(buf, 0, &val); \
1482 if (!valid_threshold(mcbsp, val)) \
1485 mcbsp->prop = val; \
1489 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1491 THRESHOLD_PROP_BUILDER(max_tx_thres
);
1492 THRESHOLD_PROP_BUILDER(max_rx_thres
);
1494 static const char *dma_op_modes
[] = {
1495 "element", "threshold", "frame",
1498 static ssize_t
dma_op_mode_show(struct device
*dev
,
1499 struct device_attribute
*attr
, char *buf
)
1501 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1502 int dma_op_mode
, i
= 0;
1504 const char * const *s
;
1506 dma_op_mode
= mcbsp
->dma_op_mode
;
1508 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++) {
1509 if (dma_op_mode
== i
)
1510 len
+= sprintf(buf
+ len
, "[%s] ", *s
);
1512 len
+= sprintf(buf
+ len
, "%s ", *s
);
1514 len
+= sprintf(buf
+ len
, "\n");
1519 static ssize_t
dma_op_mode_store(struct device
*dev
,
1520 struct device_attribute
*attr
,
1521 const char *buf
, size_t size
)
1523 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1524 const char * const *s
;
1527 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++)
1528 if (sysfs_streq(buf
, *s
))
1531 if (i
== ARRAY_SIZE(dma_op_modes
))
1534 spin_lock_irq(&mcbsp
->lock
);
1539 mcbsp
->dma_op_mode
= i
;
1542 spin_unlock_irq(&mcbsp
->lock
);
1547 static DEVICE_ATTR(dma_op_mode
, 0644, dma_op_mode_show
, dma_op_mode_store
);
1549 static ssize_t
st_taps_show(struct device
*dev
,
1550 struct device_attribute
*attr
, char *buf
)
1552 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1553 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1557 spin_lock_irq(&mcbsp
->lock
);
1558 for (i
= 0; i
< st_data
->nr_taps
; i
++)
1559 status
+= sprintf(&buf
[status
], (i
? ", %d" : "%d"),
1562 status
+= sprintf(&buf
[status
], "\n");
1563 spin_unlock_irq(&mcbsp
->lock
);
1568 static ssize_t
st_taps_store(struct device
*dev
,
1569 struct device_attribute
*attr
,
1570 const char *buf
, size_t size
)
1572 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1573 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1574 int val
, tmp
, status
, i
= 0;
1576 spin_lock_irq(&mcbsp
->lock
);
1577 memset(st_data
->taps
, 0, sizeof(st_data
->taps
));
1578 st_data
->nr_taps
= 0;
1581 status
= sscanf(buf
, "%d%n", &val
, &tmp
);
1582 if (status
< 0 || status
== 0) {
1586 if (val
< -32768 || val
> 32767) {
1590 st_data
->taps
[i
++] = val
;
1597 st_data
->nr_taps
= i
;
1600 spin_unlock_irq(&mcbsp
->lock
);
1605 static DEVICE_ATTR(st_taps
, 0644, st_taps_show
, st_taps_store
);
1607 static const struct attribute
*additional_attrs
[] = {
1608 &dev_attr_max_tx_thres
.attr
,
1609 &dev_attr_max_rx_thres
.attr
,
1610 &dev_attr_dma_op_mode
.attr
,
1614 static const struct attribute_group additional_attr_group
= {
1615 .attrs
= (struct attribute
**)additional_attrs
,
1618 static inline int __devinit
omap_additional_add(struct device
*dev
)
1620 return sysfs_create_group(&dev
->kobj
, &additional_attr_group
);
1623 static inline void __devexit
omap_additional_remove(struct device
*dev
)
1625 sysfs_remove_group(&dev
->kobj
, &additional_attr_group
);
1628 static const struct attribute
*sidetone_attrs
[] = {
1629 &dev_attr_st_taps
.attr
,
1633 static const struct attribute_group sidetone_attr_group
= {
1634 .attrs
= (struct attribute
**)sidetone_attrs
,
1637 int __devinit
omap_st_add(struct omap_mcbsp
*mcbsp
)
1639 struct omap_mcbsp_platform_data
*pdata
= mcbsp
->pdata
;
1640 struct omap_mcbsp_st_data
*st_data
;
1643 st_data
= kzalloc(sizeof(*mcbsp
->st_data
), GFP_KERNEL
);
1649 st_data
->io_base_st
= ioremap(pdata
->phys_base_st
, SZ_4K
);
1650 if (!st_data
->io_base_st
) {
1655 err
= sysfs_create_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
1659 mcbsp
->st_data
= st_data
;
1663 iounmap(st_data
->io_base_st
);
1671 static void __devexit
omap_st_remove(struct omap_mcbsp
*mcbsp
)
1673 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1676 sysfs_remove_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
1677 iounmap(st_data
->io_base_st
);
1682 static inline void __devinit
omap34xx_device_init(struct omap_mcbsp
*mcbsp
)
1684 mcbsp
->dma_op_mode
= MCBSP_DMA_MODE_ELEMENT
;
1685 if (cpu_is_omap34xx()) {
1686 mcbsp
->max_tx_thres
= max_thres(mcbsp
);
1687 mcbsp
->max_rx_thres
= max_thres(mcbsp
);
1689 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1690 * for mcbsp2 instances.
1692 if (omap_additional_add(mcbsp
->dev
))
1693 dev_warn(mcbsp
->dev
,
1694 "Unable to create additional controls\n");
1696 if (mcbsp
->id
== 2 || mcbsp
->id
== 3)
1697 if (omap_st_add(mcbsp
))
1698 dev_warn(mcbsp
->dev
,
1699 "Unable to create sidetone controls\n");
1702 mcbsp
->max_tx_thres
= -EINVAL
;
1703 mcbsp
->max_rx_thres
= -EINVAL
;
1707 static inline void __devexit
omap34xx_device_exit(struct omap_mcbsp
*mcbsp
)
1709 if (cpu_is_omap34xx()) {
1710 omap_additional_remove(mcbsp
->dev
);
1712 if (mcbsp
->id
== 2 || mcbsp
->id
== 3)
1713 omap_st_remove(mcbsp
);
1717 static inline void __devinit
omap34xx_device_init(struct omap_mcbsp
*mcbsp
) {}
1718 static inline void __devexit
omap34xx_device_exit(struct omap_mcbsp
*mcbsp
) {}
1719 #endif /* CONFIG_ARCH_OMAP3 */
1722 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1723 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1725 static int __devinit
omap_mcbsp_probe(struct platform_device
*pdev
)
1727 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
1728 struct omap_mcbsp
*mcbsp
;
1729 int id
= pdev
->id
- 1;
1733 dev_err(&pdev
->dev
, "McBSP device initialized without"
1739 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
1741 if (id
>= omap_mcbsp_count
) {
1742 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
1747 mcbsp
= kzalloc(sizeof(struct omap_mcbsp
), GFP_KERNEL
);
1753 spin_lock_init(&mcbsp
->lock
);
1756 mcbsp
->dma_tx_lch
= -1;
1757 mcbsp
->dma_rx_lch
= -1;
1759 mcbsp
->phys_base
= pdata
->phys_base
;
1760 mcbsp
->io_base
= ioremap(pdata
->phys_base
, SZ_4K
);
1761 if (!mcbsp
->io_base
) {
1766 /* Default I/O is IRQ based */
1767 mcbsp
->io_type
= OMAP_MCBSP_IRQ_IO
;
1768 mcbsp
->tx_irq
= pdata
->tx_irq
;
1769 mcbsp
->rx_irq
= pdata
->rx_irq
;
1770 mcbsp
->dma_rx_sync
= pdata
->dma_rx_sync
;
1771 mcbsp
->dma_tx_sync
= pdata
->dma_tx_sync
;
1773 mcbsp
->iclk
= clk_get(&pdev
->dev
, "ick");
1774 if (IS_ERR(mcbsp
->iclk
)) {
1775 ret
= PTR_ERR(mcbsp
->iclk
);
1776 dev_err(&pdev
->dev
, "unable to get ick: %d\n", ret
);
1780 mcbsp
->fclk
= clk_get(&pdev
->dev
, "fck");
1781 if (IS_ERR(mcbsp
->fclk
)) {
1782 ret
= PTR_ERR(mcbsp
->fclk
);
1783 dev_err(&pdev
->dev
, "unable to get fck: %d\n", ret
);
1787 mcbsp
->pdata
= pdata
;
1788 mcbsp
->dev
= &pdev
->dev
;
1789 mcbsp_ptr
[id
] = mcbsp
;
1790 platform_set_drvdata(pdev
, mcbsp
);
1792 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1793 omap34xx_device_init(mcbsp
);
1798 clk_put(mcbsp
->iclk
);
1800 iounmap(mcbsp
->io_base
);
1807 static int __devexit
omap_mcbsp_remove(struct platform_device
*pdev
)
1809 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
1811 platform_set_drvdata(pdev
, NULL
);
1814 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
1815 mcbsp
->pdata
->ops
->free
)
1816 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
1818 omap34xx_device_exit(mcbsp
);
1820 clk_disable(mcbsp
->fclk
);
1821 clk_disable(mcbsp
->iclk
);
1822 clk_put(mcbsp
->fclk
);
1823 clk_put(mcbsp
->iclk
);
1825 iounmap(mcbsp
->io_base
);
1836 static struct platform_driver omap_mcbsp_driver
= {
1837 .probe
= omap_mcbsp_probe
,
1838 .remove
= __devexit_p(omap_mcbsp_remove
),
1840 .name
= "omap-mcbsp",
1844 int __init
omap_mcbsp_init(void)
1846 /* Register the McBSP driver */
1847 return platform_driver_register(&omap_mcbsp_driver
);