arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31
  32 #include "sram.h"
  33
  34 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
  35 #include "../mach-omap2/iomap.h"
  36 #include "../mach-omap2/prm2xxx_3xxx.h"
  37 #include "../mach-omap2/sdrc.h"
  38
  39 #define OMAP1_SRAM_PA           0x20000000
  40 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  41 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  42 #ifdef CONFIG_OMAP4_ERRATA_I688
  43 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  44 #else
  45 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  46 #endif
  47
  48 #if defined(CONFIG_ARCH_OMAP2PLUS)
  49 #define SRAM_BOOTLOADER_SZ      0x00
  50 #else
  51 #define SRAM_BOOTLOADER_SZ      0x80
  52 #endif
  53
  54 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  55 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  56 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  57
  58 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  59 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  60 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  61 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  62 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  63
  64 #define GP_DEVICE               0x300
  65
  66 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  67
  68 static unsigned long omap_sram_start;
  69 static void __iomem *omap_sram_base;
  70 static unsigned long omap_sram_size;
  71 static void __iomem *omap_sram_ceil;
  72
  73 /*
  74  * Depending on the target RAMFS firewall setup, the public usable amount of
  75  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  76  * device allows ARM11 but not other initiators for full size. This
  77  * functionality seems ok until some nice security API happens.
  78  */
  79 static int is_sram_locked(void)
  80 {
  81         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  82                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  83                 if (cpu_is_omap242x()) {
  84                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  85                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  86                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  87                 }
  88                 if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
  89                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  90                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  92                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  93                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  94                 }
  95                 return 0;
  96         } else
  97                 return 1; /* assume locked with no PPA or security driver */
  98 }
  99
 100 /*
 101  * The amount of SRAM depends on the core type.
 102  * Note that we cannot try to test for SRAM here because writes
 103  * to secure SRAM will hang the system. Also the SRAM is not
 104  * yet mapped at this point.
 105  */
 106 static void __init omap_detect_sram(void)
 107 {
 108         if (cpu_class_is_omap2()) {
 109                 if (is_sram_locked()) {
 110                         if (cpu_is_omap34xx()) {
 111                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 112                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 113                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 114                                         omap_sram_size = 0x7000; /* 28K */
 115                                 } else {
 116                                         omap_sram_size = 0x8000; /* 32K */
 117                                 }
 118                         } else if (cpu_is_omap44xx()) {
 119                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 120                                 omap_sram_size = 0xa000; /* 40K */
 121                         } else {
 122                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 123                                 omap_sram_size = 0x800; /* 2K */
 124                         }
 125                 } else {
 126                         if (cpu_is_am33xx()) {
 127                                 omap_sram_start = AM33XX_SRAM_PA;
 128                                 omap_sram_size = 0x10000; /* 64K */
 129                         } else if (cpu_is_omap34xx()) {
 130                                 omap_sram_start = OMAP3_SRAM_PA;
 131                                 omap_sram_size = 0x10000; /* 64K */
 132                         } else if (cpu_is_omap44xx()) {
 133                                 omap_sram_start = OMAP4_SRAM_PA;
 134                                 omap_sram_size = 0xe000; /* 56K */
 135                         } else {
 136                                 omap_sram_start = OMAP2_SRAM_PA;
 137                                 if (cpu_is_omap242x())
 138                                         omap_sram_size = 0xa0000; /* 640K */
 139                                 else if (cpu_is_omap243x())
 140                                         omap_sram_size = 0x10000; /* 64K */
 141                         }
 142                 }
 143         } else {
 144                 omap_sram_start = OMAP1_SRAM_PA;
 145
 146                 if (cpu_is_omap7xx())
 147                         omap_sram_size = 0x32000;       /* 200K */
 148                 else if (cpu_is_omap15xx())
 149                         omap_sram_size = 0x30000;       /* 192K */
 150                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
 151                                 cpu_is_omap1621() || cpu_is_omap1710())
 152                         omap_sram_size = 0x4000;        /* 16K */
 153                 else {
 154                         pr_err("Could not detect SRAM size\n");
 155                         omap_sram_size = 0x4000;
 156                 }
 157         }
 158 }
 159
 160 /*
 161  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 162  */
 163 static void __init omap_map_sram(void)
 164 {
 165         int cached = 1;
 166
 167         if (omap_sram_size == 0)
 168                 return;
 169
 170 #ifdef CONFIG_OMAP4_ERRATA_I688
 171                 omap_sram_start += PAGE_SIZE;
 172                 omap_sram_size -= SZ_16K;
 173 #endif
 174         if (cpu_is_omap34xx()) {
 175                 /*
 176                  * SRAM must be marked as non-cached on OMAP3 since the
 177                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 178                  * SDRAM controller disabled, and if it is marked cached,
 179                  * the ARM may attempt to write cache lines back to SDRAM
 180                  * which will cause the system to hang.
 181                  */
 182                 cached = 0;
 183         }
 184
 185         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 186         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 187                                                 cached);
 188         if (!omap_sram_base) {
 189                 pr_err("SRAM: Could not map\n");
 190                 return;
 191         }
 192
 193         omap_sram_ceil = omap_sram_base + omap_sram_size;
 194
 195         /*
 196          * Looks like we need to preserve some bootloader code at the
 197          * beginning of SRAM for jumping to flash for reboot to work...
 198          */
 199         memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 200                   omap_sram_size - SRAM_BOOTLOADER_SZ);
 201 }
 202
 203 /*
 204  * Memory allocator for SRAM: calculates the new ceiling address
 205  * for pushing a function using the fncpy API.
 206  *
 207  * Note that fncpy requires the returned address to be aligned
 208  * to an 8-byte boundary.
 209  */
 210 void *omap_sram_push_address(unsigned long size)
 211 {
 212         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 213
 214         available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
 215
 216         if (size > available) {
 217                 pr_err("Not enough space in SRAM\n");
 218                 return NULL;
 219         }
 220
 221         new_ceil -= size;
 222         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 223         omap_sram_ceil = IOMEM(new_ceil);
 224
 225         return (void *)omap_sram_ceil;
 226 }
 227
 228 #ifdef CONFIG_ARCH_OMAP1
 229
 230 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 231
 232 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 233 {
 234         BUG_ON(!_omap_sram_reprogram_clock);
 235         /* On 730, bit 13 must always be 1 */
 236         if (cpu_is_omap7xx())
 237                 ckctl |= 0x2000;
 238         _omap_sram_reprogram_clock(dpllctl, ckctl);
 239 }
 240
 241 static int __init omap1_sram_init(void)
 242 {
 243         _omap_sram_reprogram_clock =
 244                         omap_sram_push(omap1_sram_reprogram_clock,
 245                                         omap1_sram_reprogram_clock_sz);
 246
 247         return 0;
 248 }
 249
 250 #else
 251 #define omap1_sram_init()       do {} while (0)
 252 #endif
 253
 254 #if defined(CONFIG_ARCH_OMAP2)
 255
 256 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 257                               u32 base_cs, u32 force_unlock);
 258
 259 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 260                    u32 base_cs, u32 force_unlock)
 261 {
 262         BUG_ON(!_omap2_sram_ddr_init);
 263         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 264                              base_cs, force_unlock);
 265 }
 266
 267 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 268                                           u32 mem_type);
 269
 270 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 271 {
 272         BUG_ON(!_omap2_sram_reprogram_sdrc);
 273         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 274 }
 275
 276 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 277
 278 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 279 {
 280         BUG_ON(!_omap2_set_prcm);
 281         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 282 }
 283 #endif
 284
 285 #ifdef CONFIG_SOC_OMAP2420
 286 static int __init omap242x_sram_init(void)
 287 {
 288         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 289                                         omap242x_sram_ddr_init_sz);
 290
 291         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 292                                             omap242x_sram_reprogram_sdrc_sz);
 293
 294         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 295                                          omap242x_sram_set_prcm_sz);
 296
 297         return 0;
 298 }
 299 #else
 300 static inline int omap242x_sram_init(void)
 301 {
 302         return 0;
 303 }
 304 #endif
 305
 306 #ifdef CONFIG_SOC_OMAP2430
 307 static int __init omap243x_sram_init(void)
 308 {
 309         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 310                                         omap243x_sram_ddr_init_sz);
 311
 312         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 313                                             omap243x_sram_reprogram_sdrc_sz);
 314
 315         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 316                                          omap243x_sram_set_prcm_sz);
 317
 318         return 0;
 319 }
 320 #else
 321 static inline int omap243x_sram_init(void)
 322 {
 323         return 0;
 324 }
 325 #endif
 326
 327 #ifdef CONFIG_ARCH_OMAP3
 328
 329 static u32 (*_omap3_sram_configure_core_dpll)(
 330                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 331                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 332                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 333                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 334                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 335
 336 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 337                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 338                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 339                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 340                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 341 {
 342         BUG_ON(!_omap3_sram_configure_core_dpll);
 343         return _omap3_sram_configure_core_dpll(
 344                         m2, unlock_dll, f, inc,
 345                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 346                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 347                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 348                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 349 }
 350
 351 void omap3_sram_restore_context(void)
 352 {
 353         omap_sram_ceil = omap_sram_base + omap_sram_size;
 354
 355         _omap3_sram_configure_core_dpll =
 356                 omap_sram_push(omap3_sram_configure_core_dpll,
 357                                omap3_sram_configure_core_dpll_sz);
 358         omap_push_sram_idle();
 359 }
 360
 361 static inline int omap34xx_sram_init(void)
 362 {
 363         omap3_sram_restore_context();
 364         return 0;
 365 }
 366 #else
 367 static inline int omap34xx_sram_init(void)
 368 {
 369         return 0;
 370 }
 371 #endif /* CONFIG_ARCH_OMAP3 */
 372
 373 static inline int am33xx_sram_init(void)
 374 {
 375         return 0;
 376 }
 377
 378 int __init omap_sram_init(void)
 379 {
 380         omap_detect_sram();
 381         omap_map_sram();
 382
 383         if (!(cpu_class_is_omap2()))
 384                 omap1_sram_init();
 385         else if (cpu_is_omap242x())
 386                 omap242x_sram_init();
 387         else if (cpu_is_omap2430())
 388                 omap243x_sram_init();
 389         else if (cpu_is_am33xx())
 390                 am33xx_sram_init();
 391         else if (cpu_is_omap34xx())
 392                 omap34xx_sram_init();
 393
 394         return 0;
 395 }