2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
24 #include <asm/cacheflush.h>
26 #include <asm/mach/map.h>
32 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
33 #include "../mach-omap2/iomap.h"
34 #include "../mach-omap2/prm2xxx_3xxx.h"
35 #include "../mach-omap2/sdrc.h"
37 #define OMAP1_SRAM_PA 0x20000000
38 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
39 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
40 #ifdef CONFIG_OMAP4_ERRATA_I688
41 #define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
43 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
45 #define OMAP5_SRAM_PA 0x40300000
47 #if defined(CONFIG_ARCH_OMAP2PLUS)
48 #define SRAM_BOOTLOADER_SZ 0x00
50 #define SRAM_BOOTLOADER_SZ 0x80
53 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
54 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
55 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
57 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
58 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
59 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
60 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
61 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
63 #define GP_DEVICE 0x300
65 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
67 static unsigned long omap_sram_start
;
68 static void __iomem
*omap_sram_base
;
69 static unsigned long omap_sram_skip
;
70 static unsigned long omap_sram_size
;
71 static void __iomem
*omap_sram_ceil
;
74 * Depending on the target RAMFS firewall setup, the public usable amount of
75 * SRAM varies. The default accessible size for all device types is 2k. A GP
76 * device allows ARM11 but not other initiators for full size. This
77 * functionality seems ok until some nice security API happens.
79 static int is_sram_locked(void)
81 if (OMAP2_DEVICE_TYPE_GP
== omap_type()) {
82 /* RAMFW: R/W access to all initiators for all qualifier sets */
83 if (cpu_is_omap242x()) {
84 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0
); /* all q-vects */
85 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0
); /* all i-read */
86 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0
); /* all i-write */
88 if (cpu_is_omap34xx()) {
89 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0
); /* all q-vects */
90 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0
); /* all i-read */
91 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0
); /* all i-write */
92 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2
);
93 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0
);
97 return 1; /* assume locked with no PPA or security driver */
101 * The amount of SRAM depends on the core type.
102 * Note that we cannot try to test for SRAM here because writes
103 * to secure SRAM will hang the system. Also the SRAM is not
104 * yet mapped at this point.
106 static void __init
omap_detect_sram(void)
108 omap_sram_skip
= SRAM_BOOTLOADER_SZ
;
109 if (cpu_class_is_omap2()) {
110 if (is_sram_locked()) {
111 if (cpu_is_omap34xx()) {
112 omap_sram_start
= OMAP3_SRAM_PUB_PA
;
113 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU
) ||
114 (omap_type() == OMAP2_DEVICE_TYPE_SEC
)) {
115 omap_sram_size
= 0x7000; /* 28K */
116 omap_sram_skip
+= SZ_16K
;
118 omap_sram_size
= 0x8000; /* 32K */
120 } else if (cpu_is_omap44xx()) {
121 omap_sram_start
= OMAP4_SRAM_PUB_PA
;
122 omap_sram_size
= 0xa000; /* 40K */
123 } else if (soc_is_omap54xx()) {
124 omap_sram_start
= OMAP5_SRAM_PA
;
125 omap_sram_size
= SZ_128K
; /* 128KB */
127 omap_sram_start
= OMAP2_SRAM_PUB_PA
;
128 omap_sram_size
= 0x800; /* 2K */
131 if (soc_is_am33xx()) {
132 omap_sram_start
= AM33XX_SRAM_PA
;
133 omap_sram_size
= 0x10000; /* 64K */
134 } else if (cpu_is_omap34xx()) {
135 omap_sram_start
= OMAP3_SRAM_PA
;
136 omap_sram_size
= 0x10000; /* 64K */
137 } else if (cpu_is_omap44xx()) {
138 omap_sram_start
= OMAP4_SRAM_PA
;
139 omap_sram_size
= 0xe000; /* 56K */
140 } else if (soc_is_omap54xx()) {
141 omap_sram_start
= OMAP5_SRAM_PA
;
142 omap_sram_size
= SZ_128K
; /* 128KB */
144 omap_sram_start
= OMAP2_SRAM_PA
;
145 if (cpu_is_omap242x())
146 omap_sram_size
= 0xa0000; /* 640K */
147 else if (cpu_is_omap243x())
148 omap_sram_size
= 0x10000; /* 64K */
152 omap_sram_start
= OMAP1_SRAM_PA
;
154 if (cpu_is_omap7xx())
155 omap_sram_size
= 0x32000; /* 200K */
156 else if (cpu_is_omap15xx())
157 omap_sram_size
= 0x30000; /* 192K */
158 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
159 cpu_is_omap1621() || cpu_is_omap1710())
160 omap_sram_size
= 0x4000; /* 16K */
162 pr_err("Could not detect SRAM size\n");
163 omap_sram_size
= 0x4000;
169 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
171 static void __init
omap_map_sram(void)
175 if (omap_sram_size
== 0)
178 #ifdef CONFIG_OMAP4_ERRATA_I688
179 if (cpu_is_omap44xx()) {
180 omap_sram_start
+= PAGE_SIZE
;
181 omap_sram_size
-= SZ_16K
;
184 if (cpu_is_omap34xx()) {
186 * SRAM must be marked as non-cached on OMAP3 since the
187 * CORE DPLL M2 divider change code (in SRAM) runs with the
188 * SDRAM controller disabled, and if it is marked cached,
189 * the ARM may attempt to write cache lines back to SDRAM
190 * which will cause the system to hang.
195 omap_sram_start
= ROUND_DOWN(omap_sram_start
, PAGE_SIZE
);
196 omap_sram_base
= __arm_ioremap_exec(omap_sram_start
, omap_sram_size
,
198 if (!omap_sram_base
) {
199 pr_err("SRAM: Could not map\n");
203 omap_sram_ceil
= omap_sram_base
+ omap_sram_size
;
206 * Looks like we need to preserve some bootloader code at the
207 * beginning of SRAM for jumping to flash for reboot to work...
209 memset_io(omap_sram_base
+ omap_sram_skip
, 0,
210 omap_sram_size
- omap_sram_skip
);
214 * Memory allocator for SRAM: calculates the new ceiling address
215 * for pushing a function using the fncpy API.
217 * Note that fncpy requires the returned address to be aligned
218 * to an 8-byte boundary.
220 void *omap_sram_push_address(unsigned long size
)
222 unsigned long available
, new_ceil
= (unsigned long)omap_sram_ceil
;
224 available
= omap_sram_ceil
- (omap_sram_base
+ omap_sram_skip
);
226 if (size
> available
) {
227 pr_err("Not enough space in SRAM\n");
232 new_ceil
= ROUND_DOWN(new_ceil
, FNCPY_ALIGN
);
233 omap_sram_ceil
= IOMEM(new_ceil
);
235 return (void *)omap_sram_ceil
;
238 #ifdef CONFIG_ARCH_OMAP1
240 static void (*_omap_sram_reprogram_clock
)(u32 dpllctl
, u32 ckctl
);
242 void omap_sram_reprogram_clock(u32 dpllctl
, u32 ckctl
)
244 BUG_ON(!_omap_sram_reprogram_clock
);
245 /* On 730, bit 13 must always be 1 */
246 if (cpu_is_omap7xx())
248 _omap_sram_reprogram_clock(dpllctl
, ckctl
);
251 static int __init
omap1_sram_init(void)
253 _omap_sram_reprogram_clock
=
254 omap_sram_push(omap1_sram_reprogram_clock
,
255 omap1_sram_reprogram_clock_sz
);
261 #define omap1_sram_init() do {} while (0)
264 #if defined(CONFIG_ARCH_OMAP2)
266 static void (*_omap2_sram_ddr_init
)(u32
*slow_dll_ctrl
, u32 fast_dll_ctrl
,
267 u32 base_cs
, u32 force_unlock
);
269 void omap2_sram_ddr_init(u32
*slow_dll_ctrl
, u32 fast_dll_ctrl
,
270 u32 base_cs
, u32 force_unlock
)
272 BUG_ON(!_omap2_sram_ddr_init
);
273 _omap2_sram_ddr_init(slow_dll_ctrl
, fast_dll_ctrl
,
274 base_cs
, force_unlock
);
277 static void (*_omap2_sram_reprogram_sdrc
)(u32 perf_level
, u32 dll_val
,
280 void omap2_sram_reprogram_sdrc(u32 perf_level
, u32 dll_val
, u32 mem_type
)
282 BUG_ON(!_omap2_sram_reprogram_sdrc
);
283 _omap2_sram_reprogram_sdrc(perf_level
, dll_val
, mem_type
);
286 static u32 (*_omap2_set_prcm
)(u32 dpll_ctrl_val
, u32 sdrc_rfr_val
, int bypass
);
288 u32
omap2_set_prcm(u32 dpll_ctrl_val
, u32 sdrc_rfr_val
, int bypass
)
290 BUG_ON(!_omap2_set_prcm
);
291 return _omap2_set_prcm(dpll_ctrl_val
, sdrc_rfr_val
, bypass
);
295 #ifdef CONFIG_SOC_OMAP2420
296 static int __init
omap242x_sram_init(void)
298 _omap2_sram_ddr_init
= omap_sram_push(omap242x_sram_ddr_init
,
299 omap242x_sram_ddr_init_sz
);
301 _omap2_sram_reprogram_sdrc
= omap_sram_push(omap242x_sram_reprogram_sdrc
,
302 omap242x_sram_reprogram_sdrc_sz
);
304 _omap2_set_prcm
= omap_sram_push(omap242x_sram_set_prcm
,
305 omap242x_sram_set_prcm_sz
);
310 static inline int omap242x_sram_init(void)
316 #ifdef CONFIG_SOC_OMAP2430
317 static int __init
omap243x_sram_init(void)
319 _omap2_sram_ddr_init
= omap_sram_push(omap243x_sram_ddr_init
,
320 omap243x_sram_ddr_init_sz
);
322 _omap2_sram_reprogram_sdrc
= omap_sram_push(omap243x_sram_reprogram_sdrc
,
323 omap243x_sram_reprogram_sdrc_sz
);
325 _omap2_set_prcm
= omap_sram_push(omap243x_sram_set_prcm
,
326 omap243x_sram_set_prcm_sz
);
331 static inline int omap243x_sram_init(void)
337 #ifdef CONFIG_ARCH_OMAP3
339 static u32 (*_omap3_sram_configure_core_dpll
)(
340 u32 m2
, u32 unlock_dll
, u32 f
, u32 inc
,
341 u32 sdrc_rfr_ctrl_0
, u32 sdrc_actim_ctrl_a_0
,
342 u32 sdrc_actim_ctrl_b_0
, u32 sdrc_mr_0
,
343 u32 sdrc_rfr_ctrl_1
, u32 sdrc_actim_ctrl_a_1
,
344 u32 sdrc_actim_ctrl_b_1
, u32 sdrc_mr_1
);
346 u32
omap3_configure_core_dpll(u32 m2
, u32 unlock_dll
, u32 f
, u32 inc
,
347 u32 sdrc_rfr_ctrl_0
, u32 sdrc_actim_ctrl_a_0
,
348 u32 sdrc_actim_ctrl_b_0
, u32 sdrc_mr_0
,
349 u32 sdrc_rfr_ctrl_1
, u32 sdrc_actim_ctrl_a_1
,
350 u32 sdrc_actim_ctrl_b_1
, u32 sdrc_mr_1
)
352 BUG_ON(!_omap3_sram_configure_core_dpll
);
353 return _omap3_sram_configure_core_dpll(
354 m2
, unlock_dll
, f
, inc
,
355 sdrc_rfr_ctrl_0
, sdrc_actim_ctrl_a_0
,
356 sdrc_actim_ctrl_b_0
, sdrc_mr_0
,
357 sdrc_rfr_ctrl_1
, sdrc_actim_ctrl_a_1
,
358 sdrc_actim_ctrl_b_1
, sdrc_mr_1
);
361 void omap3_sram_restore_context(void)
363 omap_sram_ceil
= omap_sram_base
+ omap_sram_size
;
365 _omap3_sram_configure_core_dpll
=
366 omap_sram_push(omap3_sram_configure_core_dpll
,
367 omap3_sram_configure_core_dpll_sz
);
368 omap_push_sram_idle();
371 static inline int omap34xx_sram_init(void)
373 omap3_sram_restore_context();
377 static inline int omap34xx_sram_init(void)
381 #endif /* CONFIG_ARCH_OMAP3 */
383 static inline int am33xx_sram_init(void)
388 int __init
omap_sram_init(void)
393 if (!(cpu_class_is_omap2()))
395 else if (cpu_is_omap242x())
396 omap242x_sram_init();
397 else if (cpu_is_omap2430())
398 omap243x_sram_init();
399 else if (soc_is_am33xx())
401 else if (cpu_is_omap34xx())
402 omap34xx_sram_init();