arch/arm/plat-orion/gpio.c

   1 /*
   2  * arch/arm/plat-orion/gpio.c
   3  *
   4  * Marvell Orion SoC GPIO handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/irq.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/bitops.h>
  17 #include <linux/io.h>
  18 #include <linux/gpio.h>
  19
  20 /*
  21  * GPIO unit register offsets.
  22  */
  23 #define GPIO_OUT_OFF            0x0000
  24 #define GPIO_IO_CONF_OFF        0x0004
  25 #define GPIO_BLINK_EN_OFF       0x0008
  26 #define GPIO_IN_POL_OFF         0x000c
  27 #define GPIO_DATA_IN_OFF        0x0010
  28 #define GPIO_EDGE_CAUSE_OFF     0x0014
  29 #define GPIO_EDGE_MASK_OFF      0x0018
  30 #define GPIO_LEVEL_MASK_OFF     0x001c
  31
  32 struct orion_gpio_chip {
  33         struct gpio_chip        chip;
  34         spinlock_t              lock;
  35         void __iomem            *base;
  36         unsigned long           valid_input;
  37         unsigned long           valid_output;
  38         int                     mask_offset;
  39         int                     secondary_irq_base;
  40 };
  41
  42 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
  43 {
  44         return ochip->base + GPIO_OUT_OFF;
  45 }
  46
  47 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
  48 {
  49         return ochip->base + GPIO_IO_CONF_OFF;
  50 }
  51
  52 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
  53 {
  54         return ochip->base + GPIO_BLINK_EN_OFF;
  55 }
  56
  57 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
  58 {
  59         return ochip->base + GPIO_IN_POL_OFF;
  60 }
  61
  62 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
  63 {
  64         return ochip->base + GPIO_DATA_IN_OFF;
  65 }
  66
  67 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
  68 {
  69         return ochip->base + GPIO_EDGE_CAUSE_OFF;
  70 }
  71
  72 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
  73 {
  74         return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
  75 }
  76
  77 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
  78 {
  79         return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
  80 }
  81
  82
  83 static struct orion_gpio_chip orion_gpio_chips[2];
  84 static int orion_gpio_chip_count;
  85
  86 static inline void
  87 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
  88 {
  89         u32 u;
  90
  91         u = readl(GPIO_IO_CONF(ochip));
  92         if (input)
  93                 u |= 1 << pin;
  94         else
  95                 u &= ~(1 << pin);
  96         writel(u, GPIO_IO_CONF(ochip));
  97 }
  98
  99 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
 100 {
 101         u32 u;
 102
 103         u = readl(GPIO_OUT(ochip));
 104         if (high)
 105                 u |= 1 << pin;
 106         else
 107                 u &= ~(1 << pin);
 108         writel(u, GPIO_OUT(ochip));
 109 }
 110
 111 static inline void
 112 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
 113 {
 114         u32 u;
 115
 116         u = readl(GPIO_BLINK_EN(ochip));
 117         if (blink)
 118                 u |= 1 << pin;
 119         else
 120                 u &= ~(1 << pin);
 121         writel(u, GPIO_BLINK_EN(ochip));
 122 }
 123
 124 static inline int
 125 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
 126 {
 127         if (pin >= ochip->chip.ngpio)
 128                 goto err_out;
 129
 130         if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
 131                 goto err_out;
 132
 133         if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
 134                 goto err_out;
 135
 136         return 1;
 137
 138 err_out:
 139         pr_debug("%s: invalid GPIO %d\n", __func__, pin);
 140         return false;
 141 }
 142
 143 /*
 144  * GENERIC_GPIO primitives.
 145  */
 146 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
 147 {
 148         struct orion_gpio_chip *ochip =
 149                 container_of(chip, struct orion_gpio_chip, chip);
 150
 151         if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
 152             orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
 153                 return 0;
 154
 155         return -EINVAL;
 156 }
 157
 158 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 159 {
 160         struct orion_gpio_chip *ochip =
 161                 container_of(chip, struct orion_gpio_chip, chip);
 162         unsigned long flags;
 163
 164         if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
 165                 return -EINVAL;
 166
 167         spin_lock_irqsave(&ochip->lock, flags);
 168         __set_direction(ochip, pin, 1);
 169         spin_unlock_irqrestore(&ochip->lock, flags);
 170
 171         return 0;
 172 }
 173
 174 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
 175 {
 176         struct orion_gpio_chip *ochip =
 177                 container_of(chip, struct orion_gpio_chip, chip);
 178         int val;
 179
 180         if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
 181                 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
 182         } else {
 183                 val = readl(GPIO_OUT(ochip));
 184         }
 185
 186         return (val >> pin) & 1;
 187 }
 188
 189 static int
 190 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
 191 {
 192         struct orion_gpio_chip *ochip =
 193                 container_of(chip, struct orion_gpio_chip, chip);
 194         unsigned long flags;
 195
 196         if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
 197                 return -EINVAL;
 198
 199         spin_lock_irqsave(&ochip->lock, flags);
 200         __set_blinking(ochip, pin, 0);
 201         __set_level(ochip, pin, value);
 202         __set_direction(ochip, pin, 0);
 203         spin_unlock_irqrestore(&ochip->lock, flags);
 204
 205         return 0;
 206 }
 207
 208 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 209 {
 210         struct orion_gpio_chip *ochip =
 211                 container_of(chip, struct orion_gpio_chip, chip);
 212         unsigned long flags;
 213
 214         spin_lock_irqsave(&ochip->lock, flags);
 215         __set_level(ochip, pin, value);
 216         spin_unlock_irqrestore(&ochip->lock, flags);
 217 }
 218
 219 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 220 {
 221         struct orion_gpio_chip *ochip =
 222                 container_of(chip, struct orion_gpio_chip, chip);
 223
 224         return ochip->secondary_irq_base + pin;
 225 }
 226
 227
 228 /*
 229  * Orion-specific GPIO API extensions.
 230  */
 231 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
 232 {
 233         int i;
 234
 235         for (i = 0; i < orion_gpio_chip_count; i++) {
 236                 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
 237                 struct gpio_chip *chip = &ochip->chip;
 238
 239                 if (pin >= chip->base && pin < chip->base + chip->ngpio)
 240                         return ochip;
 241         }
 242
 243         return NULL;
 244 }
 245
 246 void __init orion_gpio_set_unused(unsigned pin)
 247 {
 248         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 249
 250         if (ochip == NULL)
 251                 return;
 252
 253         pin -= ochip->chip.base;
 254
 255         /* Configure as output, drive low. */
 256         __set_level(ochip, pin, 0);
 257         __set_direction(ochip, pin, 0);
 258 }
 259
 260 void __init orion_gpio_set_valid(unsigned pin, int mode)
 261 {
 262         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 263
 264         if (ochip == NULL)
 265                 return;
 266
 267         pin -= ochip->chip.base;
 268
 269         if (mode == 1)
 270                 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
 271
 272         if (mode & GPIO_INPUT_OK)
 273                 __set_bit(pin, &ochip->valid_input);
 274         else
 275                 __clear_bit(pin, &ochip->valid_input);
 276
 277         if (mode & GPIO_OUTPUT_OK)
 278                 __set_bit(pin, &ochip->valid_output);
 279         else
 280                 __clear_bit(pin, &ochip->valid_output);
 281 }
 282
 283 void orion_gpio_set_blink(unsigned pin, int blink)
 284 {
 285         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 286         unsigned long flags;
 287
 288         if (ochip == NULL)
 289                 return;
 290
 291         spin_lock_irqsave(&ochip->lock, flags);
 292         __set_level(ochip, pin, 0);
 293         __set_blinking(ochip, pin, blink);
 294         spin_unlock_irqrestore(&ochip->lock, flags);
 295 }
 296 EXPORT_SYMBOL(orion_gpio_set_blink);
 297
 298
 299 /*****************************************************************************
 300  * Orion GPIO IRQ
 301  *
 302  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 303  * value of the line or the opposite value.
 304  *
 305  * Level IRQ handlers: DATA_IN is used directly as cause register.
 306  *                     Interrupt are masked by LEVEL_MASK registers.
 307  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 308  *                     Interrupt are masked by EDGE_MASK registers.
 309  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 310  *                     the polarity to catch the next line transaction.
 311  *                     This is a race condition that might not perfectly
 312  *                     work on some use cases.
 313  *
 314  * Every eight GPIO lines are grouped (OR'ed) before going up to main
 315  * cause register.
 316  *
 317  *                    EDGE  cause    mask
 318  *        data-in   /--------| |-----| |----\
 319  *     -----| |-----                         ---- to main cause reg
 320  *           X      \----------------| |----/
 321  *        polarity    LEVEL          mask
 322  *
 323  ****************************************************************************/
 324 static void gpio_irq_ack(struct irq_data *d)
 325 {
 326         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
 327         int type = irqd_get_trigger_type(d);
 328
 329         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 330                 int pin = d->irq - ochip->secondary_irq_base;
 331
 332                 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
 333         }
 334 }
 335
 336 static void gpio_irq_mask(struct irq_data *d)
 337 {
 338         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
 339         int type = irqd_get_trigger_type(d);
 340         void __iomem *reg;
 341         int pin;
 342
 343         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 344                 reg = GPIO_EDGE_MASK(ochip);
 345         else
 346                 reg = GPIO_LEVEL_MASK(ochip);
 347
 348         pin = d->irq - ochip->secondary_irq_base;
 349
 350         writel(readl(reg) & ~(1 << pin), reg);
 351 }
 352
 353 static void gpio_irq_unmask(struct irq_data *d)
 354 {
 355         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
 356         int type = irqd_get_trigger_type(d);
 357         void __iomem *reg;
 358         int pin;
 359
 360         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 361                 reg = GPIO_EDGE_MASK(ochip);
 362         else
 363                 reg = GPIO_LEVEL_MASK(ochip);
 364
 365         pin = d->irq - ochip->secondary_irq_base;
 366
 367         writel(readl(reg) | (1 << pin), reg);
 368 }
 369
 370 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 371 {
 372         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
 373         int pin;
 374         u32 u;
 375
 376         pin = d->irq - ochip->secondary_irq_base;
 377
 378         u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
 379         if (!u) {
 380                 printk(KERN_ERR "orion gpio_irq_set_type failed "
 381                                 "(irq %d, pin %d).\n", d->irq, pin);
 382                 return -EINVAL;
 383         }
 384
 385         /*
 386          * Set edge/level type.
 387          */
 388         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 389                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 390         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 391                 __irq_set_handler_locked(d->irq, handle_level_irq);
 392         } else {
 393                 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
 394                        d->irq, type);
 395                 return -EINVAL;
 396         }
 397
 398         /*
 399          * Configure interrupt polarity.
 400          */
 401         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
 402                 u = readl(GPIO_IN_POL(ochip));
 403                 u &= ~(1 << pin);
 404                 writel(u, GPIO_IN_POL(ochip));
 405         } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
 406                 u = readl(GPIO_IN_POL(ochip));
 407                 u |= 1 << pin;
 408                 writel(u, GPIO_IN_POL(ochip));
 409         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 410                 u32 v;
 411
 412                 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
 413
 414                 /*
 415                  * set initial polarity based on current input level
 416                  */
 417                 u = readl(GPIO_IN_POL(ochip));
 418                 if (v & (1 << pin))
 419                         u |= 1 << pin;          /* falling */
 420                 else
 421                         u &= ~(1 << pin);       /* rising */
 422                 writel(u, GPIO_IN_POL(ochip));
 423         }
 424
 425         return 0;
 426 }
 427
 428 struct irq_chip orion_gpio_irq_chip = {
 429         .name           = "orion_gpio_irq",
 430         .irq_ack        = gpio_irq_ack,
 431         .irq_mask       = gpio_irq_mask,
 432         .irq_unmask     = gpio_irq_unmask,
 433         .irq_set_type   = gpio_irq_set_type,
 434 };
 435
 436 void __init orion_gpio_init(int gpio_base, int ngpio,
 437                             u32 base, int mask_offset, int secondary_irq_base)
 438 {
 439         struct orion_gpio_chip *ochip;
 440         int i;
 441
 442         if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
 443                 return;
 444
 445         ochip = orion_gpio_chips + orion_gpio_chip_count;
 446         ochip->chip.label = "orion_gpio";
 447         ochip->chip.request = orion_gpio_request;
 448         ochip->chip.direction_input = orion_gpio_direction_input;
 449         ochip->chip.get = orion_gpio_get;
 450         ochip->chip.direction_output = orion_gpio_direction_output;
 451         ochip->chip.set = orion_gpio_set;
 452         ochip->chip.to_irq = orion_gpio_to_irq;
 453         ochip->chip.base = gpio_base;
 454         ochip->chip.ngpio = ngpio;
 455         ochip->chip.can_sleep = 0;
 456         spin_lock_init(&ochip->lock);
 457         ochip->base = (void __iomem *)base;
 458         ochip->valid_input = 0;
 459         ochip->valid_output = 0;
 460         ochip->mask_offset = mask_offset;
 461         ochip->secondary_irq_base = secondary_irq_base;
 462
 463         gpiochip_add(&ochip->chip);
 464
 465         orion_gpio_chip_count++;
 466
 467         /*
 468          * Mask and clear GPIO interrupts.
 469          */
 470         writel(0, GPIO_EDGE_CAUSE(ochip));
 471         writel(0, GPIO_EDGE_MASK(ochip));
 472         writel(0, GPIO_LEVEL_MASK(ochip));
 473
 474         for (i = 0; i < ngpio; i++) {
 475                 unsigned int irq = secondary_irq_base + i;
 476
 477                 irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
 478                                          handle_level_irq);
 479                 irq_set_chip_data(irq, ochip);
 480                 irq_set_status_flags(irq, IRQ_LEVEL);
 481                 set_irq_flags(irq, IRQF_VALID);
 482         }
 483 }
 484
 485 void orion_gpio_irq_handler(int pinoff)
 486 {
 487         struct orion_gpio_chip *ochip;
 488         u32 cause, type;
 489         int i;
 490
 491         ochip = orion_gpio_chip_find(pinoff);
 492         if (ochip == NULL)
 493                 return;
 494
 495         cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
 496         cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
 497
 498         for (i = 0; i < ochip->chip.ngpio; i++) {
 499                 int irq;
 500
 501                 irq = ochip->secondary_irq_base + i;
 502
 503                 if (!(cause & (1 << i)))
 504                         continue;
 505
 506                 type = irqd_get_trigger_type(irq_get_irq_data(irq));
 507                 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 508                         /* Swap polarity (race with GPIO line) */
 509                         u32 polarity;
 510
 511                         polarity = readl(GPIO_IN_POL(ochip));
 512                         polarity ^= 1 << i;
 513                         writel(polarity, GPIO_IN_POL(ochip));
 514                 }
 515                 generic_handle_irq(irq);
 516         }
 517 }