arch/arm/plat-pxa/gpio.c

   1 /*
   2  *  linux/arch/arm/plat-pxa/gpio.c
   3  *
   4  *  Generic PXA GPIO handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/io.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/bootmem.h>
  20
  21 #include <mach/gpio.h>
  22
  23 int pxa_last_gpio;
  24
  25 struct pxa_gpio_chip {
  26         struct gpio_chip chip;
  27         void __iomem    *regbase;
  28         char label[10];
  29
  30         unsigned long   irq_mask;
  31         unsigned long   irq_edge_rise;
  32         unsigned long   irq_edge_fall;
  33
  34 #ifdef CONFIG_PM
  35         unsigned long   saved_gplr;
  36         unsigned long   saved_gpdr;
  37         unsigned long   saved_grer;
  38         unsigned long   saved_gfer;
  39 #endif
  40 };
  41
  42 static DEFINE_SPINLOCK(gpio_lock);
  43 static struct pxa_gpio_chip *pxa_gpio_chips;
  44
  45 #define for_each_gpio_chip(i, c)                        \
  46         for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
  47
  48 static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
  49 {
  50         return container_of(c, struct pxa_gpio_chip, chip)->regbase;
  51 }
  52
  53 static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio)
  54 {
  55         return &pxa_gpio_chips[gpio_to_bank(gpio)];
  56 }
  57
  58 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  59 {
  60         void __iomem *base = gpio_chip_base(chip);
  61         uint32_t value, mask = 1 << offset;
  62         unsigned long flags;
  63
  64         spin_lock_irqsave(&gpio_lock, flags);
  65
  66         value = __raw_readl(base + GPDR_OFFSET);
  67         if (__gpio_is_inverted(chip->base + offset))
  68                 value |= mask;
  69         else
  70                 value &= ~mask;
  71         __raw_writel(value, base + GPDR_OFFSET);
  72
  73         spin_unlock_irqrestore(&gpio_lock, flags);
  74         return 0;
  75 }
  76
  77 static int pxa_gpio_direction_output(struct gpio_chip *chip,
  78                                      unsigned offset, int value)
  79 {
  80         void __iomem *base = gpio_chip_base(chip);
  81         uint32_t tmp, mask = 1 << offset;
  82         unsigned long flags;
  83
  84         __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
  85
  86         spin_lock_irqsave(&gpio_lock, flags);
  87
  88         tmp = __raw_readl(base + GPDR_OFFSET);
  89         if (__gpio_is_inverted(chip->base + offset))
  90                 tmp &= ~mask;
  91         else
  92                 tmp |= mask;
  93         __raw_writel(tmp, base + GPDR_OFFSET);
  94
  95         spin_unlock_irqrestore(&gpio_lock, flags);
  96         return 0;
  97 }
  98
  99 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 100 {
 101         return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
 102 }
 103
 104 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 105 {
 106         __raw_writel(1 << offset, gpio_chip_base(chip) +
 107                                 (value ? GPSR_OFFSET : GPCR_OFFSET));
 108 }
 109
 110 static int __init pxa_init_gpio_chip(int gpio_end)
 111 {
 112         int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
 113         struct pxa_gpio_chip *chips;
 114
 115         /* this is early, we have to use bootmem allocator, and we really
 116          * want this to be allocated dynamically for different 'gpio_end'
 117          */
 118         chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip));
 119         if (chips == NULL) {
 120                 pr_err("%s: failed to allocate GPIO chips\n", __func__);
 121                 return -ENOMEM;
 122         }
 123
 124         memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip));
 125
 126         for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
 127                 struct gpio_chip *c = &chips[i].chip;
 128
 129                 sprintf(chips[i].label, "gpio-%d", i);
 130                 chips[i].regbase = (void __iomem *)GPIO_BANK(i);
 131
 132                 c->base  = gpio;
 133                 c->label = chips[i].label;
 134
 135                 c->direction_input  = pxa_gpio_direction_input;
 136                 c->direction_output = pxa_gpio_direction_output;
 137                 c->get = pxa_gpio_get;
 138                 c->set = pxa_gpio_set;
 139
 140                 /* number of GPIOs on last bank may be less than 32 */
 141                 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
 142                 gpiochip_add(c);
 143         }
 144         pxa_gpio_chips = chips;
 145         return 0;
 146 }
 147
 148 /* Update only those GRERx and GFERx edge detection register bits if those
 149  * bits are set in c->irq_mask
 150  */
 151 static inline void update_edge_detect(struct pxa_gpio_chip *c)
 152 {
 153         uint32_t grer, gfer;
 154
 155         grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
 156         gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
 157         grer |= c->irq_edge_rise & c->irq_mask;
 158         gfer |= c->irq_edge_fall & c->irq_mask;
 159         __raw_writel(grer, c->regbase + GRER_OFFSET);
 160         __raw_writel(gfer, c->regbase + GFER_OFFSET);
 161 }
 162
 163 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 164 {
 165         struct pxa_gpio_chip *c;
 166         int gpio = irq_to_gpio(irq);
 167         unsigned long gpdr, mask = GPIO_bit(gpio);
 168
 169         c = gpio_to_chip(gpio);
 170
 171         if (type == IRQ_TYPE_PROBE) {
 172                 /* Don't mess with enabled GPIOs using preconfigured edges or
 173                  * GPIOs set to alternate function or to output during probe
 174                  */
 175                 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
 176                         return 0;
 177
 178                 if (__gpio_is_occupied(gpio))
 179                         return 0;
 180
 181                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 182         }
 183
 184         gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
 185
 186         if (__gpio_is_inverted(gpio))
 187                 __raw_writel(gpdr | mask,  c->regbase + GPDR_OFFSET);
 188         else
 189                 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
 190
 191         if (type & IRQ_TYPE_EDGE_RISING)
 192                 c->irq_edge_rise |= mask;
 193         else
 194                 c->irq_edge_rise &= ~mask;
 195
 196         if (type & IRQ_TYPE_EDGE_FALLING)
 197                 c->irq_edge_fall |= mask;
 198         else
 199                 c->irq_edge_fall &= ~mask;
 200
 201         update_edge_detect(c);
 202
 203         pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
 204                 ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
 205                 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
 206         return 0;
 207 }
 208
 209 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 210 {
 211         struct pxa_gpio_chip *c;
 212         int loop, gpio, gpio_base, n;
 213         unsigned long gedr;
 214
 215         do {
 216                 loop = 0;
 217                 for_each_gpio_chip(gpio, c) {
 218                         gpio_base = c->chip.base;
 219
 220                         gedr = __raw_readl(c->regbase + GEDR_OFFSET);
 221                         gedr = gedr & c->irq_mask;
 222                         __raw_writel(gedr, c->regbase + GEDR_OFFSET);
 223
 224                         n = find_first_bit(&gedr, BITS_PER_LONG);
 225                         while (n < BITS_PER_LONG) {
 226                                 loop = 1;
 227
 228                                 generic_handle_irq(gpio_to_irq(gpio_base + n));
 229                                 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
 230                         }
 231                 }
 232         } while (loop);
 233 }
 234
 235 static void pxa_ack_muxed_gpio(unsigned int irq)
 236 {
 237         int gpio = irq_to_gpio(irq);
 238         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
 239
 240         __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
 241 }
 242
 243 static void pxa_mask_muxed_gpio(unsigned int irq)
 244 {
 245         int gpio = irq_to_gpio(irq);
 246         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
 247         uint32_t grer, gfer;
 248
 249         c->irq_mask &= ~GPIO_bit(gpio);
 250
 251         grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
 252         gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
 253         __raw_writel(grer, c->regbase + GRER_OFFSET);
 254         __raw_writel(gfer, c->regbase + GFER_OFFSET);
 255 }
 256
 257 static void pxa_unmask_muxed_gpio(unsigned int irq)
 258 {
 259         int gpio = irq_to_gpio(irq);
 260         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
 261
 262         c->irq_mask |= GPIO_bit(gpio);
 263         update_edge_detect(c);
 264 }
 265
 266 static struct irq_chip pxa_muxed_gpio_chip = {
 267         .name           = "GPIO",
 268         .ack            = pxa_ack_muxed_gpio,
 269         .mask           = pxa_mask_muxed_gpio,
 270         .unmask         = pxa_unmask_muxed_gpio,
 271         .set_type       = pxa_gpio_irq_type,
 272 };
 273
 274 void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
 275 {
 276         struct pxa_gpio_chip *c;
 277         int gpio, irq;
 278
 279         pxa_last_gpio = end;
 280
 281         /* Initialize GPIO chips */
 282         pxa_init_gpio_chip(end);
 283
 284         /* clear all GPIO edge detects */
 285         for_each_gpio_chip(gpio, c) {
 286                 __raw_writel(0, c->regbase + GFER_OFFSET);
 287                 __raw_writel(0, c->regbase + GRER_OFFSET);
 288                 __raw_writel(~0,c->regbase + GEDR_OFFSET);
 289         }
 290
 291         for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
 292                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 293                 set_irq_handler(irq, handle_edge_irq);
 294                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 295         }
 296
 297         /* Install handler for GPIO>=2 edge detect interrupts */
 298         set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
 299         pxa_muxed_gpio_chip.set_wake = fn;
 300 }
 301
 302 #ifdef CONFIG_PM
 303 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
 304 {
 305         struct pxa_gpio_chip *c;
 306         int gpio;
 307
 308         for_each_gpio_chip(gpio, c) {
 309                 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
 310                 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
 311                 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
 312                 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
 313
 314                 /* Clear GPIO transition detect bits */
 315                 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
 316         }
 317         return 0;
 318 }
 319
 320 static int pxa_gpio_resume(struct sys_device *dev)
 321 {
 322         struct pxa_gpio_chip *c;
 323         int gpio;
 324
 325         for_each_gpio_chip(gpio, c) {
 326                 /* restore level with set/clear */
 327                 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
 328                 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
 329
 330                 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
 331                 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
 332                 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
 333         }
 334         return 0;
 335 }
 336 #else
 337 #define pxa_gpio_suspend        NULL
 338 #define pxa_gpio_resume         NULL
 339 #endif
 340
 341 struct sysdev_class pxa_gpio_sysclass = {
 342         .name           = "gpio",
 343         .suspend        = pxa_gpio_suspend,
 344         .resume         = pxa_gpio_resume,
 345 };
 346
 347 static int __init pxa_gpio_init(void)
 348 {
 349         return sysdev_class_register(&pxa_gpio_sysclass);
 350 }
 351
 352 core_initcall(pxa_gpio_init);