arch/arm/plat-s3c24xx/clock.c

   1 /* linux/arch/arm/plat-s3c24xx/clock.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C24XX Core clock control support
   7  *
   8  * Based on, and code from linux/arch/arm/mach-versatile/clock.c
   9  **
  10  **  Copyright (C) 2004 ARM Limited.
  11  **  Written by Deep Blue Solutions Limited.
  12  *
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/errno.h>
  34 #include <linux/err.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/sysdev.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/ioport.h>
  39 #include <linux/clk.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/delay.h>
  42 #include <linux/io.h>
  43
  44 #include <mach/hardware.h>
  45 #include <asm/irq.h>
  46
  47 #include <mach/regs-clock.h>
  48 #include <mach/regs-gpio.h>
  49
  50 #include <plat/clock.h>
  51 #include <plat/cpu.h>
  52 #include <plat/pll.h>
  53
  54 /* clock information */
  55
  56 static LIST_HEAD(clocks);
  57
  58 /* We originally used an mutex here, but some contexts (see resume)
  59  * are calling functions such as clk_set_parent() with IRQs disabled
  60  * causing an BUG to be triggered.
  61  */
  62 DEFINE_SPINLOCK(clocks_lock);
  63
  64 /* enable and disable calls for use with the clk struct */
  65
  66 static int clk_null_enable(struct clk *clk, int enable)
  67 {
  68         return 0;
  69 }
  70
  71 /* Clock API calls */
  72
  73 struct clk *clk_get(struct device *dev, const char *id)
  74 {
  75         struct clk *p;
  76         struct clk *clk = ERR_PTR(-ENOENT);
  77         int idno;
  78
  79         if (dev == NULL || dev->bus != &platform_bus_type)
  80                 idno = -1;
  81         else
  82                 idno = to_platform_device(dev)->id;
  83
  84         spin_lock(&clocks_lock);
  85
  86         list_for_each_entry(p, &clocks, list) {
  87                 if (p->id == idno &&
  88                     strcmp(id, p->name) == 0 &&
  89                     try_module_get(p->owner)) {
  90                         clk = p;
  91                         break;
  92                 }
  93         }
  94
  95         /* check for the case where a device was supplied, but the
  96          * clock that was being searched for is not device specific */
  97
  98         if (IS_ERR(clk)) {
  99                 list_for_each_entry(p, &clocks, list) {
 100                         if (p->id == -1 && strcmp(id, p->name) == 0 &&
 101                             try_module_get(p->owner)) {
 102                                 clk = p;
 103                                 break;
 104                         }
 105                 }
 106         }
 107
 108         spin_unlock(&clocks_lock);
 109         return clk;
 110 }
 111
 112 void clk_put(struct clk *clk)
 113 {
 114         module_put(clk->owner);
 115 }
 116
 117 int clk_enable(struct clk *clk)
 118 {
 119         if (IS_ERR(clk) || clk == NULL)
 120                 return -EINVAL;
 121
 122         clk_enable(clk->parent);
 123
 124         spin_lock(&clocks_lock);
 125
 126         if ((clk->usage++) == 0)
 127                 (clk->enable)(clk, 1);
 128
 129         spin_unlock(&clocks_lock);
 130         return 0;
 131 }
 132
 133 void clk_disable(struct clk *clk)
 134 {
 135         if (IS_ERR(clk) || clk == NULL)
 136                 return;
 137
 138         spin_lock(&clocks_lock);
 139
 140         if ((--clk->usage) == 0)
 141                 (clk->enable)(clk, 0);
 142
 143         spin_unlock(&clocks_lock);
 144         clk_disable(clk->parent);
 145 }
 146
 147
 148 unsigned long clk_get_rate(struct clk *clk)
 149 {
 150         if (IS_ERR(clk))
 151                 return 0;
 152
 153         if (clk->rate != 0)
 154                 return clk->rate;
 155
 156         if (clk->get_rate != NULL)
 157                 return (clk->get_rate)(clk);
 158
 159         if (clk->parent != NULL)
 160                 return clk_get_rate(clk->parent);
 161
 162         return clk->rate;
 163 }
 164
 165 long clk_round_rate(struct clk *clk, unsigned long rate)
 166 {
 167         if (!IS_ERR(clk) && clk->round_rate)
 168                 return (clk->round_rate)(clk, rate);
 169
 170         return rate;
 171 }
 172
 173 int clk_set_rate(struct clk *clk, unsigned long rate)
 174 {
 175         int ret;
 176
 177         if (IS_ERR(clk))
 178                 return -EINVAL;
 179
 180         /* We do not default just do a clk->rate = rate as
 181          * the clock may have been made this way by choice.
 182          */
 183
 184         WARN_ON(clk->set_rate == NULL);
 185
 186         if (clk->set_rate == NULL)
 187                 return -EINVAL;
 188
 189         spin_lock(&clocks_lock);
 190         ret = (clk->set_rate)(clk, rate);
 191         spin_unlock(&clocks_lock);
 192
 193         return ret;
 194 }
 195
 196 struct clk *clk_get_parent(struct clk *clk)
 197 {
 198         return clk->parent;
 199 }
 200
 201 int clk_set_parent(struct clk *clk, struct clk *parent)
 202 {
 203         int ret = 0;
 204
 205         if (IS_ERR(clk))
 206                 return -EINVAL;
 207
 208         spin_lock(&clocks_lock);
 209
 210         if (clk->set_parent)
 211                 ret = (clk->set_parent)(clk, parent);
 212
 213         spin_unlock(&clocks_lock);
 214
 215         return ret;
 216 }
 217
 218 EXPORT_SYMBOL(clk_get);
 219 EXPORT_SYMBOL(clk_put);
 220 EXPORT_SYMBOL(clk_enable);
 221 EXPORT_SYMBOL(clk_disable);
 222 EXPORT_SYMBOL(clk_get_rate);
 223 EXPORT_SYMBOL(clk_round_rate);
 224 EXPORT_SYMBOL(clk_set_rate);
 225 EXPORT_SYMBOL(clk_get_parent);
 226 EXPORT_SYMBOL(clk_set_parent);
 227
 228 /* base clocks */
 229
 230 static int clk_default_setrate(struct clk *clk, unsigned long rate)
 231 {
 232         clk->rate = rate;
 233         return 0;
 234 }
 235
 236 struct clk clk_xtal = {
 237         .name           = "xtal",
 238         .id             = -1,
 239         .rate           = 0,
 240         .parent         = NULL,
 241         .ctrlbit        = 0,
 242 };
 243
 244 struct clk clk_mpll = {
 245         .name           = "mpll",
 246         .id             = -1,
 247         .set_rate       = clk_default_setrate,
 248 };
 249
 250 struct clk clk_upll = {
 251         .name           = "upll",
 252         .id             = -1,
 253         .parent         = NULL,
 254         .ctrlbit        = 0,
 255 };
 256
 257 struct clk clk_f = {
 258         .name           = "fclk",
 259         .id             = -1,
 260         .rate           = 0,
 261         .parent         = &clk_mpll,
 262         .ctrlbit        = 0,
 263         .set_rate       = clk_default_setrate,
 264 };
 265
 266 struct clk clk_h = {
 267         .name           = "hclk",
 268         .id             = -1,
 269         .rate           = 0,
 270         .parent         = NULL,
 271         .ctrlbit        = 0,
 272         .set_rate       = clk_default_setrate,
 273 };
 274
 275 struct clk clk_p = {
 276         .name           = "pclk",
 277         .id             = -1,
 278         .rate           = 0,
 279         .parent         = NULL,
 280         .ctrlbit        = 0,
 281         .set_rate       = clk_default_setrate,
 282 };
 283
 284 struct clk clk_usb_bus = {
 285         .name           = "usb-bus",
 286         .id             = -1,
 287         .rate           = 0,
 288         .parent         = &clk_upll,
 289 };
 290
 291
 292
 293 struct clk s3c24xx_uclk = {
 294         .name           = "uclk",
 295         .id             = -1,
 296 };
 297
 298 /* initialise the clock system */
 299
 300 int s3c24xx_register_clock(struct clk *clk)
 301 {
 302         clk->owner = THIS_MODULE;
 303
 304         if (clk->enable == NULL)
 305                 clk->enable = clk_null_enable;
 306
 307         /* add to the list of available clocks */
 308
 309         spin_lock(&clocks_lock);
 310         list_add(&clk->list, &clocks);
 311         spin_unlock(&clocks_lock);
 312
 313         return 0;
 314 }
 315
 316 int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
 317 {
 318         int fails = 0;
 319
 320         for (; nr_clks > 0; nr_clks--, clks++) {
 321                 if (s3c24xx_register_clock(*clks) < 0)
 322                         fails++;
 323         }
 324
 325         return fails;
 326 }
 327
 328 /* initalise all the clocks */
 329
 330 int __init s3c24xx_setup_clocks(unsigned long xtal,
 331                                 unsigned long fclk,
 332                                 unsigned long hclk,
 333                                 unsigned long pclk)
 334 {
 335         printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
 336
 337         /* initialise the main system clocks */
 338
 339         clk_xtal.rate = xtal;
 340         clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
 341
 342         clk_mpll.rate = fclk;
 343         clk_h.rate = hclk;
 344         clk_p.rate = pclk;
 345         clk_f.rate = fclk;
 346
 347         /* assume uart clocks are correctly setup */
 348
 349         /* register our clocks */
 350
 351         if (s3c24xx_register_clock(&clk_xtal) < 0)
 352                 printk(KERN_ERR "failed to register master xtal\n");
 353
 354         if (s3c24xx_register_clock(&clk_mpll) < 0)
 355                 printk(KERN_ERR "failed to register mpll clock\n");
 356
 357         if (s3c24xx_register_clock(&clk_upll) < 0)
 358                 printk(KERN_ERR "failed to register upll clock\n");
 359
 360         if (s3c24xx_register_clock(&clk_f) < 0)
 361                 printk(KERN_ERR "failed to register cpu fclk\n");
 362
 363         if (s3c24xx_register_clock(&clk_h) < 0)
 364                 printk(KERN_ERR "failed to register cpu hclk\n");
 365
 366         if (s3c24xx_register_clock(&clk_p) < 0)
 367                 printk(KERN_ERR "failed to register cpu pclk\n");
 368
 369         return 0;
 370 }