1 /* linux/arch/arm/plat-s3c24xx/dma.c
3 * Copyright (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
30 #include <asm/system.h>
32 #include <mach/hardware.h>
37 #include <plat/dma-plat.h>
40 static void __iomem
*dma_base
;
41 static struct kmem_cache
*dma_kmem
;
43 static int dma_channels
;
45 static struct s3c24xx_dma_selection dma_sel
;
47 /* dma channel state information */
48 struct s3c2410_dma_chan s3c2410_chans
[S3C2410_DMA_CHANNELS
];
50 /* debugging functions */
52 #define BUF_MAGIC (0xcafebabe)
54 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
56 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
59 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
62 dma_wrreg(struct s3c2410_dma_chan
*chan
, int reg
, unsigned long val
)
64 pr_debug("writing %08x to register %08x\n",(unsigned int)val
,reg
);
65 writel(val
, dma_regaddr(chan
, reg
));
69 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
71 /* captured register state for debug */
73 struct s3c2410_dma_regstate
{
78 unsigned long dmsktrig
;
81 #ifdef CONFIG_S3C2410_DMA_DEBUG
85 * simple debug routine to print the current state of the dma registers
89 dmadbg_capture(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_regstate
*regs
)
91 regs
->dcsrc
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
92 regs
->disrc
= dma_rdreg(chan
, S3C2410_DMA_DISRC
);
93 regs
->dstat
= dma_rdreg(chan
, S3C2410_DMA_DSTAT
);
94 regs
->dcon
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
95 regs
->dmsktrig
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
99 dmadbg_dumpregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
,
100 struct s3c2410_dma_regstate
*regs
)
102 printk(KERN_DEBUG
"dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
103 chan
->number
, fname
, line
,
104 regs
->dcsrc
, regs
->disrc
, regs
->dstat
, regs
->dmsktrig
,
109 dmadbg_showchan(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
111 struct s3c2410_dma_regstate state
;
113 dmadbg_capture(chan
, &state
);
115 printk(KERN_DEBUG
"dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
116 chan
->number
, fname
, line
, chan
->load_state
,
117 chan
->curr
, chan
->next
, chan
->end
);
119 dmadbg_dumpregs(fname
, line
, chan
, &state
);
123 dmadbg_showregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
125 struct s3c2410_dma_regstate state
;
127 dmadbg_capture(chan
, &state
);
128 dmadbg_dumpregs(fname
, line
, chan
, &state
);
131 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
132 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
134 #define dbg_showregs(chan) do { } while(0)
135 #define dbg_showchan(chan) do { } while(0)
136 #endif /* CONFIG_S3C2410_DMA_DEBUG */
138 static struct s3c2410_dma_chan
*dma_chan_map
[DMACH_MAX
];
140 /* lookup_dma_channel
142 * change the dma channel number given into a real dma channel id
145 static struct s3c2410_dma_chan
*lookup_dma_channel(unsigned int channel
)
147 if (channel
& DMACH_LOW_LEVEL
)
148 return &s3c2410_chans
[channel
& ~DMACH_LOW_LEVEL
];
150 return dma_chan_map
[channel
];
153 /* s3c2410_dma_stats_timeout
155 * Update DMA stats from timeout info
159 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats
*stats
, int val
)
164 if (val
> stats
->timeout_longest
)
165 stats
->timeout_longest
= val
;
166 if (val
< stats
->timeout_shortest
)
167 stats
->timeout_shortest
= val
;
169 stats
->timeout_avg
+= val
;
172 /* s3c2410_dma_waitforload
174 * wait for the DMA engine to load a buffer, and update the state accordingly
178 s3c2410_dma_waitforload(struct s3c2410_dma_chan
*chan
, int line
)
180 int timeout
= chan
->load_timeout
;
183 if (chan
->load_state
!= S3C2410_DMALOAD_1LOADED
) {
184 printk(KERN_ERR
"dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan
->number
, chan
->load_state
, line
);
188 if (chan
->stats
!= NULL
)
189 chan
->stats
->loads
++;
191 while (--timeout
> 0) {
192 if ((dma_rdreg(chan
, S3C2410_DMA_DSTAT
) << (32-20)) != 0) {
193 took
= chan
->load_timeout
- timeout
;
195 s3c2410_dma_stats_timeout(chan
->stats
, took
);
197 switch (chan
->load_state
) {
198 case S3C2410_DMALOAD_1LOADED
:
199 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
203 printk(KERN_ERR
"dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan
->number
, chan
->load_state
);
210 if (chan
->stats
!= NULL
) {
211 chan
->stats
->timeout_failed
++;
219 /* s3c2410_dma_loadbuffer
221 * load a buffer, and update the channel state
225 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan
*chan
,
226 struct s3c2410_dma_buf
*buf
)
228 unsigned long reload
;
230 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
231 buf
, (unsigned long)buf
->data
, buf
->size
);
234 dmawarn("buffer is NULL\n");
238 /* check the state of the channel before we do anything */
240 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
241 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
244 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED_1RUNNING
) {
245 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
248 /* it would seem sensible if we are the last buffer to not bother
249 * with the auto-reload bit, so that the DMA engine will not try
250 * and load another transfer after this one has finished...
252 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
253 pr_debug("load_state is none, checking for noreload (next=%p)\n",
255 reload
= (buf
->next
== NULL
) ? S3C2410_DCON_NORELOAD
: 0;
257 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
258 reload
= S3C2410_DCON_AUTORELOAD
;
261 if ((buf
->data
& 0xf0000000) != 0x30000000) {
262 dmawarn("dmaload: buffer is %p\n", (void *)buf
->data
);
265 writel(buf
->data
, chan
->addr_reg
);
267 dma_wrreg(chan
, S3C2410_DMA_DCON
,
268 chan
->dcon
| reload
| (buf
->size
/chan
->xfer_unit
));
270 chan
->next
= buf
->next
;
272 /* update the state of the channel */
274 switch (chan
->load_state
) {
275 case S3C2410_DMALOAD_NONE
:
276 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
279 case S3C2410_DMALOAD_1RUNNING
:
280 chan
->load_state
= S3C2410_DMALOAD_1LOADED_1RUNNING
;
284 dmawarn("dmaload: unknown state %d in loadbuffer\n",
292 /* s3c2410_dma_call_op
294 * small routine to call the op routine with the given op if it has been
299 s3c2410_dma_call_op(struct s3c2410_dma_chan
*chan
, enum s3c2410_chan_op op
)
301 if (chan
->op_fn
!= NULL
) {
302 (chan
->op_fn
)(chan
, op
);
306 /* s3c2410_dma_buffdone
308 * small wrapper to check if callback routine needs to be called, and
313 s3c2410_dma_buffdone(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_buf
*buf
,
314 enum s3c2410_dma_buffresult result
)
317 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
318 chan
->callback_fn
, buf
, buf
->id
, buf
->size
, result
);
321 if (chan
->callback_fn
!= NULL
) {
322 (chan
->callback_fn
)(chan
, buf
->id
, buf
->size
, result
);
328 * start a dma channel going
331 static int s3c2410_dma_start(struct s3c2410_dma_chan
*chan
)
336 pr_debug("s3c2410_start_dma: channel=%d\n", chan
->number
);
338 local_irq_save(flags
);
340 if (chan
->state
== S3C2410_DMA_RUNNING
) {
341 pr_debug("s3c2410_start_dma: already running (%d)\n", chan
->state
);
342 local_irq_restore(flags
);
346 chan
->state
= S3C2410_DMA_RUNNING
;
348 /* check wether there is anything to load, and if not, see
349 * if we can find anything to load
352 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
353 if (chan
->next
== NULL
) {
354 printk(KERN_ERR
"dma%d: channel has nothing loaded\n",
356 chan
->state
= S3C2410_DMA_IDLE
;
357 local_irq_restore(flags
);
361 s3c2410_dma_loadbuffer(chan
, chan
->next
);
366 /* enable the channel */
368 if (!chan
->irq_enabled
) {
369 enable_irq(chan
->irq
);
370 chan
->irq_enabled
= 1;
373 /* start the channel going */
375 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
376 tmp
&= ~S3C2410_DMASKTRIG_STOP
;
377 tmp
|= S3C2410_DMASKTRIG_ON
;
378 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
380 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan
->number
, tmp
);
383 /* the dma buffer loads should take care of clearing the AUTO
384 * reloading feature */
385 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
386 tmp
&= ~S3C2410_DCON_NORELOAD
;
387 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
390 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_START
);
394 /* if we've only loaded one buffer onto the channel, then chec
395 * to see if we have another, and if so, try and load it so when
396 * the first buffer is finished, the new one will be loaded onto
399 if (chan
->next
!= NULL
) {
400 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
402 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
403 pr_debug("%s: buff not yet loaded, no more todo\n",
406 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
407 s3c2410_dma_loadbuffer(chan
, chan
->next
);
410 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
411 s3c2410_dma_loadbuffer(chan
, chan
->next
);
416 local_irq_restore(flags
);
421 /* s3c2410_dma_canload
423 * work out if we can queue another buffer into the DMA engine
427 s3c2410_dma_canload(struct s3c2410_dma_chan
*chan
)
429 if (chan
->load_state
== S3C2410_DMALOAD_NONE
||
430 chan
->load_state
== S3C2410_DMALOAD_1RUNNING
)
436 /* s3c2410_dma_enqueue
438 * queue an given buffer for dma transfer.
440 * id the device driver's id information for this buffer
441 * data the physical address of the buffer data
442 * size the size of the buffer in bytes
444 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
445 * is checked, and if set, the channel is started. If this flag isn't set,
446 * then an error will be returned.
448 * It is possible to queue more than one DMA buffer onto a channel at
449 * once, and the code will deal with the re-loading of the next buffer
453 int s3c2410_dma_enqueue(unsigned int channel
, void *id
,
454 dma_addr_t data
, int size
)
456 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
457 struct s3c2410_dma_buf
*buf
;
463 pr_debug("%s: id=%p, data=%08x, size=%d\n",
464 __func__
, id
, (unsigned int)data
, size
);
466 buf
= kmem_cache_alloc(dma_kmem
, GFP_ATOMIC
);
468 pr_debug("%s: out of memory (%ld alloc)\n",
469 __func__
, (long)sizeof(*buf
));
473 //pr_debug("%s: new buffer %p\n", __func__, buf);
474 //dbg_showchan(chan);
477 buf
->data
= buf
->ptr
= data
;
480 buf
->magic
= BUF_MAGIC
;
482 local_irq_save(flags
);
484 if (chan
->curr
== NULL
) {
485 /* we've got nothing loaded... */
486 pr_debug("%s: buffer %p queued onto empty channel\n",
493 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
494 chan
->number
, __func__
, buf
);
496 if (chan
->end
== NULL
)
497 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
498 chan
->number
, __func__
, chan
);
500 chan
->end
->next
= buf
;
504 /* if necessary, update the next buffer field */
505 if (chan
->next
== NULL
)
508 /* check to see if we can load a buffer */
509 if (chan
->state
== S3C2410_DMA_RUNNING
) {
510 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
&& 1) {
511 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
512 printk(KERN_ERR
"dma%d: loadbuffer:"
513 "timeout loading buffer\n",
516 local_irq_restore(flags
);
521 while (s3c2410_dma_canload(chan
) && chan
->next
!= NULL
) {
522 s3c2410_dma_loadbuffer(chan
, chan
->next
);
524 } else if (chan
->state
== S3C2410_DMA_IDLE
) {
525 if (chan
->flags
& S3C2410_DMAF_AUTOSTART
) {
526 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
527 S3C2410_DMAOP_START
);
531 local_irq_restore(flags
);
535 EXPORT_SYMBOL(s3c2410_dma_enqueue
);
538 s3c2410_dma_freebuf(struct s3c2410_dma_buf
*buf
)
540 int magicok
= (buf
->magic
== BUF_MAGIC
);
545 kmem_cache_free(dma_kmem
, buf
);
547 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf
);
551 /* s3c2410_dma_lastxfer
553 * called when the system is out of buffers, to ensure that the channel
554 * is prepared for shutdown.
558 s3c2410_dma_lastxfer(struct s3c2410_dma_chan
*chan
)
561 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
562 chan
->number
, chan
->load_state
);
565 switch (chan
->load_state
) {
566 case S3C2410_DMALOAD_NONE
:
569 case S3C2410_DMALOAD_1LOADED
:
570 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
572 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
573 chan
->number
, __func__
);
578 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
579 /* I belive in this case we do not have anything to do
580 * until the next buffer comes along, and we turn off the
585 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
586 chan
->number
, chan
->load_state
);
591 /* hopefully this'll shut the damned thing up after the transfer... */
592 dma_wrreg(chan
, S3C2410_DMA_DCON
, chan
->dcon
| S3C2410_DCON_NORELOAD
);
596 #define dmadbg2(x...)
599 s3c2410_dma_irq(int irq
, void *devpw
)
601 struct s3c2410_dma_chan
*chan
= (struct s3c2410_dma_chan
*)devpw
;
602 struct s3c2410_dma_buf
*buf
;
608 /* modify the channel state */
610 switch (chan
->load_state
) {
611 case S3C2410_DMALOAD_1RUNNING
:
612 /* TODO - if we are running only one buffer, we probably
613 * want to reload here, and then worry about the buffer
616 chan
->load_state
= S3C2410_DMALOAD_NONE
;
619 case S3C2410_DMALOAD_1LOADED
:
620 /* iirc, we should go back to NONE loaded here, we
621 * had a buffer, and it was never verified as being
625 chan
->load_state
= S3C2410_DMALOAD_NONE
;
628 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
629 /* we'll worry about checking to see if another buffer is
630 * ready after we've called back the owner. This should
631 * ensure we do not wait around too long for the DMA
632 * engine to start the next transfer
635 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
638 case S3C2410_DMALOAD_NONE
:
639 printk(KERN_ERR
"dma%d: IRQ with no loaded buffer?\n",
644 printk(KERN_ERR
"dma%d: IRQ in invalid load_state %d\n",
645 chan
->number
, chan
->load_state
);
650 /* update the chain to make sure that if we load any more
651 * buffers when we call the callback function, things should
654 chan
->curr
= buf
->next
;
657 if (buf
->magic
!= BUF_MAGIC
) {
658 printk(KERN_ERR
"dma%d: %s: buf %p incorrect magic\n",
659 chan
->number
, __func__
, buf
);
663 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_OK
);
666 s3c2410_dma_freebuf(buf
);
670 /* only reload if the channel is still running... our buffer done
671 * routine may have altered the state by requesting the dma channel
672 * to stop or shutdown... */
674 /* todo: check that when the channel is shut-down from inside this
675 * function, we cope with unsetting reload, etc */
677 if (chan
->next
!= NULL
&& chan
->state
!= S3C2410_DMA_IDLE
) {
680 switch (chan
->load_state
) {
681 case S3C2410_DMALOAD_1RUNNING
:
682 /* don't need to do anything for this state */
685 case S3C2410_DMALOAD_NONE
:
686 /* can load buffer immediately */
689 case S3C2410_DMALOAD_1LOADED
:
690 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
692 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
693 chan
->number
, __func__
);
699 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
703 printk(KERN_ERR
"dma%d: unknown load_state in irq, %d\n",
704 chan
->number
, chan
->load_state
);
708 local_irq_save(flags
);
709 s3c2410_dma_loadbuffer(chan
, chan
->next
);
710 local_irq_restore(flags
);
712 s3c2410_dma_lastxfer(chan
);
714 /* see if we can stop this channel.. */
715 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
716 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
717 chan
->number
, jiffies
);
718 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
727 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
);
729 /* s3c2410_request_dma
731 * get control of an dma channel
734 int s3c2410_dma_request(unsigned int channel
,
735 struct s3c2410_dma_client
*client
,
738 struct s3c2410_dma_chan
*chan
;
742 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
743 channel
, client
->name
, dev
);
745 local_irq_save(flags
);
747 chan
= s3c2410_dma_map_channel(channel
);
749 local_irq_restore(flags
);
755 chan
->client
= client
;
758 if (!chan
->irq_claimed
) {
759 pr_debug("dma%d: %s : requesting irq %d\n",
760 channel
, __func__
, chan
->irq
);
762 chan
->irq_claimed
= 1;
763 local_irq_restore(flags
);
765 err
= request_irq(chan
->irq
, s3c2410_dma_irq
, IRQF_DISABLED
,
766 client
->name
, (void *)chan
);
768 local_irq_save(flags
);
772 chan
->irq_claimed
= 0;
773 local_irq_restore(flags
);
775 printk(KERN_ERR
"%s: cannot get IRQ %d for DMA %d\n",
776 client
->name
, chan
->irq
, chan
->number
);
780 chan
->irq_enabled
= 1;
783 local_irq_restore(flags
);
787 pr_debug("%s: channel initialised, %p\n", __func__
, chan
);
789 return chan
->number
| DMACH_LOW_LEVEL
;
792 EXPORT_SYMBOL(s3c2410_dma_request
);
796 * release the given channel back to the system, will stop and flush
797 * any outstanding transfers, and ensure the channel is ready for the
800 * Note, although a warning is currently printed if the freeing client
801 * info is not the same as the registrant's client info, the free is still
802 * allowed to go through.
805 int s3c2410_dma_free(unsigned int channel
, struct s3c2410_dma_client
*client
)
807 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
813 local_irq_save(flags
);
815 if (chan
->client
!= client
) {
816 printk(KERN_WARNING
"dma%d: possible free from different client (channel %p, passed %p)\n",
817 channel
, chan
->client
, client
);
820 /* sort out stopping and freeing the channel */
822 if (chan
->state
!= S3C2410_DMA_IDLE
) {
823 pr_debug("%s: need to stop dma channel %p\n",
826 /* possibly flush the channel */
827 s3c2410_dma_ctrl(channel
, S3C2410_DMAOP_STOP
);
833 if (chan
->irq_claimed
)
834 free_irq(chan
->irq
, (void *)chan
);
836 chan
->irq_claimed
= 0;
838 if (!(channel
& DMACH_LOW_LEVEL
))
839 dma_chan_map
[channel
] = NULL
;
841 local_irq_restore(flags
);
846 EXPORT_SYMBOL(s3c2410_dma_free
);
848 static int s3c2410_dma_dostop(struct s3c2410_dma_chan
*chan
)
853 pr_debug("%s:\n", __func__
);
857 local_irq_save(flags
);
859 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_STOP
);
861 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
862 tmp
|= S3C2410_DMASKTRIG_STOP
;
863 //tmp &= ~S3C2410_DMASKTRIG_ON;
864 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
867 /* should also clear interrupts, according to WinCE BSP */
868 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
869 tmp
|= S3C2410_DCON_NORELOAD
;
870 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
873 /* should stop do this, or should we wait for flush? */
874 chan
->state
= S3C2410_DMA_IDLE
;
875 chan
->load_state
= S3C2410_DMALOAD_NONE
;
877 local_irq_restore(flags
);
882 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan
*chan
)
885 unsigned int timeout
= 0x10000;
887 while (timeout
-- > 0) {
888 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
890 if (!(tmp
& S3C2410_DMASKTRIG_ON
))
894 pr_debug("dma%d: failed to stop?\n", chan
->number
);
900 * stop the channel, and remove all current and pending transfers
903 static int s3c2410_dma_flush(struct s3c2410_dma_chan
*chan
)
905 struct s3c2410_dma_buf
*buf
, *next
;
908 pr_debug("%s: chan %p (%d)\n", __func__
, chan
, chan
->number
);
912 local_irq_save(flags
);
914 if (chan
->state
!= S3C2410_DMA_IDLE
) {
915 pr_debug("%s: stopping channel...\n", __func__
);
916 s3c2410_dma_ctrl(chan
->number
, S3C2410_DMAOP_STOP
);
923 chan
->curr
= chan
->next
= chan
->end
= NULL
;
926 for ( ; buf
!= NULL
; buf
= next
) {
929 pr_debug("%s: free buffer %p, next %p\n",
930 __func__
, buf
, buf
->next
);
932 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_ABORT
);
933 s3c2410_dma_freebuf(buf
);
939 s3c2410_dma_waitforstop(chan
);
942 /* should also clear interrupts, according to WinCE BSP */
946 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
947 tmp
|= S3C2410_DCON_NORELOAD
;
948 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
954 local_irq_restore(flags
);
959 static int s3c2410_dma_started(struct s3c2410_dma_chan
*chan
)
963 local_irq_save(flags
);
967 /* if we've only loaded one buffer onto the channel, then chec
968 * to see if we have another, and if so, try and load it so when
969 * the first buffer is finished, the new one will be loaded onto
972 if (chan
->next
!= NULL
) {
973 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
975 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
976 pr_debug("%s: buff not yet loaded, no more todo\n",
979 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
980 s3c2410_dma_loadbuffer(chan
, chan
->next
);
983 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
984 s3c2410_dma_loadbuffer(chan
, chan
->next
);
989 local_irq_restore(flags
);
996 s3c2410_dma_ctrl(unsigned int channel
, enum s3c2410_chan_op op
)
998 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1004 case S3C2410_DMAOP_START
:
1005 return s3c2410_dma_start(chan
);
1007 case S3C2410_DMAOP_STOP
:
1008 return s3c2410_dma_dostop(chan
);
1010 case S3C2410_DMAOP_PAUSE
:
1011 case S3C2410_DMAOP_RESUME
:
1014 case S3C2410_DMAOP_FLUSH
:
1015 return s3c2410_dma_flush(chan
);
1017 case S3C2410_DMAOP_STARTED
:
1018 return s3c2410_dma_started(chan
);
1020 case S3C2410_DMAOP_TIMEOUT
:
1025 return -ENOENT
; /* unknown, don't bother */
1028 EXPORT_SYMBOL(s3c2410_dma_ctrl
);
1030 /* DMA configuration for each channel
1032 * DISRCC -> source of the DMA (AHB,APB)
1033 * DISRC -> source address of the DMA
1034 * DIDSTC -> destination of the DMA (AHB,APD)
1035 * DIDST -> destination address of the DMA
1038 /* s3c2410_dma_config
1040 * xfersize: size of unit in bytes (1,2,4)
1043 int s3c2410_dma_config(unsigned int channel
,
1046 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1049 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1050 __func__
, channel
, xferunit
, dcon
);
1055 pr_debug("%s: Initial dcon is %08x\n", __func__
, dcon
);
1057 dcon
= chan
->dcon
& dma_sel
.dcon_mask
;
1059 pr_debug("%s: New dcon is %08x\n", __func__
, dcon
);
1061 switch (chan
->req_ch
) {
1068 dcon
|= S3C2410_DCON_HANDSHAKE
;
1069 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1073 /* note, ensure if need HANDSHAKE or not */
1074 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1079 dcon
|= S3C2410_DCON_HANDSHAKE
;
1080 dcon
|= S3C2410_DCON_SYNC_HCLK
;
1086 dcon
|= S3C2410_DCON_BYTE
;
1090 dcon
|= S3C2410_DCON_HALFWORD
;
1094 dcon
|= S3C2410_DCON_WORD
;
1098 pr_debug("%s: bad transfer size %d\n", __func__
, xferunit
);
1102 dcon
|= S3C2410_DCON_HWTRIG
;
1103 dcon
|= S3C2410_DCON_INTREQ
;
1105 pr_debug("%s: dcon now %08x\n", __func__
, dcon
);
1108 chan
->xfer_unit
= xferunit
;
1113 EXPORT_SYMBOL(s3c2410_dma_config
);
1115 int s3c2410_dma_setflags(unsigned int channel
, unsigned int flags
)
1117 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1122 pr_debug("%s: chan=%p, flags=%08x\n", __func__
, chan
, flags
);
1124 chan
->flags
= flags
;
1129 EXPORT_SYMBOL(s3c2410_dma_setflags
);
1132 /* do we need to protect the settings of the fields from
1136 int s3c2410_dma_set_opfn(unsigned int channel
, s3c2410_dma_opfn_t rtn
)
1138 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1143 pr_debug("%s: chan=%p, op rtn=%p\n", __func__
, chan
, rtn
);
1150 EXPORT_SYMBOL(s3c2410_dma_set_opfn
);
1152 int s3c2410_dma_set_buffdone_fn(unsigned int channel
, s3c2410_dma_cbfn_t rtn
)
1154 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1159 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__
, chan
, rtn
);
1161 chan
->callback_fn
= rtn
;
1166 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn
);
1168 /* s3c2410_dma_devconfig
1170 * configure the dma source/destination hardware type and address
1172 * source: S3C2410_DMASRC_HW: source is hardware
1173 * S3C2410_DMASRC_MEM: source is memory
1175 * devaddr: physical address of the source
1178 int s3c2410_dma_devconfig(int channel
,
1179 enum s3c2410_dmasrc source
,
1180 unsigned long devaddr
)
1182 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1188 pr_debug("%s: source=%d, devaddr=%08lx\n",
1189 __func__
, (int)source
, devaddr
);
1191 chan
->source
= source
;
1192 chan
->dev_addr
= devaddr
;
1194 switch (chan
->req_ch
) {
1197 hwcfg
= 0; /* AHB */
1201 hwcfg
= S3C2410_DISRCC_APB
;
1204 /* always assume our peripheral desintation is a fixed
1205 * address in memory. */
1206 hwcfg
|= S3C2410_DISRCC_INC
;
1209 case S3C2410_DMASRC_HW
:
1210 /* source is hardware */
1211 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1212 __func__
, devaddr
, hwcfg
);
1213 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, hwcfg
& 3);
1214 dma_wrreg(chan
, S3C2410_DMA_DISRC
, devaddr
);
1215 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, (0<<1) | (0<<0));
1217 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DIDST
);
1220 case S3C2410_DMASRC_MEM
:
1221 /* source is memory */
1222 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1223 __func__
, devaddr
, hwcfg
);
1224 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, (0<<1) | (0<<0));
1225 dma_wrreg(chan
, S3C2410_DMA_DIDST
, devaddr
);
1226 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, hwcfg
& 3);
1228 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DISRC
);
1232 printk(KERN_ERR
"dma%d: invalid source type (%d)\n",
1238 if (dma_sel
.direction
!= NULL
)
1239 (dma_sel
.direction
)(chan
, chan
->map
, source
);
1244 EXPORT_SYMBOL(s3c2410_dma_devconfig
);
1246 /* s3c2410_dma_getposition
1248 * returns the current transfer points for the dma source and destination
1251 int s3c2410_dma_getposition(unsigned int channel
, dma_addr_t
*src
, dma_addr_t
*dst
)
1253 struct s3c2410_dma_chan
*chan
= lookup_dma_channel(channel
);
1259 *src
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
1262 *dst
= dma_rdreg(chan
, S3C2410_DMA_DCDST
);
1267 EXPORT_SYMBOL(s3c2410_dma_getposition
);
1269 static struct s3c2410_dma_chan
*to_dma_chan(struct sys_device
*dev
)
1271 return container_of(dev
, struct s3c2410_dma_chan
, dev
);
1274 /* system device class */
1278 static int s3c2410_dma_suspend(struct sys_device
*dev
, pm_message_t state
)
1280 struct s3c2410_dma_chan
*cp
= to_dma_chan(dev
);
1282 printk(KERN_DEBUG
"suspending dma channel %d\n", cp
->number
);
1284 if (dma_rdreg(cp
, S3C2410_DMA_DMASKTRIG
) & S3C2410_DMASKTRIG_ON
) {
1285 /* the dma channel is still working, which is probably
1286 * a bad thing to do over suspend/resume. We stop the
1287 * channel and assume that the client is either going to
1288 * retry after resume, or that it is broken.
1291 printk(KERN_INFO
"dma: stopping channel %d due to suspend\n",
1294 s3c2410_dma_dostop(cp
);
1300 static int s3c2410_dma_resume(struct sys_device
*dev
)
1302 struct s3c2410_dma_chan
*cp
= to_dma_chan(dev
);
1303 unsigned int no
= cp
->number
| DMACH_LOW_LEVEL
;
1305 /* restore channel's hardware configuration */
1310 printk(KERN_INFO
"dma%d: restoring configuration\n", cp
->number
);
1312 s3c2410_dma_config(no
, cp
->xfer_unit
);
1313 s3c2410_dma_devconfig(no
, cp
->source
, cp
->dev_addr
);
1315 /* re-select the dma source for this channel */
1317 if (cp
->map
!= NULL
)
1318 dma_sel
.select(cp
, cp
->map
);
1324 #define s3c2410_dma_suspend NULL
1325 #define s3c2410_dma_resume NULL
1326 #endif /* CONFIG_PM */
1328 struct sysdev_class dma_sysclass
= {
1329 .name
= "s3c24xx-dma",
1330 .suspend
= s3c2410_dma_suspend
,
1331 .resume
= s3c2410_dma_resume
,
1334 /* kmem cache implementation */
1336 static void s3c2410_dma_cache_ctor(void *p
)
1338 memset(p
, 0, sizeof(struct s3c2410_dma_buf
));
1341 /* initialisation code */
1343 static int __init
s3c24xx_dma_sysclass_init(void)
1345 int ret
= sysdev_class_register(&dma_sysclass
);
1348 printk(KERN_ERR
"dma sysclass registration failed\n");
1353 core_initcall(s3c24xx_dma_sysclass_init
);
1355 static int __init
s3c24xx_dma_sysdev_register(void)
1357 struct s3c2410_dma_chan
*cp
= s3c2410_chans
;
1360 for (channel
= 0; channel
< dma_channels
; cp
++, channel
++) {
1361 cp
->dev
.cls
= &dma_sysclass
;
1362 cp
->dev
.id
= channel
;
1363 ret
= sysdev_register(&cp
->dev
);
1366 printk(KERN_ERR
"error registering dev for dma %d\n",
1375 late_initcall(s3c24xx_dma_sysdev_register
);
1377 int __init
s3c24xx_dma_init(unsigned int channels
, unsigned int irq
,
1378 unsigned int stride
)
1380 struct s3c2410_dma_chan
*cp
;
1384 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1386 dma_channels
= channels
;
1388 dma_base
= ioremap(S3C24XX_PA_DMA
, stride
* channels
);
1389 if (dma_base
== NULL
) {
1390 printk(KERN_ERR
"dma failed to remap register block\n");
1394 dma_kmem
= kmem_cache_create("dma_desc",
1395 sizeof(struct s3c2410_dma_buf
), 0,
1397 s3c2410_dma_cache_ctor
);
1399 if (dma_kmem
== NULL
) {
1400 printk(KERN_ERR
"dma failed to make kmem cache\n");
1405 for (channel
= 0; channel
< channels
; channel
++) {
1406 cp
= &s3c2410_chans
[channel
];
1408 memset(cp
, 0, sizeof(struct s3c2410_dma_chan
));
1410 /* dma channel irqs are in order.. */
1411 cp
->number
= channel
;
1412 cp
->irq
= channel
+ irq
;
1413 cp
->regs
= dma_base
+ (channel
* stride
);
1415 /* point current stats somewhere */
1416 cp
->stats
= &cp
->stats_store
;
1417 cp
->stats_store
.timeout_shortest
= LONG_MAX
;
1419 /* basic channel configuration */
1421 cp
->load_timeout
= 1<<18;
1423 printk("DMA channel %d at %p, irq %d\n",
1424 cp
->number
, cp
->regs
, cp
->irq
);
1430 kmem_cache_destroy(dma_kmem
);
1436 int __init
s3c2410_dma_init(void)
1438 return s3c24xx_dma_init(4, IRQ_DMA0
, 0x40);
1441 static inline int is_channel_valid(unsigned int channel
)
1443 return (channel
& DMA_CH_VALID
);
1446 static struct s3c24xx_dma_order
*dma_order
;
1449 /* s3c2410_dma_map_channel()
1451 * turn the virtual channel number into a real, and un-used hardware
1454 * first, try the dma ordering given to us by either the relevant
1455 * dma code, or the board. Then just find the first usable free
1459 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
)
1461 struct s3c24xx_dma_order_ch
*ord
= NULL
;
1462 struct s3c24xx_dma_map
*ch_map
;
1463 struct s3c2410_dma_chan
*dmach
;
1466 if (dma_sel
.map
== NULL
|| channel
> dma_sel
.map_size
)
1469 ch_map
= dma_sel
.map
+ channel
;
1471 /* first, try the board mapping */
1474 ord
= &dma_order
->channels
[channel
];
1476 for (ch
= 0; ch
< dma_channels
; ch
++) {
1477 if (!is_channel_valid(ord
->list
[ch
]))
1480 if (s3c2410_chans
[ord
->list
[ch
]].in_use
== 0) {
1481 ch
= ord
->list
[ch
] & ~DMA_CH_VALID
;
1486 if (ord
->flags
& DMA_CH_NEVER
)
1490 /* second, search the channel map for first free */
1492 for (ch
= 0; ch
< dma_channels
; ch
++) {
1493 if (!is_channel_valid(ch_map
->channels
[ch
]))
1496 if (s3c2410_chans
[ch
].in_use
== 0) {
1497 printk("mapped channel %d to %d\n", channel
, ch
);
1502 if (ch
>= dma_channels
)
1505 /* update our channel mapping */
1508 dmach
= &s3c2410_chans
[ch
];
1509 dmach
->map
= ch_map
;
1510 dmach
->req_ch
= channel
;
1511 dma_chan_map
[channel
] = dmach
;
1513 /* select the channel */
1515 (dma_sel
.select
)(dmach
, ch_map
);
1520 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map
*map
, int ch
)
1525 int __init
s3c24xx_dma_init_map(struct s3c24xx_dma_selection
*sel
)
1527 struct s3c24xx_dma_map
*nmap
;
1528 size_t map_sz
= sizeof(*nmap
) * sel
->map_size
;
1531 nmap
= kmalloc(map_sz
, GFP_KERNEL
);
1535 memcpy(nmap
, sel
->map
, map_sz
);
1536 memcpy(&dma_sel
, sel
, sizeof(*sel
));
1540 for (ptr
= 0; ptr
< sel
->map_size
; ptr
++)
1541 s3c24xx_dma_check_entry(nmap
+ptr
, ptr
);
1546 int __init
s3c24xx_dma_order_set(struct s3c24xx_dma_order
*ord
)
1548 struct s3c24xx_dma_order
*nord
= dma_order
;
1551 nord
= kmalloc(sizeof(struct s3c24xx_dma_order
), GFP_KERNEL
);
1554 printk(KERN_ERR
"no memory to store dma channel order\n");
1559 memcpy(nord
, ord
, sizeof(struct s3c24xx_dma_order
));