arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_DEVMEM_IS_ALLOWED
   7         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   8         select ARCH_HAS_ELF_RANDOMIZE
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_HAS_SG_CHAIN
  11         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_SUPPORTS_ATOMIC_RMW
  14         select ARCH_WANT_OPTIONAL_GPIOLIB
  15         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  16         select ARCH_WANT_FRAME_POINTERS
  17         select ARM_AMBA
  18         select ARM_ARCH_TIMER
  19         select ARM_GIC
  20         select AUDIT_ARCH_COMPAT_GENERIC
  21         select ARM_GIC_V2M if PCI_MSI
  22         select ARM_GIC_V3
  23         select ARM_GIC_V3_ITS if PCI_MSI
  24         select ARM_PSCI_FW
  25         select BUILDTIME_EXTABLE_SORT
  26         select CLONE_BACKWARDS
  27         select COMMON_CLK
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS
  30         select EDAC_SUPPORT
  31         select FRAME_POINTER
  32         select GENERIC_ALLOCATOR
  33         select GENERIC_CLOCKEVENTS
  34         select GENERIC_CLOCKEVENTS_BROADCAST
  35         select GENERIC_CPU_AUTOPROBE
  36         select GENERIC_EARLY_IOREMAP
  37         select GENERIC_IDLE_POLL_SETUP
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_SHOW_LEVEL
  41         select GENERIC_PCI_IOMAP
  42         select GENERIC_SCHED_CLOCK
  43         select GENERIC_SMP_IDLE_THREAD
  44         select GENERIC_STRNCPY_FROM_USER
  45         select GENERIC_STRNLEN_USER
  46         select GENERIC_TIME_VSYSCALL
  47         select HANDLE_DOMAIN_IRQ
  48         select HARDIRQS_SW_RESEND
  49         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  50         select HAVE_ARCH_AUDITSYSCALL
  51         select HAVE_ARCH_BITREVERSE
  52         select HAVE_ARCH_JUMP_LABEL
  53         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
  54         select HAVE_ARCH_KGDB
  55         select HAVE_ARCH_MMAP_RND_BITS
  56         select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
  57         select HAVE_ARCH_SECCOMP_FILTER
  58         select HAVE_ARCH_TRACEHOOK
  59         select HAVE_BPF_JIT
  60         select HAVE_C_RECORDMCOUNT
  61         select HAVE_CC_STACKPROTECTOR
  62         select HAVE_CMPXCHG_DOUBLE
  63         select HAVE_CMPXCHG_LOCAL
  64         select HAVE_DEBUG_BUGVERBOSE
  65         select HAVE_DEBUG_KMEMLEAK
  66         select HAVE_DMA_API_DEBUG
  67         select HAVE_DMA_ATTRS
  68         select HAVE_DMA_CONTIGUOUS
  69         select HAVE_DYNAMIC_FTRACE
  70         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  71         select HAVE_FTRACE_MCOUNT_RECORD
  72         select HAVE_FUNCTION_TRACER
  73         select HAVE_FUNCTION_GRAPH_TRACER
  74         select HAVE_GENERIC_DMA_COHERENT
  75         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  76         select HAVE_IRQ_TIME_ACCOUNTING
  77         select HAVE_MEMBLOCK
  78         select HAVE_PATA_PLATFORM
  79         select HAVE_PERF_EVENTS
  80         select HAVE_PERF_REGS
  81         select HAVE_PERF_USER_STACK_DUMP
  82         select HAVE_RCU_TABLE_FREE
  83         select HAVE_SYSCALL_TRACEPOINTS
  84         select IOMMU_DMA if IOMMU_SUPPORT
  85         select IRQ_DOMAIN
  86         select IRQ_FORCED_THREADING
  87         select MODULES_USE_ELF_RELA
  88         select NO_BOOTMEM
  89         select OF
  90         select OF_EARLY_FLATTREE
  91         select OF_RESERVED_MEM
  92         select PERF_USE_VMALLOC
  93         select POWER_RESET
  94         select POWER_SUPPLY
  95         select RTC_LIB
  96         select SPARSE_IRQ
  97         select SYSCTL_EXCEPTION_TRACE
  98         select HAVE_CONTEXT_TRACKING
  99         select HAVE_ARM_SMCCC
 100         help
 101           ARM 64-bit (AArch64) Linux support.
 102
 103 config 64BIT
 104         def_bool y
 105
 106 config ARCH_PHYS_ADDR_T_64BIT
 107         def_bool y
 108
 109 config MMU
 110         def_bool y
 111
 112 config ARCH_MMAP_RND_BITS_MIN
 113        default 14 if ARM64_64K_PAGES
 114        default 16 if ARM64_16K_PAGES
 115        default 18
 116
 117 # max bits determined by the following formula:
 118 #  VA_BITS - PAGE_SHIFT - 3
 119 config ARCH_MMAP_RND_BITS_MAX
 120        default 19 if ARM64_VA_BITS=36
 121        default 24 if ARM64_VA_BITS=39
 122        default 27 if ARM64_VA_BITS=42
 123        default 30 if ARM64_VA_BITS=47
 124        default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 125        default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 126        default 33 if ARM64_VA_BITS=48
 127        default 14 if ARM64_64K_PAGES
 128        default 16 if ARM64_16K_PAGES
 129        default 18
 130
 131 config ARCH_MMAP_RND_COMPAT_BITS_MIN
 132        default 7 if ARM64_64K_PAGES
 133        default 9 if ARM64_16K_PAGES
 134        default 11
 135
 136 config ARCH_MMAP_RND_COMPAT_BITS_MAX
 137        default 16
 138
 139 config NO_IOPORT_MAP
 140         def_bool y if !PCI
 141
 142 config STACKTRACE_SUPPORT
 143         def_bool y
 144
 145 config ILLEGAL_POINTER_VALUE
 146         hex
 147         default 0xdead000000000000
 148
 149 config LOCKDEP_SUPPORT
 150         def_bool y
 151
 152 config TRACE_IRQFLAGS_SUPPORT
 153         def_bool y
 154
 155 config RWSEM_XCHGADD_ALGORITHM
 156         def_bool y
 157
 158 config GENERIC_BUG
 159         def_bool y
 160         depends on BUG
 161
 162 config GENERIC_BUG_RELATIVE_POINTERS
 163         def_bool y
 164         depends on GENERIC_BUG
 165
 166 config GENERIC_HWEIGHT
 167         def_bool y
 168
 169 config GENERIC_CSUM
 170         def_bool y
 171
 172 config GENERIC_CALIBRATE_DELAY
 173         def_bool y
 174
 175 config ZONE_DMA
 176         def_bool y
 177
 178 config HAVE_GENERIC_RCU_GUP
 179         def_bool y
 180
 181 config ARCH_DMA_ADDR_T_64BIT
 182         def_bool y
 183
 184 config NEED_DMA_MAP_STATE
 185         def_bool y
 186
 187 config NEED_SG_DMA_LENGTH
 188         def_bool y
 189
 190 config SMP
 191         def_bool y
 192
 193 config SWIOTLB
 194         def_bool y
 195
 196 config IOMMU_HELPER
 197         def_bool SWIOTLB
 198
 199 config KERNEL_MODE_NEON
 200         def_bool y
 201
 202 config FIX_EARLYCON_MEM
 203         def_bool y
 204
 205 config PGTABLE_LEVELS
 206         int
 207         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 208         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 209         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 210         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 211         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 212         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 213
 214 source "init/Kconfig"
 215
 216 source "kernel/Kconfig.freezer"
 217
 218 source "arch/arm64/Kconfig.platforms"
 219
 220 menu "Bus support"
 221
 222 config PCI
 223         bool "PCI support"
 224         help
 225           This feature enables support for PCI bus system. If you say Y
 226           here, the kernel will include drivers and infrastructure code
 227           to support PCI bus devices.
 228
 229 config PCI_DOMAINS
 230         def_bool PCI
 231
 232 config PCI_DOMAINS_GENERIC
 233         def_bool PCI
 234
 235 config PCI_SYSCALL
 236         def_bool PCI
 237
 238 source "drivers/pci/Kconfig"
 239 source "drivers/pci/pcie/Kconfig"
 240 source "drivers/pci/hotplug/Kconfig"
 241
 242 endmenu
 243
 244 menu "Kernel Features"
 245
 246 menu "ARM errata workarounds via the alternatives framework"
 247
 248 config ARM64_ERRATUM_826319
 249         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 250         default y
 251         help
 252           This option adds an alternative code sequence to work around ARM
 253           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 254           AXI master interface and an L2 cache.
 255
 256           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 257           and is unable to accept a certain write via this interface, it will
 258           not progress on read data presented on the read data channel and the
 259           system can deadlock.
 260
 261           The workaround promotes data cache clean instructions to
 262           data cache clean-and-invalidate.
 263           Please note that this does not necessarily enable the workaround,
 264           as it depends on the alternative framework, which will only patch
 265           the kernel if an affected CPU is detected.
 266
 267           If unsure, say Y.
 268
 269 config ARM64_ERRATUM_827319
 270         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 271         default y
 272         help
 273           This option adds an alternative code sequence to work around ARM
 274           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 275           master interface and an L2 cache.
 276
 277           Under certain conditions this erratum can cause a clean line eviction
 278           to occur at the same time as another transaction to the same address
 279           on the AMBA 5 CHI interface, which can cause data corruption if the
 280           interconnect reorders the two transactions.
 281
 282           The workaround promotes data cache clean instructions to
 283           data cache clean-and-invalidate.
 284           Please note that this does not necessarily enable the workaround,
 285           as it depends on the alternative framework, which will only patch
 286           the kernel if an affected CPU is detected.
 287
 288           If unsure, say Y.
 289
 290 config ARM64_ERRATUM_824069
 291         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 292         default y
 293         help
 294           This option adds an alternative code sequence to work around ARM
 295           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 296           to a coherent interconnect.
 297
 298           If a Cortex-A53 processor is executing a store or prefetch for
 299           write instruction at the same time as a processor in another
 300           cluster is executing a cache maintenance operation to the same
 301           address, then this erratum might cause a clean cache line to be
 302           incorrectly marked as dirty.
 303
 304           The workaround promotes data cache clean instructions to
 305           data cache clean-and-invalidate.
 306           Please note that this option does not necessarily enable the
 307           workaround, as it depends on the alternative framework, which will
 308           only patch the kernel if an affected CPU is detected.
 309
 310           If unsure, say Y.
 311
 312 config ARM64_ERRATUM_819472
 313         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 314         default y
 315         help
 316           This option adds an alternative code sequence to work around ARM
 317           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 318           present when it is connected to a coherent interconnect.
 319
 320           If the processor is executing a load and store exclusive sequence at
 321           the same time as a processor in another cluster is executing a cache
 322           maintenance operation to the same address, then this erratum might
 323           cause data corruption.
 324
 325           The workaround promotes data cache clean instructions to
 326           data cache clean-and-invalidate.
 327           Please note that this does not necessarily enable the workaround,
 328           as it depends on the alternative framework, which will only patch
 329           the kernel if an affected CPU is detected.
 330
 331           If unsure, say Y.
 332
 333 config ARM64_ERRATUM_832075
 334         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 335         default y
 336         help
 337           This option adds an alternative code sequence to work around ARM
 338           erratum 832075 on Cortex-A57 parts up to r1p2.
 339
 340           Affected Cortex-A57 parts might deadlock when exclusive load/store
 341           instructions to Write-Back memory are mixed with Device loads.
 342
 343           The workaround is to promote device loads to use Load-Acquire
 344           semantics.
 345           Please note that this does not necessarily enable the workaround,
 346           as it depends on the alternative framework, which will only patch
 347           the kernel if an affected CPU is detected.
 348
 349           If unsure, say Y.
 350
 351 config ARM64_ERRATUM_834220
 352         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 353         depends on KVM
 354         default y
 355         help
 356           This option adds an alternative code sequence to work around ARM
 357           erratum 834220 on Cortex-A57 parts up to r1p2.
 358
 359           Affected Cortex-A57 parts might report a Stage 2 translation
 360           fault as the result of a Stage 1 fault for load crossing a
 361           page boundary when there is a permission or device memory
 362           alignment fault at Stage 1 and a translation fault at Stage 2.
 363
 364           The workaround is to verify that the Stage 1 translation
 365           doesn't generate a fault before handling the Stage 2 fault.
 366           Please note that this does not necessarily enable the workaround,
 367           as it depends on the alternative framework, which will only patch
 368           the kernel if an affected CPU is detected.
 369
 370           If unsure, say Y.
 371
 372 config ARM64_ERRATUM_845719
 373         bool "Cortex-A53: 845719: a load might read incorrect data"
 374         depends on COMPAT
 375         default y
 376         help
 377           This option adds an alternative code sequence to work around ARM
 378           erratum 845719 on Cortex-A53 parts up to r0p4.
 379
 380           When running a compat (AArch32) userspace on an affected Cortex-A53
 381           part, a load at EL0 from a virtual address that matches the bottom 32
 382           bits of the virtual address used by a recent load at (AArch64) EL1
 383           might return incorrect data.
 384
 385           The workaround is to write the contextidr_el1 register on exception
 386           return to a 32-bit task.
 387           Please note that this does not necessarily enable the workaround,
 388           as it depends on the alternative framework, which will only patch
 389           the kernel if an affected CPU is detected.
 390
 391           If unsure, say Y.
 392
 393 config ARM64_ERRATUM_843419
 394         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 395         depends on MODULES
 396         default y
 397         help
 398           This option builds kernel modules using the large memory model in
 399           order to avoid the use of the ADRP instruction, which can cause
 400           a subsequent memory access to use an incorrect address on Cortex-A53
 401           parts up to r0p4.
 402
 403           Note that the kernel itself must be linked with a version of ld
 404           which fixes potentially affected ADRP instructions through the
 405           use of veneers.
 406
 407           If unsure, say Y.
 408
 409 config CAVIUM_ERRATUM_22375
 410         bool "Cavium erratum 22375, 24313"
 411         default y
 412         help
 413           Enable workaround for erratum 22375, 24313.
 414
 415           This implements two gicv3-its errata workarounds for ThunderX. Both
 416           with small impact affecting only ITS table allocation.
 417
 418             erratum 22375: only alloc 8MB table size
 419             erratum 24313: ignore memory access type
 420
 421           The fixes are in ITS initialization and basically ignore memory access
 422           type and table size provided by the TYPER and BASER registers.
 423
 424           If unsure, say Y.
 425
 426 config CAVIUM_ERRATUM_23154
 427         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 428         default y
 429         help
 430           The gicv3 of ThunderX requires a modified version for
 431           reading the IAR status to ensure data synchronization
 432           (access to icc_iar1_el1 is not sync'ed before and after).
 433
 434           If unsure, say Y.
 435
 436 endmenu
 437
 438
 439 choice
 440         prompt "Page size"
 441         default ARM64_4K_PAGES
 442         help
 443           Page size (translation granule) configuration.
 444
 445 config ARM64_4K_PAGES
 446         bool "4KB"
 447         help
 448           This feature enables 4KB pages support.
 449
 450 config ARM64_16K_PAGES
 451         bool "16KB"
 452         help
 453           The system will use 16KB pages support. AArch32 emulation
 454           requires applications compiled with 16K (or a multiple of 16K)
 455           aligned segments.
 456
 457 config ARM64_64K_PAGES
 458         bool "64KB"
 459         help
 460           This feature enables 64KB pages support (4KB by default)
 461           allowing only two levels of page tables and faster TLB
 462           look-up. AArch32 emulation requires applications compiled
 463           with 64K aligned segments.
 464
 465 endchoice
 466
 467 choice
 468         prompt "Virtual address space size"
 469         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 470         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 471         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 472         help
 473           Allows choosing one of multiple possible virtual address
 474           space sizes. The level of translation table is determined by
 475           a combination of page size and virtual address space size.
 476
 477 config ARM64_VA_BITS_36
 478         bool "36-bit" if EXPERT
 479         depends on ARM64_16K_PAGES
 480
 481 config ARM64_VA_BITS_39
 482         bool "39-bit"
 483         depends on ARM64_4K_PAGES
 484
 485 config ARM64_VA_BITS_42
 486         bool "42-bit"
 487         depends on ARM64_64K_PAGES
 488
 489 config ARM64_VA_BITS_47
 490         bool "47-bit"
 491         depends on ARM64_16K_PAGES
 492
 493 config ARM64_VA_BITS_48
 494         bool "48-bit"
 495
 496 endchoice
 497
 498 config ARM64_VA_BITS
 499         int
 500         default 36 if ARM64_VA_BITS_36
 501         default 39 if ARM64_VA_BITS_39
 502         default 42 if ARM64_VA_BITS_42
 503         default 47 if ARM64_VA_BITS_47
 504         default 48 if ARM64_VA_BITS_48
 505
 506 config CPU_BIG_ENDIAN
 507        bool "Build big-endian kernel"
 508        help
 509          Say Y if you plan on running a kernel in big-endian mode.
 510
 511 config SCHED_MC
 512         bool "Multi-core scheduler support"
 513         help
 514           Multi-core scheduler support improves the CPU scheduler's decision
 515           making when dealing with multi-core CPU chips at a cost of slightly
 516           increased overhead in some places. If unsure say N here.
 517
 518 config SCHED_SMT
 519         bool "SMT scheduler support"
 520         help
 521           Improves the CPU scheduler's decision making when dealing with
 522           MultiThreading at a cost of slightly increased overhead in some
 523           places. If unsure say N here.
 524
 525 config NR_CPUS
 526         int "Maximum number of CPUs (2-4096)"
 527         range 2 4096
 528         # These have to remain sorted largest to smallest
 529         default "64"
 530
 531 config HOTPLUG_CPU
 532         bool "Support for hot-pluggable CPUs"
 533         select GENERIC_IRQ_MIGRATION
 534         help
 535           Say Y here to experiment with turning CPUs off and on.  CPUs
 536           can be controlled through /sys/devices/system/cpu.
 537
 538 source kernel/Kconfig.preempt
 539 source kernel/Kconfig.hz
 540
 541 config ARCH_HAS_HOLES_MEMORYMODEL
 542         def_bool y if SPARSEMEM
 543
 544 config ARCH_SPARSEMEM_ENABLE
 545         def_bool y
 546         select SPARSEMEM_VMEMMAP_ENABLE
 547
 548 config ARCH_SPARSEMEM_DEFAULT
 549         def_bool ARCH_SPARSEMEM_ENABLE
 550
 551 config ARCH_SELECT_MEMORY_MODEL
 552         def_bool ARCH_SPARSEMEM_ENABLE
 553
 554 config HAVE_ARCH_PFN_VALID
 555         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 556
 557 config HW_PERF_EVENTS
 558         def_bool y
 559         depends on ARM_PMU
 560
 561 config SYS_SUPPORTS_HUGETLBFS
 562         def_bool y
 563
 564 config ARCH_WANT_HUGE_PMD_SHARE
 565         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 566
 567 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 568         def_bool y
 569
 570 config ARCH_HAS_CACHE_LINE_SIZE
 571         def_bool y
 572
 573 source "mm/Kconfig"
 574
 575 config SECCOMP
 576         bool "Enable seccomp to safely compute untrusted bytecode"
 577         ---help---
 578           This kernel feature is useful for number crunching applications
 579           that may need to compute untrusted bytecode during their
 580           execution. By using pipes or other transports made available to
 581           the process as file descriptors supporting the read/write
 582           syscalls, it's possible to isolate those applications in
 583           their own address space using seccomp. Once seccomp is
 584           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 585           and the task is only allowed to execute a few safe syscalls
 586           defined by each seccomp mode.
 587
 588 config PARAVIRT
 589         bool "Enable paravirtualization code"
 590         help
 591           This changes the kernel so it can modify itself when it is run
 592           under a hypervisor, potentially improving performance significantly
 593           over full virtualization.
 594
 595 config PARAVIRT_TIME_ACCOUNTING
 596         bool "Paravirtual steal time accounting"
 597         select PARAVIRT
 598         default n
 599         help
 600           Select this option to enable fine granularity task steal time
 601           accounting. Time spent executing other tasks in parallel with
 602           the current vCPU is discounted from the vCPU power. To account for
 603           that, there can be a small performance impact.
 604
 605           If in doubt, say N here.
 606
 607 config XEN_DOM0
 608         def_bool y
 609         depends on XEN
 610
 611 config XEN
 612         bool "Xen guest support on ARM64"
 613         depends on ARM64 && OF
 614         select SWIOTLB_XEN
 615         select PARAVIRT
 616         help
 617           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 618
 619 config FORCE_MAX_ZONEORDER
 620         int
 621         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 622         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 623         default "11"
 624         help
 625           The kernel memory allocator divides physically contiguous memory
 626           blocks into "zones", where each zone is a power of two number of
 627           pages.  This option selects the largest power of two that the kernel
 628           keeps in the memory allocator.  If you need to allocate very large
 629           blocks of physically contiguous memory, then you may need to
 630           increase this value.
 631
 632           This config option is actually maximum order plus one. For example,
 633           a value of 11 means that the largest free memory block is 2^10 pages.
 634
 635           We make sure that we can allocate upto a HugePage size for each configuration.
 636           Hence we have :
 637                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 638
 639           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 640           4M allocations matching the default size used by generic code.
 641
 642 menuconfig ARMV8_DEPRECATED
 643         bool "Emulate deprecated/obsolete ARMv8 instructions"
 644         depends on COMPAT
 645         help
 646           Legacy software support may require certain instructions
 647           that have been deprecated or obsoleted in the architecture.
 648
 649           Enable this config to enable selective emulation of these
 650           features.
 651
 652           If unsure, say Y
 653
 654 if ARMV8_DEPRECATED
 655
 656 config SWP_EMULATION
 657         bool "Emulate SWP/SWPB instructions"
 658         help
 659           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 660           they are always undefined. Say Y here to enable software
 661           emulation of these instructions for userspace using LDXR/STXR.
 662
 663           In some older versions of glibc [<=2.8] SWP is used during futex
 664           trylock() operations with the assumption that the code will not
 665           be preempted. This invalid assumption may be more likely to fail
 666           with SWP emulation enabled, leading to deadlock of the user
 667           application.
 668
 669           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 670           on an external transaction monitoring block called a global
 671           monitor to maintain update atomicity. If your system does not
 672           implement a global monitor, this option can cause programs that
 673           perform SWP operations to uncached memory to deadlock.
 674
 675           If unsure, say Y
 676
 677 config CP15_BARRIER_EMULATION
 678         bool "Emulate CP15 Barrier instructions"
 679         help
 680           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 681           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 682           strongly recommended to use the ISB, DSB, and DMB
 683           instructions instead.
 684
 685           Say Y here to enable software emulation of these
 686           instructions for AArch32 userspace code. When this option is
 687           enabled, CP15 barrier usage is traced which can help
 688           identify software that needs updating.
 689
 690           If unsure, say Y
 691
 692 config SETEND_EMULATION
 693         bool "Emulate SETEND instruction"
 694         help
 695           The SETEND instruction alters the data-endianness of the
 696           AArch32 EL0, and is deprecated in ARMv8.
 697
 698           Say Y here to enable software emulation of the instruction
 699           for AArch32 userspace code.
 700
 701           Note: All the cpus on the system must have mixed endian support at EL0
 702           for this feature to be enabled. If a new CPU - which doesn't support mixed
 703           endian - is hotplugged in after this feature has been enabled, there could
 704           be unexpected results in the applications.
 705
 706           If unsure, say Y
 707 endif
 708
 709 menu "ARMv8.1 architectural features"
 710
 711 config ARM64_HW_AFDBM
 712         bool "Support for hardware updates of the Access and Dirty page flags"
 713         default y
 714         help
 715           The ARMv8.1 architecture extensions introduce support for
 716           hardware updates of the access and dirty information in page
 717           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 718           capable processors, accesses to pages with PTE_AF cleared will
 719           set this bit instead of raising an access flag fault.
 720           Similarly, writes to read-only pages with the DBM bit set will
 721           clear the read-only bit (AP[2]) instead of raising a
 722           permission fault.
 723
 724           Kernels built with this configuration option enabled continue
 725           to work on pre-ARMv8.1 hardware and the performance impact is
 726           minimal. If unsure, say Y.
 727
 728 config ARM64_PAN
 729         bool "Enable support for Privileged Access Never (PAN)"
 730         default y
 731         help
 732          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 733          prevents the kernel or hypervisor from accessing user-space (EL0)
 734          memory directly.
 735
 736          Choosing this option will cause any unprotected (not using
 737          copy_to_user et al) memory access to fail with a permission fault.
 738
 739          The feature is detected at runtime, and will remain as a 'nop'
 740          instruction if the cpu does not implement the feature.
 741
 742 config ARM64_LSE_ATOMICS
 743         bool "Atomic instructions"
 744         help
 745           As part of the Large System Extensions, ARMv8.1 introduces new
 746           atomic instructions that are designed specifically to scale in
 747           very large systems.
 748
 749           Say Y here to make use of these instructions for the in-kernel
 750           atomic routines. This incurs a small overhead on CPUs that do
 751           not support these instructions and requires the kernel to be
 752           built with binutils >= 2.25.
 753
 754 endmenu
 755
 756 endmenu
 757
 758 menu "Boot options"
 759
 760 config CMDLINE
 761         string "Default kernel command string"
 762         default ""
 763         help
 764           Provide a set of default command-line options at build time by
 765           entering them here. As a minimum, you should specify the the
 766           root device (e.g. root=/dev/nfs).
 767
 768 config CMDLINE_FORCE
 769         bool "Always use the default kernel command string"
 770         help
 771           Always use the default kernel command string, even if the boot
 772           loader passes other arguments to the kernel.
 773           This is useful if you cannot or don't want to change the
 774           command-line options your boot loader passes to the kernel.
 775
 776 config EFI_STUB
 777         bool
 778
 779 config EFI
 780         bool "UEFI runtime support"
 781         depends on OF && !CPU_BIG_ENDIAN
 782         select LIBFDT
 783         select UCS2_STRING
 784         select EFI_PARAMS_FROM_FDT
 785         select EFI_RUNTIME_WRAPPERS
 786         select EFI_STUB
 787         select EFI_ARMSTUB
 788         default y
 789         help
 790           This option provides support for runtime services provided
 791           by UEFI firmware (such as non-volatile variables, realtime
 792           clock, and platform reset). A UEFI stub is also provided to
 793           allow the kernel to be booted as an EFI application. This
 794           is only useful on systems that have UEFI firmware.
 795
 796 config DMI
 797         bool "Enable support for SMBIOS (DMI) tables"
 798         depends on EFI
 799         default y
 800         help
 801           This enables SMBIOS/DMI feature for systems.
 802
 803           This option is only useful on systems that have UEFI firmware.
 804           However, even with this option, the resultant kernel should
 805           continue to boot on existing non-UEFI platforms.
 806
 807 endmenu
 808
 809 menu "Userspace binary formats"
 810
 811 source "fs/Kconfig.binfmt"
 812
 813 config COMPAT
 814         bool "Kernel support for 32-bit EL0"
 815         depends on ARM64_4K_PAGES || EXPERT
 816         select COMPAT_BINFMT_ELF
 817         select HAVE_UID16
 818         select OLD_SIGSUSPEND3
 819         select COMPAT_OLD_SIGACTION
 820         help
 821           This option enables support for a 32-bit EL0 running under a 64-bit
 822           kernel at EL1. AArch32-specific components such as system calls,
 823           the user helper functions, VFP support and the ptrace interface are
 824           handled appropriately by the kernel.
 825
 826           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
 827           that you will only be able to execute AArch32 binaries that were compiled
 828           with page size aligned segments.
 829
 830           If you want to execute 32-bit userspace applications, say Y.
 831
 832 config SYSVIPC_COMPAT
 833         def_bool y
 834         depends on COMPAT && SYSVIPC
 835
 836 endmenu
 837
 838 menu "Power management options"
 839
 840 source "kernel/power/Kconfig"
 841
 842 config ARCH_SUSPEND_POSSIBLE
 843         def_bool y
 844
 845 endmenu
 846
 847 menu "CPU Power Management"
 848
 849 source "drivers/cpuidle/Kconfig"
 850
 851 source "drivers/cpufreq/Kconfig"
 852
 853 endmenu
 854
 855 source "net/Kconfig"
 856
 857 source "drivers/Kconfig"
 858
 859 source "drivers/firmware/Kconfig"
 860
 861 source "drivers/acpi/Kconfig"
 862
 863 source "fs/Kconfig"
 864
 865 source "arch/arm64/kvm/Kconfig"
 866
 867 source "arch/arm64/Kconfig.debug"
 868
 869 source "security/Kconfig"
 870
 871 source "crypto/Kconfig"
 872 if CRYPTO
 873 source "arch/arm64/crypto/Kconfig"
 874 endif
 875
 876 source "lib/Kconfig"