3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
8 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_HAS_SG_CHAIN
13 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
14 select ARCH_USE_CMPXCHG_LOCKREF
15 select ARCH_SUPPORTS_ATOMIC_RMW
16 select ARCH_SUPPORTS_NUMA_BALANCING
17 select ARCH_WANT_OPTIONAL_GPIOLIB
18 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
19 select ARCH_WANT_FRAME_POINTERS
20 select ARCH_HAS_UBSAN_SANITIZE_ALL
24 select AUDIT_ARCH_COMPAT_GENERIC
25 select ARM_GIC_V2M if PCI_MSI
27 select ARM_GIC_V3_ITS if PCI_MSI
29 select BUILDTIME_EXTABLE_SORT
30 select CLONE_BACKWARDS
32 select CPU_PM if (SUSPEND || CPU_IDLE)
33 select DCACHE_WORD_ACCESS
36 select GENERIC_ALLOCATOR
37 select GENERIC_CLOCKEVENTS
38 select GENERIC_CLOCKEVENTS_BROADCAST
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select GENERIC_TIME_VSYSCALL
51 select HANDLE_DOMAIN_IRQ
52 select HARDIRQS_SW_RESEND
53 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
54 select HAVE_ARCH_AUDITSYSCALL
55 select HAVE_ARCH_BITREVERSE
56 select HAVE_ARCH_HUGE_VMAP
57 select HAVE_ARCH_JUMP_LABEL
58 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
60 select HAVE_ARCH_MMAP_RND_BITS
61 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
62 select HAVE_ARCH_SECCOMP_FILTER
63 select HAVE_ARCH_TRACEHOOK
64 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
67 select HAVE_C_RECORDMCOUNT
68 select HAVE_CC_STACKPROTECTOR
69 select HAVE_CMPXCHG_DOUBLE
70 select HAVE_CMPXCHG_LOCAL
71 select HAVE_CONTEXT_TRACKING
72 select HAVE_DEBUG_BUGVERBOSE
73 select HAVE_DEBUG_KMEMLEAK
74 select HAVE_DMA_API_DEBUG
75 select HAVE_DMA_CONTIGUOUS
76 select HAVE_DYNAMIC_FTRACE
77 select HAVE_EFFICIENT_UNALIGNED_ACCESS
78 select HAVE_FTRACE_MCOUNT_RECORD
79 select HAVE_FUNCTION_TRACER
80 select HAVE_FUNCTION_GRAPH_TRACER
81 select HAVE_GENERIC_DMA_COHERENT
82 select HAVE_HW_BREAKPOINT if PERF_EVENTS
83 select HAVE_IRQ_TIME_ACCOUNTING
85 select HAVE_MEMBLOCK_NODE_MAP if NUMA
86 select HAVE_PATA_PLATFORM
87 select HAVE_PERF_EVENTS
89 select HAVE_PERF_USER_STACK_DUMP
90 select HAVE_REGS_AND_STACK_ACCESS_API
91 select HAVE_RCU_TABLE_FREE
92 select HAVE_SYSCALL_TRACEPOINTS
94 select HAVE_KRETPROBES if HAVE_KPROBES
95 select IOMMU_DMA if IOMMU_SUPPORT
97 select IRQ_FORCED_THREADING
98 select MODULES_USE_ELF_RELA
101 select OF_EARLY_FLATTREE
102 select OF_NUMA if NUMA && OF
103 select OF_RESERVED_MEM
104 select PERF_USE_VMALLOC
108 select SYSCTL_EXCEPTION_TRACE
110 ARM 64-bit (AArch64) Linux support.
115 config ARCH_PHYS_ADDR_T_64BIT
121 config ARM64_PAGE_SHIFT
123 default 16 if ARM64_64K_PAGES
124 default 14 if ARM64_16K_PAGES
127 config ARM64_CONT_SHIFT
129 default 5 if ARM64_64K_PAGES
130 default 7 if ARM64_16K_PAGES
133 config ARCH_MMAP_RND_BITS_MIN
134 default 14 if ARM64_64K_PAGES
135 default 16 if ARM64_16K_PAGES
138 # max bits determined by the following formula:
139 # VA_BITS - PAGE_SHIFT - 3
140 config ARCH_MMAP_RND_BITS_MAX
141 default 19 if ARM64_VA_BITS=36
142 default 24 if ARM64_VA_BITS=39
143 default 27 if ARM64_VA_BITS=42
144 default 30 if ARM64_VA_BITS=47
145 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
146 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
147 default 33 if ARM64_VA_BITS=48
148 default 14 if ARM64_64K_PAGES
149 default 16 if ARM64_16K_PAGES
152 config ARCH_MMAP_RND_COMPAT_BITS_MIN
153 default 7 if ARM64_64K_PAGES
154 default 9 if ARM64_16K_PAGES
157 config ARCH_MMAP_RND_COMPAT_BITS_MAX
163 config STACKTRACE_SUPPORT
166 config ILLEGAL_POINTER_VALUE
168 default 0xdead000000000000
170 config LOCKDEP_SUPPORT
173 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
183 config GENERIC_BUG_RELATIVE_POINTERS
185 depends on GENERIC_BUG
187 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
199 config HAVE_GENERIC_RCU_GUP
202 config ARCH_DMA_ADDR_T_64BIT
205 config NEED_DMA_MAP_STATE
208 config NEED_SG_DMA_LENGTH
220 config KERNEL_MODE_NEON
223 config FIX_EARLYCON_MEM
226 config PGTABLE_LEVELS
228 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
229 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
230 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
231 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
232 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
233 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
235 source "init/Kconfig"
237 source "kernel/Kconfig.freezer"
239 source "arch/arm64/Kconfig.platforms"
246 This feature enables support for PCI bus system. If you say Y
247 here, the kernel will include drivers and infrastructure code
248 to support PCI bus devices.
253 config PCI_DOMAINS_GENERIC
259 source "drivers/pci/Kconfig"
263 menu "Kernel Features"
265 menu "ARM errata workarounds via the alternatives framework"
267 config ARM64_ERRATUM_826319
268 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
271 This option adds an alternative code sequence to work around ARM
272 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
273 AXI master interface and an L2 cache.
275 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
276 and is unable to accept a certain write via this interface, it will
277 not progress on read data presented on the read data channel and the
280 The workaround promotes data cache clean instructions to
281 data cache clean-and-invalidate.
282 Please note that this does not necessarily enable the workaround,
283 as it depends on the alternative framework, which will only patch
284 the kernel if an affected CPU is detected.
288 config ARM64_ERRATUM_827319
289 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
292 This option adds an alternative code sequence to work around ARM
293 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
294 master interface and an L2 cache.
296 Under certain conditions this erratum can cause a clean line eviction
297 to occur at the same time as another transaction to the same address
298 on the AMBA 5 CHI interface, which can cause data corruption if the
299 interconnect reorders the two transactions.
301 The workaround promotes data cache clean instructions to
302 data cache clean-and-invalidate.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
309 config ARM64_ERRATUM_824069
310 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
313 This option adds an alternative code sequence to work around ARM
314 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
315 to a coherent interconnect.
317 If a Cortex-A53 processor is executing a store or prefetch for
318 write instruction at the same time as a processor in another
319 cluster is executing a cache maintenance operation to the same
320 address, then this erratum might cause a clean cache line to be
321 incorrectly marked as dirty.
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this option does not necessarily enable the
326 workaround, as it depends on the alternative framework, which will
327 only patch the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_819472
332 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
335 This option adds an alternative code sequence to work around ARM
336 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
337 present when it is connected to a coherent interconnect.
339 If the processor is executing a load and store exclusive sequence at
340 the same time as a processor in another cluster is executing a cache
341 maintenance operation to the same address, then this erratum might
342 cause data corruption.
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_832075
353 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
356 This option adds an alternative code sequence to work around ARM
357 erratum 832075 on Cortex-A57 parts up to r1p2.
359 Affected Cortex-A57 parts might deadlock when exclusive load/store
360 instructions to Write-Back memory are mixed with Device loads.
362 The workaround is to promote device loads to use Load-Acquire
364 Please note that this does not necessarily enable the workaround,
365 as it depends on the alternative framework, which will only patch
366 the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_834220
371 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
375 This option adds an alternative code sequence to work around ARM
376 erratum 834220 on Cortex-A57 parts up to r1p2.
378 Affected Cortex-A57 parts might report a Stage 2 translation
379 fault as the result of a Stage 1 fault for load crossing a
380 page boundary when there is a permission or device memory
381 alignment fault at Stage 1 and a translation fault at Stage 2.
383 The workaround is to verify that the Stage 1 translation
384 doesn't generate a fault before handling the Stage 2 fault.
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_845719
392 bool "Cortex-A53: 845719: a load might read incorrect data"
396 This option adds an alternative code sequence to work around ARM
397 erratum 845719 on Cortex-A53 parts up to r0p4.
399 When running a compat (AArch32) userspace on an affected Cortex-A53
400 part, a load at EL0 from a virtual address that matches the bottom 32
401 bits of the virtual address used by a recent load at (AArch64) EL1
402 might return incorrect data.
404 The workaround is to write the contextidr_el1 register on exception
405 return to a 32-bit task.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_843419
413 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
416 select ARM64_MODULE_CMODEL_LARGE
418 This option builds kernel modules using the large memory model in
419 order to avoid the use of the ADRP instruction, which can cause
420 a subsequent memory access to use an incorrect address on Cortex-A53
423 Note that the kernel itself must be linked with a version of ld
424 which fixes potentially affected ADRP instructions through the
429 config CAVIUM_ERRATUM_22375
430 bool "Cavium erratum 22375, 24313"
433 Enable workaround for erratum 22375, 24313.
435 This implements two gicv3-its errata workarounds for ThunderX. Both
436 with small impact affecting only ITS table allocation.
438 erratum 22375: only alloc 8MB table size
439 erratum 24313: ignore memory access type
441 The fixes are in ITS initialization and basically ignore memory access
442 type and table size provided by the TYPER and BASER registers.
446 config CAVIUM_ERRATUM_23144
447 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
451 ITS SYNC command hang for cross node io and collections/cpu mapping.
455 config CAVIUM_ERRATUM_23154
456 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
459 The gicv3 of ThunderX requires a modified version for
460 reading the IAR status to ensure data synchronization
461 (access to icc_iar1_el1 is not sync'ed before and after).
465 config CAVIUM_ERRATUM_27456
466 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
469 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
470 instructions may cause the icache to become corrupted if it
471 contains data for a non-current ASID. The fix is to
472 invalidate the icache when changing the mm context.
481 default ARM64_4K_PAGES
483 Page size (translation granule) configuration.
485 config ARM64_4K_PAGES
488 This feature enables 4KB pages support.
490 config ARM64_16K_PAGES
493 The system will use 16KB pages support. AArch32 emulation
494 requires applications compiled with 16K (or a multiple of 16K)
497 config ARM64_64K_PAGES
500 This feature enables 64KB pages support (4KB by default)
501 allowing only two levels of page tables and faster TLB
502 look-up. AArch32 emulation requires applications compiled
503 with 64K aligned segments.
508 prompt "Virtual address space size"
509 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
510 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
511 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
513 Allows choosing one of multiple possible virtual address
514 space sizes. The level of translation table is determined by
515 a combination of page size and virtual address space size.
517 config ARM64_VA_BITS_36
518 bool "36-bit" if EXPERT
519 depends on ARM64_16K_PAGES
521 config ARM64_VA_BITS_39
523 depends on ARM64_4K_PAGES
525 config ARM64_VA_BITS_42
527 depends on ARM64_64K_PAGES
529 config ARM64_VA_BITS_47
531 depends on ARM64_16K_PAGES
533 config ARM64_VA_BITS_48
540 default 36 if ARM64_VA_BITS_36
541 default 39 if ARM64_VA_BITS_39
542 default 42 if ARM64_VA_BITS_42
543 default 47 if ARM64_VA_BITS_47
544 default 48 if ARM64_VA_BITS_48
546 config CPU_BIG_ENDIAN
547 bool "Build big-endian kernel"
549 Say Y if you plan on running a kernel in big-endian mode.
552 bool "Multi-core scheduler support"
554 Multi-core scheduler support improves the CPU scheduler's decision
555 making when dealing with multi-core CPU chips at a cost of slightly
556 increased overhead in some places. If unsure say N here.
559 bool "SMT scheduler support"
561 Improves the CPU scheduler's decision making when dealing with
562 MultiThreading at a cost of slightly increased overhead in some
563 places. If unsure say N here.
566 int "Maximum number of CPUs (2-4096)"
568 # These have to remain sorted largest to smallest
572 bool "Support for hot-pluggable CPUs"
573 select GENERIC_IRQ_MIGRATION
575 Say Y here to experiment with turning CPUs off and on. CPUs
576 can be controlled through /sys/devices/system/cpu.
578 # Common NUMA Features
580 bool "Numa Memory Allocation and Scheduler Support"
583 Enable NUMA (Non Uniform Memory Access) support.
585 The kernel will try to allocate memory used by a CPU on the
586 local memory of the CPU and add some more
587 NUMA awareness to the kernel.
590 int "Maximum NUMA Nodes (as a power of 2)"
593 depends on NEED_MULTIPLE_NODES
595 Specify the maximum number of NUMA Nodes available on the target
596 system. Increases memory reserved to accommodate various tables.
598 config USE_PERCPU_NUMA_NODE_ID
602 source kernel/Kconfig.preempt
603 source kernel/Kconfig.hz
605 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
606 depends on !HIBERNATION
609 config ARCH_HAS_HOLES_MEMORYMODEL
610 def_bool y if SPARSEMEM
612 config ARCH_SPARSEMEM_ENABLE
614 select SPARSEMEM_VMEMMAP_ENABLE
616 config ARCH_SPARSEMEM_DEFAULT
617 def_bool ARCH_SPARSEMEM_ENABLE
619 config ARCH_SELECT_MEMORY_MODEL
620 def_bool ARCH_SPARSEMEM_ENABLE
622 config HAVE_ARCH_PFN_VALID
623 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
625 config HW_PERF_EVENTS
629 config SYS_SUPPORTS_HUGETLBFS
632 config ARCH_WANT_HUGE_PMD_SHARE
633 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
635 config ARCH_HAS_CACHE_LINE_SIZE
641 bool "Enable seccomp to safely compute untrusted bytecode"
643 This kernel feature is useful for number crunching applications
644 that may need to compute untrusted bytecode during their
645 execution. By using pipes or other transports made available to
646 the process as file descriptors supporting the read/write
647 syscalls, it's possible to isolate those applications in
648 their own address space using seccomp. Once seccomp is
649 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
650 and the task is only allowed to execute a few safe syscalls
651 defined by each seccomp mode.
654 bool "Enable paravirtualization code"
656 This changes the kernel so it can modify itself when it is run
657 under a hypervisor, potentially improving performance significantly
658 over full virtualization.
660 config PARAVIRT_TIME_ACCOUNTING
661 bool "Paravirtual steal time accounting"
665 Select this option to enable fine granularity task steal time
666 accounting. Time spent executing other tasks in parallel with
667 the current vCPU is discounted from the vCPU power. To account for
668 that, there can be a small performance impact.
670 If in doubt, say N here.
673 depends on PM_SLEEP_SMP
675 bool "kexec system call"
677 kexec is a system call that implements the ability to shutdown your
678 current kernel, and to start another kernel. It is like a reboot
679 but it is independent of the system firmware. And like a reboot
680 you can start any kernel with it, not just Linux.
687 bool "Xen guest support on ARM64"
688 depends on ARM64 && OF
692 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
694 config FORCE_MAX_ZONEORDER
696 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
697 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
700 The kernel memory allocator divides physically contiguous memory
701 blocks into "zones", where each zone is a power of two number of
702 pages. This option selects the largest power of two that the kernel
703 keeps in the memory allocator. If you need to allocate very large
704 blocks of physically contiguous memory, then you may need to
707 This config option is actually maximum order plus one. For example,
708 a value of 11 means that the largest free memory block is 2^10 pages.
710 We make sure that we can allocate upto a HugePage size for each configuration.
712 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
714 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
715 4M allocations matching the default size used by generic code.
717 menuconfig ARMV8_DEPRECATED
718 bool "Emulate deprecated/obsolete ARMv8 instructions"
721 Legacy software support may require certain instructions
722 that have been deprecated or obsoleted in the architecture.
724 Enable this config to enable selective emulation of these
732 bool "Emulate SWP/SWPB instructions"
734 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
735 they are always undefined. Say Y here to enable software
736 emulation of these instructions for userspace using LDXR/STXR.
738 In some older versions of glibc [<=2.8] SWP is used during futex
739 trylock() operations with the assumption that the code will not
740 be preempted. This invalid assumption may be more likely to fail
741 with SWP emulation enabled, leading to deadlock of the user
744 NOTE: when accessing uncached shared regions, LDXR/STXR rely
745 on an external transaction monitoring block called a global
746 monitor to maintain update atomicity. If your system does not
747 implement a global monitor, this option can cause programs that
748 perform SWP operations to uncached memory to deadlock.
752 config CP15_BARRIER_EMULATION
753 bool "Emulate CP15 Barrier instructions"
755 The CP15 barrier instructions - CP15ISB, CP15DSB, and
756 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
757 strongly recommended to use the ISB, DSB, and DMB
758 instructions instead.
760 Say Y here to enable software emulation of these
761 instructions for AArch32 userspace code. When this option is
762 enabled, CP15 barrier usage is traced which can help
763 identify software that needs updating.
767 config SETEND_EMULATION
768 bool "Emulate SETEND instruction"
770 The SETEND instruction alters the data-endianness of the
771 AArch32 EL0, and is deprecated in ARMv8.
773 Say Y here to enable software emulation of the instruction
774 for AArch32 userspace code.
776 Note: All the cpus on the system must have mixed endian support at EL0
777 for this feature to be enabled. If a new CPU - which doesn't support mixed
778 endian - is hotplugged in after this feature has been enabled, there could
779 be unexpected results in the applications.
784 menu "ARMv8.1 architectural features"
786 config ARM64_HW_AFDBM
787 bool "Support for hardware updates of the Access and Dirty page flags"
790 The ARMv8.1 architecture extensions introduce support for
791 hardware updates of the access and dirty information in page
792 table entries. When enabled in TCR_EL1 (HA and HD bits) on
793 capable processors, accesses to pages with PTE_AF cleared will
794 set this bit instead of raising an access flag fault.
795 Similarly, writes to read-only pages with the DBM bit set will
796 clear the read-only bit (AP[2]) instead of raising a
799 Kernels built with this configuration option enabled continue
800 to work on pre-ARMv8.1 hardware and the performance impact is
801 minimal. If unsure, say Y.
804 bool "Enable support for Privileged Access Never (PAN)"
807 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
808 prevents the kernel or hypervisor from accessing user-space (EL0)
811 Choosing this option will cause any unprotected (not using
812 copy_to_user et al) memory access to fail with a permission fault.
814 The feature is detected at runtime, and will remain as a 'nop'
815 instruction if the cpu does not implement the feature.
817 config ARM64_LSE_ATOMICS
818 bool "Atomic instructions"
820 As part of the Large System Extensions, ARMv8.1 introduces new
821 atomic instructions that are designed specifically to scale in
824 Say Y here to make use of these instructions for the in-kernel
825 atomic routines. This incurs a small overhead on CPUs that do
826 not support these instructions and requires the kernel to be
827 built with binutils >= 2.25.
830 bool "Enable support for Virtualization Host Extensions (VHE)"
833 Virtualization Host Extensions (VHE) allow the kernel to run
834 directly at EL2 (instead of EL1) on processors that support
835 it. This leads to better performance for KVM, as they reduce
836 the cost of the world switch.
838 Selecting this option allows the VHE feature to be detected
839 at runtime, and does not affect processors that do not
840 implement this feature.
844 menu "ARMv8.2 architectural features"
847 bool "Enable support for User Access Override (UAO)"
850 User Access Override (UAO; part of the ARMv8.2 Extensions)
851 causes the 'unprivileged' variant of the load/store instructions to
852 be overriden to be privileged.
854 This option changes get_user() and friends to use the 'unprivileged'
855 variant of the load/store instructions. This ensures that user-space
856 really did have access to the supplied memory. When addr_limit is
857 set to kernel memory the UAO bit will be set, allowing privileged
858 access to kernel memory.
860 Choosing this option will cause copy_to_user() et al to use user-space
863 The feature is detected at runtime, the kernel will use the
864 regular load/store instructions if the cpu does not implement the
869 config ARM64_MODULE_CMODEL_LARGE
872 config ARM64_MODULE_PLTS
874 select ARM64_MODULE_CMODEL_LARGE
875 select HAVE_MOD_ARCH_SPECIFIC
880 This builds the kernel as a Position Independent Executable (PIE),
881 which retains all relocation metadata required to relocate the
882 kernel binary at runtime to a different virtual address than the
883 address it was linked at.
884 Since AArch64 uses the RELA relocation format, this requires a
885 relocation pass at runtime even if the kernel is loaded at the
886 same address it was linked at.
888 config RANDOMIZE_BASE
889 bool "Randomize the address of the kernel image"
890 select ARM64_MODULE_PLTS if MODULES
893 Randomizes the virtual address at which the kernel image is
894 loaded, as a security feature that deters exploit attempts
895 relying on knowledge of the location of kernel internals.
897 It is the bootloader's job to provide entropy, by passing a
898 random u64 value in /chosen/kaslr-seed at kernel entry.
900 When booting via the UEFI stub, it will invoke the firmware's
901 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
902 to the kernel proper. In addition, it will randomise the physical
903 location of the kernel Image as well.
907 config RANDOMIZE_MODULE_REGION_FULL
908 bool "Randomize the module region independently from the core kernel"
909 depends on RANDOMIZE_BASE
912 Randomizes the location of the module region without considering the
913 location of the core kernel. This way, it is impossible for modules
914 to leak information about the location of core kernel data structures
915 but it does imply that function calls between modules and the core
916 kernel will need to be resolved via veneers in the module PLT.
918 When this option is not set, the module region will be randomized over
919 a limited range that contains the [_stext, _etext] interval of the
920 core kernel, so branch relocations are always in range.
926 config ARM64_ACPI_PARKING_PROTOCOL
927 bool "Enable support for the ARM64 ACPI parking protocol"
930 Enable support for the ARM64 ACPI parking protocol. If disabled
931 the kernel will not allow booting through the ARM64 ACPI parking
932 protocol even if the corresponding data is present in the ACPI
936 string "Default kernel command string"
939 Provide a set of default command-line options at build time by
940 entering them here. As a minimum, you should specify the the
941 root device (e.g. root=/dev/nfs).
944 bool "Always use the default kernel command string"
946 Always use the default kernel command string, even if the boot
947 loader passes other arguments to the kernel.
948 This is useful if you cannot or don't want to change the
949 command-line options your boot loader passes to the kernel.
955 bool "UEFI runtime support"
956 depends on OF && !CPU_BIG_ENDIAN
959 select EFI_PARAMS_FROM_FDT
960 select EFI_RUNTIME_WRAPPERS
965 This option provides support for runtime services provided
966 by UEFI firmware (such as non-volatile variables, realtime
967 clock, and platform reset). A UEFI stub is also provided to
968 allow the kernel to be booted as an EFI application. This
969 is only useful on systems that have UEFI firmware.
972 bool "Enable support for SMBIOS (DMI) tables"
976 This enables SMBIOS/DMI feature for systems.
978 This option is only useful on systems that have UEFI firmware.
979 However, even with this option, the resultant kernel should
980 continue to boot on existing non-UEFI platforms.
984 menu "Userspace binary formats"
986 source "fs/Kconfig.binfmt"
989 bool "Kernel support for 32-bit EL0"
990 depends on ARM64_4K_PAGES || EXPERT
991 select COMPAT_BINFMT_ELF
993 select OLD_SIGSUSPEND3
994 select COMPAT_OLD_SIGACTION
996 This option enables support for a 32-bit EL0 running under a 64-bit
997 kernel at EL1. AArch32-specific components such as system calls,
998 the user helper functions, VFP support and the ptrace interface are
999 handled appropriately by the kernel.
1001 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1002 that you will only be able to execute AArch32 binaries that were compiled
1003 with page size aligned segments.
1005 If you want to execute 32-bit userspace applications, say Y.
1007 config SYSVIPC_COMPAT
1009 depends on COMPAT && SYSVIPC
1013 menu "Power management options"
1015 source "kernel/power/Kconfig"
1017 config ARCH_HIBERNATION_POSSIBLE
1021 config ARCH_HIBERNATION_HEADER
1023 depends on HIBERNATION
1025 config ARCH_SUSPEND_POSSIBLE
1030 menu "CPU Power Management"
1032 source "drivers/cpuidle/Kconfig"
1034 source "drivers/cpufreq/Kconfig"
1038 source "net/Kconfig"
1040 source "drivers/Kconfig"
1042 source "drivers/firmware/Kconfig"
1044 source "drivers/acpi/Kconfig"
1048 source "arch/arm64/kvm/Kconfig"
1050 source "arch/arm64/Kconfig.debug"
1052 source "security/Kconfig"
1054 source "crypto/Kconfig"
1056 source "arch/arm64/crypto/Kconfig"
1059 source "lib/Kconfig"