arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_DEVMEM_IS_ALLOWED
   7         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   8         select ARCH_HAS_ELF_RANDOMIZE
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_HAS_SG_CHAIN
  11         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_SUPPORTS_ATOMIC_RMW
  14         select ARCH_WANT_OPTIONAL_GPIOLIB
  15         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  16         select ARCH_WANT_FRAME_POINTERS
  17         select ARM_AMBA
  18         select ARM_ARCH_TIMER
  19         select ARM_GIC
  20         select AUDIT_ARCH_COMPAT_GENERIC
  21         select ARM_GIC_V2M if PCI_MSI
  22         select ARM_GIC_V3
  23         select ARM_GIC_V3_ITS if PCI_MSI
  24         select ARM_PSCI_FW
  25         select BUILDTIME_EXTABLE_SORT
  26         select CLONE_BACKWARDS
  27         select COMMON_CLK
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS
  30         select EDAC_SUPPORT
  31         select FRAME_POINTER
  32         select GENERIC_ALLOCATOR
  33         select GENERIC_CLOCKEVENTS
  34         select GENERIC_CLOCKEVENTS_BROADCAST
  35         select GENERIC_CPU_AUTOPROBE
  36         select GENERIC_EARLY_IOREMAP
  37         select GENERIC_IDLE_POLL_SETUP
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_SHOW_LEVEL
  41         select GENERIC_PCI_IOMAP
  42         select GENERIC_SCHED_CLOCK
  43         select GENERIC_SMP_IDLE_THREAD
  44         select GENERIC_STRNCPY_FROM_USER
  45         select GENERIC_STRNLEN_USER
  46         select GENERIC_TIME_VSYSCALL
  47         select HANDLE_DOMAIN_IRQ
  48         select HARDIRQS_SW_RESEND
  49         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  50         select HAVE_ARCH_AUDITSYSCALL
  51         select HAVE_ARCH_BITREVERSE
  52         select HAVE_ARCH_JUMP_LABEL
  53         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
  54         select HAVE_ARCH_KGDB
  55         select HAVE_ARCH_MMAP_RND_BITS
  56         select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
  57         select HAVE_ARCH_SECCOMP_FILTER
  58         select HAVE_ARCH_TRACEHOOK
  59         select HAVE_BPF_JIT
  60         select HAVE_C_RECORDMCOUNT
  61         select HAVE_CC_STACKPROTECTOR
  62         select HAVE_CMPXCHG_DOUBLE
  63         select HAVE_CMPXCHG_LOCAL
  64         select HAVE_DEBUG_BUGVERBOSE
  65         select HAVE_DEBUG_KMEMLEAK
  66         select HAVE_DMA_API_DEBUG
  67         select HAVE_DMA_CONTIGUOUS
  68         select HAVE_DYNAMIC_FTRACE
  69         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  70         select HAVE_FTRACE_MCOUNT_RECORD
  71         select HAVE_FUNCTION_TRACER
  72         select HAVE_FUNCTION_GRAPH_TRACER
  73         select HAVE_GENERIC_DMA_COHERENT
  74         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  75         select HAVE_IRQ_TIME_ACCOUNTING
  76         select HAVE_MEMBLOCK
  77         select HAVE_PATA_PLATFORM
  78         select HAVE_PERF_EVENTS
  79         select HAVE_PERF_REGS
  80         select HAVE_PERF_USER_STACK_DUMP
  81         select HAVE_RCU_TABLE_FREE
  82         select HAVE_SYSCALL_TRACEPOINTS
  83         select IOMMU_DMA if IOMMU_SUPPORT
  84         select IRQ_DOMAIN
  85         select IRQ_FORCED_THREADING
  86         select MODULES_USE_ELF_RELA
  87         select NO_BOOTMEM
  88         select OF
  89         select OF_EARLY_FLATTREE
  90         select OF_RESERVED_MEM
  91         select PERF_USE_VMALLOC
  92         select POWER_RESET
  93         select POWER_SUPPLY
  94         select RTC_LIB
  95         select SPARSE_IRQ
  96         select SYSCTL_EXCEPTION_TRACE
  97         select HAVE_CONTEXT_TRACKING
  98         select HAVE_ARM_SMCCC
  99         help
 100           ARM 64-bit (AArch64) Linux support.
 101
 102 config 64BIT
 103         def_bool y
 104
 105 config ARCH_PHYS_ADDR_T_64BIT
 106         def_bool y
 107
 108 config MMU
 109         def_bool y
 110
 111 config ARCH_MMAP_RND_BITS_MIN
 112        default 14 if ARM64_64K_PAGES
 113        default 16 if ARM64_16K_PAGES
 114        default 18
 115
 116 # max bits determined by the following formula:
 117 #  VA_BITS - PAGE_SHIFT - 3
 118 config ARCH_MMAP_RND_BITS_MAX
 119        default 19 if ARM64_VA_BITS=36
 120        default 24 if ARM64_VA_BITS=39
 121        default 27 if ARM64_VA_BITS=42
 122        default 30 if ARM64_VA_BITS=47
 123        default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 124        default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 125        default 33 if ARM64_VA_BITS=48
 126        default 14 if ARM64_64K_PAGES
 127        default 16 if ARM64_16K_PAGES
 128        default 18
 129
 130 config ARCH_MMAP_RND_COMPAT_BITS_MIN
 131        default 7 if ARM64_64K_PAGES
 132        default 9 if ARM64_16K_PAGES
 133        default 11
 134
 135 config ARCH_MMAP_RND_COMPAT_BITS_MAX
 136        default 16
 137
 138 config NO_IOPORT_MAP
 139         def_bool y if !PCI
 140
 141 config STACKTRACE_SUPPORT
 142         def_bool y
 143
 144 config ILLEGAL_POINTER_VALUE
 145         hex
 146         default 0xdead000000000000
 147
 148 config LOCKDEP_SUPPORT
 149         def_bool y
 150
 151 config TRACE_IRQFLAGS_SUPPORT
 152         def_bool y
 153
 154 config RWSEM_XCHGADD_ALGORITHM
 155         def_bool y
 156
 157 config GENERIC_BUG
 158         def_bool y
 159         depends on BUG
 160
 161 config GENERIC_BUG_RELATIVE_POINTERS
 162         def_bool y
 163         depends on GENERIC_BUG
 164
 165 config GENERIC_HWEIGHT
 166         def_bool y
 167
 168 config GENERIC_CSUM
 169         def_bool y
 170
 171 config GENERIC_CALIBRATE_DELAY
 172         def_bool y
 173
 174 config ZONE_DMA
 175         def_bool y
 176
 177 config HAVE_GENERIC_RCU_GUP
 178         def_bool y
 179
 180 config ARCH_DMA_ADDR_T_64BIT
 181         def_bool y
 182
 183 config NEED_DMA_MAP_STATE
 184         def_bool y
 185
 186 config NEED_SG_DMA_LENGTH
 187         def_bool y
 188
 189 config SMP
 190         def_bool y
 191
 192 config SWIOTLB
 193         def_bool y
 194
 195 config IOMMU_HELPER
 196         def_bool SWIOTLB
 197
 198 config KERNEL_MODE_NEON
 199         def_bool y
 200
 201 config FIX_EARLYCON_MEM
 202         def_bool y
 203
 204 config PGTABLE_LEVELS
 205         int
 206         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 207         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 208         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 209         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 210         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 211         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 212
 213 source "init/Kconfig"
 214
 215 source "kernel/Kconfig.freezer"
 216
 217 source "arch/arm64/Kconfig.platforms"
 218
 219 menu "Bus support"
 220
 221 config PCI
 222         bool "PCI support"
 223         help
 224           This feature enables support for PCI bus system. If you say Y
 225           here, the kernel will include drivers and infrastructure code
 226           to support PCI bus devices.
 227
 228 config PCI_DOMAINS
 229         def_bool PCI
 230
 231 config PCI_DOMAINS_GENERIC
 232         def_bool PCI
 233
 234 config PCI_SYSCALL
 235         def_bool PCI
 236
 237 source "drivers/pci/Kconfig"
 238
 239 endmenu
 240
 241 menu "Kernel Features"
 242
 243 menu "ARM errata workarounds via the alternatives framework"
 244
 245 config ARM64_ERRATUM_826319
 246         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 247         default y
 248         help
 249           This option adds an alternative code sequence to work around ARM
 250           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 251           AXI master interface and an L2 cache.
 252
 253           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 254           and is unable to accept a certain write via this interface, it will
 255           not progress on read data presented on the read data channel and the
 256           system can deadlock.
 257
 258           The workaround promotes data cache clean instructions to
 259           data cache clean-and-invalidate.
 260           Please note that this does not necessarily enable the workaround,
 261           as it depends on the alternative framework, which will only patch
 262           the kernel if an affected CPU is detected.
 263
 264           If unsure, say Y.
 265
 266 config ARM64_ERRATUM_827319
 267         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 268         default y
 269         help
 270           This option adds an alternative code sequence to work around ARM
 271           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 272           master interface and an L2 cache.
 273
 274           Under certain conditions this erratum can cause a clean line eviction
 275           to occur at the same time as another transaction to the same address
 276           on the AMBA 5 CHI interface, which can cause data corruption if the
 277           interconnect reorders the two transactions.
 278
 279           The workaround promotes data cache clean instructions to
 280           data cache clean-and-invalidate.
 281           Please note that this does not necessarily enable the workaround,
 282           as it depends on the alternative framework, which will only patch
 283           the kernel if an affected CPU is detected.
 284
 285           If unsure, say Y.
 286
 287 config ARM64_ERRATUM_824069
 288         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 289         default y
 290         help
 291           This option adds an alternative code sequence to work around ARM
 292           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 293           to a coherent interconnect.
 294
 295           If a Cortex-A53 processor is executing a store or prefetch for
 296           write instruction at the same time as a processor in another
 297           cluster is executing a cache maintenance operation to the same
 298           address, then this erratum might cause a clean cache line to be
 299           incorrectly marked as dirty.
 300
 301           The workaround promotes data cache clean instructions to
 302           data cache clean-and-invalidate.
 303           Please note that this option does not necessarily enable the
 304           workaround, as it depends on the alternative framework, which will
 305           only patch the kernel if an affected CPU is detected.
 306
 307           If unsure, say Y.
 308
 309 config ARM64_ERRATUM_819472
 310         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 311         default y
 312         help
 313           This option adds an alternative code sequence to work around ARM
 314           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 315           present when it is connected to a coherent interconnect.
 316
 317           If the processor is executing a load and store exclusive sequence at
 318           the same time as a processor in another cluster is executing a cache
 319           maintenance operation to the same address, then this erratum might
 320           cause data corruption.
 321
 322           The workaround promotes data cache clean instructions to
 323           data cache clean-and-invalidate.
 324           Please note that this does not necessarily enable the workaround,
 325           as it depends on the alternative framework, which will only patch
 326           the kernel if an affected CPU is detected.
 327
 328           If unsure, say Y.
 329
 330 config ARM64_ERRATUM_832075
 331         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 332         default y
 333         help
 334           This option adds an alternative code sequence to work around ARM
 335           erratum 832075 on Cortex-A57 parts up to r1p2.
 336
 337           Affected Cortex-A57 parts might deadlock when exclusive load/store
 338           instructions to Write-Back memory are mixed with Device loads.
 339
 340           The workaround is to promote device loads to use Load-Acquire
 341           semantics.
 342           Please note that this does not necessarily enable the workaround,
 343           as it depends on the alternative framework, which will only patch
 344           the kernel if an affected CPU is detected.
 345
 346           If unsure, say Y.
 347
 348 config ARM64_ERRATUM_834220
 349         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 350         depends on KVM
 351         default y
 352         help
 353           This option adds an alternative code sequence to work around ARM
 354           erratum 834220 on Cortex-A57 parts up to r1p2.
 355
 356           Affected Cortex-A57 parts might report a Stage 2 translation
 357           fault as the result of a Stage 1 fault for load crossing a
 358           page boundary when there is a permission or device memory
 359           alignment fault at Stage 1 and a translation fault at Stage 2.
 360
 361           The workaround is to verify that the Stage 1 translation
 362           doesn't generate a fault before handling the Stage 2 fault.
 363           Please note that this does not necessarily enable the workaround,
 364           as it depends on the alternative framework, which will only patch
 365           the kernel if an affected CPU is detected.
 366
 367           If unsure, say Y.
 368
 369 config ARM64_ERRATUM_845719
 370         bool "Cortex-A53: 845719: a load might read incorrect data"
 371         depends on COMPAT
 372         default y
 373         help
 374           This option adds an alternative code sequence to work around ARM
 375           erratum 845719 on Cortex-A53 parts up to r0p4.
 376
 377           When running a compat (AArch32) userspace on an affected Cortex-A53
 378           part, a load at EL0 from a virtual address that matches the bottom 32
 379           bits of the virtual address used by a recent load at (AArch64) EL1
 380           might return incorrect data.
 381
 382           The workaround is to write the contextidr_el1 register on exception
 383           return to a 32-bit task.
 384           Please note that this does not necessarily enable the workaround,
 385           as it depends on the alternative framework, which will only patch
 386           the kernel if an affected CPU is detected.
 387
 388           If unsure, say Y.
 389
 390 config ARM64_ERRATUM_843419
 391         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 392         depends on MODULES
 393         default y
 394         help
 395           This option builds kernel modules using the large memory model in
 396           order to avoid the use of the ADRP instruction, which can cause
 397           a subsequent memory access to use an incorrect address on Cortex-A53
 398           parts up to r0p4.
 399
 400           Note that the kernel itself must be linked with a version of ld
 401           which fixes potentially affected ADRP instructions through the
 402           use of veneers.
 403
 404           If unsure, say Y.
 405
 406 config CAVIUM_ERRATUM_22375
 407         bool "Cavium erratum 22375, 24313"
 408         default y
 409         help
 410           Enable workaround for erratum 22375, 24313.
 411
 412           This implements two gicv3-its errata workarounds for ThunderX. Both
 413           with small impact affecting only ITS table allocation.
 414
 415             erratum 22375: only alloc 8MB table size
 416             erratum 24313: ignore memory access type
 417
 418           The fixes are in ITS initialization and basically ignore memory access
 419           type and table size provided by the TYPER and BASER registers.
 420
 421           If unsure, say Y.
 422
 423 config CAVIUM_ERRATUM_23154
 424         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 425         default y
 426         help
 427           The gicv3 of ThunderX requires a modified version for
 428           reading the IAR status to ensure data synchronization
 429           (access to icc_iar1_el1 is not sync'ed before and after).
 430
 431           If unsure, say Y.
 432
 433 endmenu
 434
 435
 436 choice
 437         prompt "Page size"
 438         default ARM64_4K_PAGES
 439         help
 440           Page size (translation granule) configuration.
 441
 442 config ARM64_4K_PAGES
 443         bool "4KB"
 444         help
 445           This feature enables 4KB pages support.
 446
 447 config ARM64_16K_PAGES
 448         bool "16KB"
 449         help
 450           The system will use 16KB pages support. AArch32 emulation
 451           requires applications compiled with 16K (or a multiple of 16K)
 452           aligned segments.
 453
 454 config ARM64_64K_PAGES
 455         bool "64KB"
 456         help
 457           This feature enables 64KB pages support (4KB by default)
 458           allowing only two levels of page tables and faster TLB
 459           look-up. AArch32 emulation requires applications compiled
 460           with 64K aligned segments.
 461
 462 endchoice
 463
 464 choice
 465         prompt "Virtual address space size"
 466         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 467         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 468         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 469         help
 470           Allows choosing one of multiple possible virtual address
 471           space sizes. The level of translation table is determined by
 472           a combination of page size and virtual address space size.
 473
 474 config ARM64_VA_BITS_36
 475         bool "36-bit" if EXPERT
 476         depends on ARM64_16K_PAGES
 477
 478 config ARM64_VA_BITS_39
 479         bool "39-bit"
 480         depends on ARM64_4K_PAGES
 481
 482 config ARM64_VA_BITS_42
 483         bool "42-bit"
 484         depends on ARM64_64K_PAGES
 485
 486 config ARM64_VA_BITS_47
 487         bool "47-bit"
 488         depends on ARM64_16K_PAGES
 489
 490 config ARM64_VA_BITS_48
 491         bool "48-bit"
 492
 493 endchoice
 494
 495 config ARM64_VA_BITS
 496         int
 497         default 36 if ARM64_VA_BITS_36
 498         default 39 if ARM64_VA_BITS_39
 499         default 42 if ARM64_VA_BITS_42
 500         default 47 if ARM64_VA_BITS_47
 501         default 48 if ARM64_VA_BITS_48
 502
 503 config CPU_BIG_ENDIAN
 504        bool "Build big-endian kernel"
 505        help
 506          Say Y if you plan on running a kernel in big-endian mode.
 507
 508 config SCHED_MC
 509         bool "Multi-core scheduler support"
 510         help
 511           Multi-core scheduler support improves the CPU scheduler's decision
 512           making when dealing with multi-core CPU chips at a cost of slightly
 513           increased overhead in some places. If unsure say N here.
 514
 515 config SCHED_SMT
 516         bool "SMT scheduler support"
 517         help
 518           Improves the CPU scheduler's decision making when dealing with
 519           MultiThreading at a cost of slightly increased overhead in some
 520           places. If unsure say N here.
 521
 522 config NR_CPUS
 523         int "Maximum number of CPUs (2-4096)"
 524         range 2 4096
 525         # These have to remain sorted largest to smallest
 526         default "64"
 527
 528 config HOTPLUG_CPU
 529         bool "Support for hot-pluggable CPUs"
 530         select GENERIC_IRQ_MIGRATION
 531         help
 532           Say Y here to experiment with turning CPUs off and on.  CPUs
 533           can be controlled through /sys/devices/system/cpu.
 534
 535 source kernel/Kconfig.preempt
 536 source kernel/Kconfig.hz
 537
 538 config ARCH_HAS_HOLES_MEMORYMODEL
 539         def_bool y if SPARSEMEM
 540
 541 config ARCH_SPARSEMEM_ENABLE
 542         def_bool y
 543         select SPARSEMEM_VMEMMAP_ENABLE
 544
 545 config ARCH_SPARSEMEM_DEFAULT
 546         def_bool ARCH_SPARSEMEM_ENABLE
 547
 548 config ARCH_SELECT_MEMORY_MODEL
 549         def_bool ARCH_SPARSEMEM_ENABLE
 550
 551 config HAVE_ARCH_PFN_VALID
 552         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 553
 554 config HW_PERF_EVENTS
 555         def_bool y
 556         depends on ARM_PMU
 557
 558 config SYS_SUPPORTS_HUGETLBFS
 559         def_bool y
 560
 561 config ARCH_WANT_HUGE_PMD_SHARE
 562         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 563
 564 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 565         def_bool y
 566
 567 config ARCH_HAS_CACHE_LINE_SIZE
 568         def_bool y
 569
 570 source "mm/Kconfig"
 571
 572 config SECCOMP
 573         bool "Enable seccomp to safely compute untrusted bytecode"
 574         ---help---
 575           This kernel feature is useful for number crunching applications
 576           that may need to compute untrusted bytecode during their
 577           execution. By using pipes or other transports made available to
 578           the process as file descriptors supporting the read/write
 579           syscalls, it's possible to isolate those applications in
 580           their own address space using seccomp. Once seccomp is
 581           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 582           and the task is only allowed to execute a few safe syscalls
 583           defined by each seccomp mode.
 584
 585 config PARAVIRT
 586         bool "Enable paravirtualization code"
 587         help
 588           This changes the kernel so it can modify itself when it is run
 589           under a hypervisor, potentially improving performance significantly
 590           over full virtualization.
 591
 592 config PARAVIRT_TIME_ACCOUNTING
 593         bool "Paravirtual steal time accounting"
 594         select PARAVIRT
 595         default n
 596         help
 597           Select this option to enable fine granularity task steal time
 598           accounting. Time spent executing other tasks in parallel with
 599           the current vCPU is discounted from the vCPU power. To account for
 600           that, there can be a small performance impact.
 601
 602           If in doubt, say N here.
 603
 604 config XEN_DOM0
 605         def_bool y
 606         depends on XEN
 607
 608 config XEN
 609         bool "Xen guest support on ARM64"
 610         depends on ARM64 && OF
 611         select SWIOTLB_XEN
 612         select PARAVIRT
 613         help
 614           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 615
 616 config FORCE_MAX_ZONEORDER
 617         int
 618         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 619         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 620         default "11"
 621         help
 622           The kernel memory allocator divides physically contiguous memory
 623           blocks into "zones", where each zone is a power of two number of
 624           pages.  This option selects the largest power of two that the kernel
 625           keeps in the memory allocator.  If you need to allocate very large
 626           blocks of physically contiguous memory, then you may need to
 627           increase this value.
 628
 629           This config option is actually maximum order plus one. For example,
 630           a value of 11 means that the largest free memory block is 2^10 pages.
 631
 632           We make sure that we can allocate upto a HugePage size for each configuration.
 633           Hence we have :
 634                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 635
 636           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 637           4M allocations matching the default size used by generic code.
 638
 639 menuconfig ARMV8_DEPRECATED
 640         bool "Emulate deprecated/obsolete ARMv8 instructions"
 641         depends on COMPAT
 642         help
 643           Legacy software support may require certain instructions
 644           that have been deprecated or obsoleted in the architecture.
 645
 646           Enable this config to enable selective emulation of these
 647           features.
 648
 649           If unsure, say Y
 650
 651 if ARMV8_DEPRECATED
 652
 653 config SWP_EMULATION
 654         bool "Emulate SWP/SWPB instructions"
 655         help
 656           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 657           they are always undefined. Say Y here to enable software
 658           emulation of these instructions for userspace using LDXR/STXR.
 659
 660           In some older versions of glibc [<=2.8] SWP is used during futex
 661           trylock() operations with the assumption that the code will not
 662           be preempted. This invalid assumption may be more likely to fail
 663           with SWP emulation enabled, leading to deadlock of the user
 664           application.
 665
 666           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 667           on an external transaction monitoring block called a global
 668           monitor to maintain update atomicity. If your system does not
 669           implement a global monitor, this option can cause programs that
 670           perform SWP operations to uncached memory to deadlock.
 671
 672           If unsure, say Y
 673
 674 config CP15_BARRIER_EMULATION
 675         bool "Emulate CP15 Barrier instructions"
 676         help
 677           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 678           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 679           strongly recommended to use the ISB, DSB, and DMB
 680           instructions instead.
 681
 682           Say Y here to enable software emulation of these
 683           instructions for AArch32 userspace code. When this option is
 684           enabled, CP15 barrier usage is traced which can help
 685           identify software that needs updating.
 686
 687           If unsure, say Y
 688
 689 config SETEND_EMULATION
 690         bool "Emulate SETEND instruction"
 691         help
 692           The SETEND instruction alters the data-endianness of the
 693           AArch32 EL0, and is deprecated in ARMv8.
 694
 695           Say Y here to enable software emulation of the instruction
 696           for AArch32 userspace code.
 697
 698           Note: All the cpus on the system must have mixed endian support at EL0
 699           for this feature to be enabled. If a new CPU - which doesn't support mixed
 700           endian - is hotplugged in after this feature has been enabled, there could
 701           be unexpected results in the applications.
 702
 703           If unsure, say Y
 704 endif
 705
 706 menu "ARMv8.1 architectural features"
 707
 708 config ARM64_HW_AFDBM
 709         bool "Support for hardware updates of the Access and Dirty page flags"
 710         default y
 711         help
 712           The ARMv8.1 architecture extensions introduce support for
 713           hardware updates of the access and dirty information in page
 714           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 715           capable processors, accesses to pages with PTE_AF cleared will
 716           set this bit instead of raising an access flag fault.
 717           Similarly, writes to read-only pages with the DBM bit set will
 718           clear the read-only bit (AP[2]) instead of raising a
 719           permission fault.
 720
 721           Kernels built with this configuration option enabled continue
 722           to work on pre-ARMv8.1 hardware and the performance impact is
 723           minimal. If unsure, say Y.
 724
 725 config ARM64_PAN
 726         bool "Enable support for Privileged Access Never (PAN)"
 727         default y
 728         help
 729          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 730          prevents the kernel or hypervisor from accessing user-space (EL0)
 731          memory directly.
 732
 733          Choosing this option will cause any unprotected (not using
 734          copy_to_user et al) memory access to fail with a permission fault.
 735
 736          The feature is detected at runtime, and will remain as a 'nop'
 737          instruction if the cpu does not implement the feature.
 738
 739 config ARM64_LSE_ATOMICS
 740         bool "Atomic instructions"
 741         help
 742           As part of the Large System Extensions, ARMv8.1 introduces new
 743           atomic instructions that are designed specifically to scale in
 744           very large systems.
 745
 746           Say Y here to make use of these instructions for the in-kernel
 747           atomic routines. This incurs a small overhead on CPUs that do
 748           not support these instructions and requires the kernel to be
 749           built with binutils >= 2.25.
 750
 751 config ARM64_VHE
 752         bool "Enable support for Virtualization Host Extensions (VHE)"
 753         default y
 754         help
 755           Virtualization Host Extensions (VHE) allow the kernel to run
 756           directly at EL2 (instead of EL1) on processors that support
 757           it. This leads to better performance for KVM, as they reduce
 758           the cost of the world switch.
 759
 760           Selecting this option allows the VHE feature to be detected
 761           at runtime, and does not affect processors that do not
 762           implement this feature.
 763
 764 endmenu
 765
 766 endmenu
 767
 768 menu "Boot options"
 769
 770 config CMDLINE
 771         string "Default kernel command string"
 772         default ""
 773         help
 774           Provide a set of default command-line options at build time by
 775           entering them here. As a minimum, you should specify the the
 776           root device (e.g. root=/dev/nfs).
 777
 778 config CMDLINE_FORCE
 779         bool "Always use the default kernel command string"
 780         help
 781           Always use the default kernel command string, even if the boot
 782           loader passes other arguments to the kernel.
 783           This is useful if you cannot or don't want to change the
 784           command-line options your boot loader passes to the kernel.
 785
 786 config EFI_STUB
 787         bool
 788
 789 config EFI
 790         bool "UEFI runtime support"
 791         depends on OF && !CPU_BIG_ENDIAN
 792         select LIBFDT
 793         select UCS2_STRING
 794         select EFI_PARAMS_FROM_FDT
 795         select EFI_RUNTIME_WRAPPERS
 796         select EFI_STUB
 797         select EFI_ARMSTUB
 798         default y
 799         help
 800           This option provides support for runtime services provided
 801           by UEFI firmware (such as non-volatile variables, realtime
 802           clock, and platform reset). A UEFI stub is also provided to
 803           allow the kernel to be booted as an EFI application. This
 804           is only useful on systems that have UEFI firmware.
 805
 806 config DMI
 807         bool "Enable support for SMBIOS (DMI) tables"
 808         depends on EFI
 809         default y
 810         help
 811           This enables SMBIOS/DMI feature for systems.
 812
 813           This option is only useful on systems that have UEFI firmware.
 814           However, even with this option, the resultant kernel should
 815           continue to boot on existing non-UEFI platforms.
 816
 817 endmenu
 818
 819 menu "Userspace binary formats"
 820
 821 source "fs/Kconfig.binfmt"
 822
 823 config COMPAT
 824         bool "Kernel support for 32-bit EL0"
 825         depends on ARM64_4K_PAGES || EXPERT
 826         select COMPAT_BINFMT_ELF
 827         select HAVE_UID16
 828         select OLD_SIGSUSPEND3
 829         select COMPAT_OLD_SIGACTION
 830         help
 831           This option enables support for a 32-bit EL0 running under a 64-bit
 832           kernel at EL1. AArch32-specific components such as system calls,
 833           the user helper functions, VFP support and the ptrace interface are
 834           handled appropriately by the kernel.
 835
 836           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
 837           that you will only be able to execute AArch32 binaries that were compiled
 838           with page size aligned segments.
 839
 840           If you want to execute 32-bit userspace applications, say Y.
 841
 842 config SYSVIPC_COMPAT
 843         def_bool y
 844         depends on COMPAT && SYSVIPC
 845
 846 endmenu
 847
 848 menu "Power management options"
 849
 850 source "kernel/power/Kconfig"
 851
 852 config ARCH_SUSPEND_POSSIBLE
 853         def_bool y
 854
 855 endmenu
 856
 857 menu "CPU Power Management"
 858
 859 source "drivers/cpuidle/Kconfig"
 860
 861 source "drivers/cpufreq/Kconfig"
 862
 863 endmenu
 864
 865 source "net/Kconfig"
 866
 867 source "drivers/Kconfig"
 868
 869 source "drivers/firmware/Kconfig"
 870
 871 source "drivers/acpi/Kconfig"
 872
 873 source "fs/Kconfig"
 874
 875 source "arch/arm64/kvm/Kconfig"
 876
 877 source "arch/arm64/Kconfig.debug"
 878
 879 source "security/Kconfig"
 880
 881 source "crypto/Kconfig"
 882 if CRYPTO
 883 source "arch/arm64/crypto/Kconfig"
 884 endif
 885
 886 source "lib/Kconfig"