2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
4 * Copyright (C) 2015, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
24 compatible = "apm,strega", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
32 compatible = "apm,strega", "arm,armv8";
34 enable-method = "spin-table";
35 cpu-release-addr = <0x1 0x0000fff8>;
36 next-level-cache = <&xgene_L2_0>;
40 compatible = "apm,strega", "arm,armv8";
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
48 compatible = "apm,strega", "arm,armv8";
50 enable-method = "spin-table";
51 cpu-release-addr = <0x1 0x0000fff8>;
52 next-level-cache = <&xgene_L2_1>;
56 compatible = "apm,strega", "arm,armv8";
58 enable-method = "spin-table";
59 cpu-release-addr = <0x1 0x0000fff8>;
60 next-level-cache = <&xgene_L2_2>;
64 compatible = "apm,strega", "arm,armv8";
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
68 next-level-cache = <&xgene_L2_2>;
72 compatible = "apm,strega", "arm,armv8";
74 enable-method = "spin-table";
75 cpu-release-addr = <0x1 0x0000fff8>;
76 next-level-cache = <&xgene_L2_3>;
80 compatible = "apm,strega", "arm,armv8";
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
86 xgene_L2_0: l2-cache-0 {
89 xgene_L2_1: l2-cache-1 {
92 xgene_L2_2: l2-cache-2 {
95 xgene_L2_3: l2-cache-3 {
100 gic: interrupt-controller@78090000 {
101 compatible = "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 #address-cells = <2>;
105 interrupt-controller;
106 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
107 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
108 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
109 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
110 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
111 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
113 compatible = "arm,gic-v2m-frame";
115 reg = <0x0 0x0 0x0 0x1000>;
118 compatible = "arm,gic-v2m-frame";
120 reg = <0x0 0x10000 0x0 0x1000>;
123 compatible = "arm,gic-v2m-frame";
125 reg = <0x0 0x20000 0x0 0x1000>;
128 compatible = "arm,gic-v2m-frame";
130 reg = <0x0 0x30000 0x0 0x1000>;
133 compatible = "arm,gic-v2m-frame";
135 reg = <0x0 0x40000 0x0 0x1000>;
138 compatible = "arm,gic-v2m-frame";
140 reg = <0x0 0x50000 0x0 0x1000>;
143 compatible = "arm,gic-v2m-frame";
145 reg = <0x0 0x60000 0x0 0x1000>;
148 compatible = "arm,gic-v2m-frame";
150 reg = <0x0 0x70000 0x0 0x1000>;
153 compatible = "arm,gic-v2m-frame";
155 reg = <0x0 0x80000 0x0 0x1000>;
158 compatible = "arm,gic-v2m-frame";
160 reg = <0x0 0x90000 0x0 0x1000>;
163 compatible = "arm,gic-v2m-frame";
165 reg = <0x0 0xa0000 0x0 0x1000>;
168 compatible = "arm,gic-v2m-frame";
170 reg = <0x0 0xb0000 0x0 0x1000>;
173 compatible = "arm,gic-v2m-frame";
175 reg = <0x0 0xc0000 0x0 0x1000>;
178 compatible = "arm,gic-v2m-frame";
180 reg = <0x0 0xd0000 0x0 0x1000>;
183 compatible = "arm,gic-v2m-frame";
185 reg = <0x0 0xe0000 0x0 0x1000>;
188 compatible = "arm,gic-v2m-frame";
190 reg = <0x0 0xf0000 0x0 0x1000>;
195 compatible = "arm,armv8-pmuv3";
196 interrupts = <1 12 0xff04>;
200 compatible = "arm,armv8-timer";
201 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
202 <1 13 0xff08>, /* Non-secure Phys IRQ */
203 <1 14 0xff08>, /* Virt IRQ */
204 <1 15 0xff08>; /* Hyp IRQ */
205 clock-frequency = <50000000>;
209 compatible = "simple-bus";
210 #address-cells = <2>;
215 #address-cells = <2>;
220 compatible = "fixed-clock";
222 clock-frequency = <100000000>;
223 clock-output-names = "refclk";
226 socpll: socpll@17000120 {
227 compatible = "apm,xgene-socpll-v2-clock";
229 clocks = <&refclk 0>;
230 reg = <0x0 0x17000120 0x0 0x1000>;
231 clock-output-names = "socpll";
234 socplldiv2: socplldiv2 {
235 compatible = "fixed-factor-clock";
237 clocks = <&socpll 0>;
240 clock-output-names = "socplldiv2";
243 ahbclk: ahbclk@17000000 {
244 compatible = "apm,xgene-device-clock";
246 clocks = <&socplldiv2 0>;
247 reg = <0x0 0x17000000 0x0 0x2000>;
248 reg-names = "div-reg";
249 divider-offset = <0x164>;
250 divider-width = <0x5>;
251 divider-shift = <0x0>;
252 clock-output-names = "ahbclk";
255 sbapbclk: sbapbclk@1704c000 {
256 compatible = "apm,xgene-device-clock";
258 clocks = <&ahbclk 0>;
259 reg = <0x0 0x1704c000 0x0 0x2000>;
260 reg-names = "div-reg";
261 divider-offset = <0x10>;
262 divider-width = <0x2>;
263 divider-shift = <0x0>;
264 clock-output-names = "sbapbclk";
267 sdioclk: sdioclk@1f2ac000 {
268 compatible = "apm,xgene-device-clock";
270 clocks = <&socplldiv2 0>;
271 reg = <0x0 0x1f2ac000 0x0 0x1000
272 0x0 0x17000000 0x0 0x2000>;
273 reg-names = "csr-reg", "div-reg";
276 enable-offset = <0x8>;
278 divider-offset = <0x178>;
279 divider-width = <0x8>;
280 divider-shift = <0x0>;
281 clock-output-names = "sdioclk";
284 pcie0clk: pcie0clk@1f2bc000 {
285 compatible = "apm,xgene-device-clock";
287 clocks = <&socplldiv2 0>;
288 reg = <0x0 0x1f2bc000 0x0 0x1000>;
289 reg-names = "csr-reg";
290 clock-output-names = "pcie0clk";
293 pcie1clk: pcie1clk@1f2cc000 {
294 compatible = "apm,xgene-device-clock";
296 clocks = <&socplldiv2 0>;
297 reg = <0x0 0x1f2cc000 0x0 0x1000>;
298 reg-names = "csr-reg";
299 clock-output-names = "pcie1clk";
302 xge0clk: xge0clk@1f61c000 {
303 compatible = "apm,xgene-device-clock";
305 clocks = <&socplldiv2 0>;
306 reg = <0x0 0x1f61c000 0x0 0x1000>;
307 reg-names = "csr-reg";
310 clock-output-names = "xge0clk";
313 xge1clk: xge1clk@1f62c000 {
314 compatible = "apm,xgene-device-clock";
316 clocks = <&socplldiv2 0>;
317 reg = <0x0 0x1f62c000 0x0 0x1000>;
318 reg-names = "csr-reg";
321 clock-output-names = "xge1clk";
324 rngpkaclk: rngpkaclk@17000000 {
325 compatible = "apm,xgene-device-clock";
327 clocks = <&socplldiv2 0>;
328 reg = <0x0 0x17000000 0x0 0x2000>;
329 reg-names = "csr-reg";
332 enable-offset = <0x10>;
333 enable-mask = <0x10>;
334 clock-output-names = "rngpkaclk";
337 i2c4clk: i2c4clk@1704c000 {
338 compatible = "apm,xgene-device-clock";
340 clocks = <&sbapbclk 0>;
341 reg = <0x0 0x1704c000 0x0 0x1000>;
342 reg-names = "csr-reg";
345 enable-offset = <0x8>;
346 enable-mask = <0x40>;
347 clock-output-names = "i2c4clk";
351 scu: system-clk-controller@17000000 {
352 compatible = "apm,xgene-scu","syscon";
353 reg = <0x0 0x17000000 0x0 0x400>;
356 reboot: reboot@17000014 {
357 compatible = "syscon-reboot";
364 compatible = "apm,xgene-csw", "syscon";
365 reg = <0x0 0x7e200000 0x0 0x1000>;
368 mcba: mcba@7e700000 {
369 compatible = "apm,xgene-mcb", "syscon";
370 reg = <0x0 0x7e700000 0x0 0x1000>;
373 mcbb: mcbb@7e720000 {
374 compatible = "apm,xgene-mcb", "syscon";
375 reg = <0x0 0x7e720000 0x0 0x1000>;
378 efuse: efuse@1054a000 {
379 compatible = "apm,xgene-efuse", "syscon";
380 reg = <0x0 0x1054a000 0x0 0x20>;
384 compatible = "apm,xgene-edac";
385 #address-cells = <2>;
389 regmap-mcba = <&mcba>;
390 regmap-mcbb = <&mcbb>;
391 regmap-efuse = <&efuse>;
392 reg = <0x0 0x78800000 0x0 0x100>;
393 interrupts = <0x0 0x20 0x4>,
398 compatible = "apm,xgene-edac-mc";
399 reg = <0x0 0x7e800000 0x0 0x1000>;
400 memory-controller = <0>;
404 compatible = "apm,xgene-edac-mc";
405 reg = <0x0 0x7e840000 0x0 0x1000>;
406 memory-controller = <1>;
410 compatible = "apm,xgene-edac-mc";
411 reg = <0x0 0x7e880000 0x0 0x1000>;
412 memory-controller = <2>;
416 compatible = "apm,xgene-edac-mc";
417 reg = <0x0 0x7e8c0000 0x0 0x1000>;
418 memory-controller = <3>;
422 compatible = "apm,xgene-edac-pmd";
423 reg = <0x0 0x7c000000 0x0 0x200000>;
424 pmd-controller = <0>;
428 compatible = "apm,xgene-edac-pmd";
429 reg = <0x0 0x7c200000 0x0 0x200000>;
430 pmd-controller = <1>;
434 compatible = "apm,xgene-edac-pmd";
435 reg = <0x0 0x7c400000 0x0 0x200000>;
436 pmd-controller = <2>;
440 compatible = "apm,xgene-edac-pmd";
441 reg = <0x0 0x7c600000 0x0 0x200000>;
442 pmd-controller = <3>;
446 compatible = "apm,xgene-edac-l3-v2";
447 reg = <0x0 0x7e600000 0x0 0x1000>;
451 compatible = "apm,xgene-edac-soc";
452 reg = <0x0 0x7e930000 0x0 0x1000>;
456 mailbox: mailbox@10540000 {
457 compatible = "apm,xgene-slimpro-mbox";
458 reg = <0x0 0x10540000 0x0 0x8000>;
460 interrupts = <0x0 0x0 0x4
471 compatible = "apm,xgene-slimpro-i2c";
472 mboxes = <&mailbox 0>;
475 serial0: serial@10600000 {
476 device_type = "serial";
477 compatible = "ns16550";
478 reg = <0 0x10600000 0x0 0x1000>;
480 clock-frequency = <10000000>;
481 interrupt-parent = <&gic>;
482 interrupts = <0x0 0x4c 0x4>;
485 /* Do not change dwusb name, coded for backward compatibility */
486 usb0: dwusb@19000000 {
488 compatible = "snps,dwc3";
489 reg = <0x0 0x19000000 0x0 0x100000>;
490 interrupts = <0x0 0x5d 0x4>;
495 pcie0: pcie@1f2b0000 {
498 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
499 #interrupt-cells = <1>;
501 #address-cells = <3>;
502 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
503 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
504 reg-names = "csr", "cfg";
505 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
506 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
507 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
508 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
509 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
510 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
511 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
512 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
513 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
514 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
516 clocks = <&pcie0clk 0>;
517 msi-parent = <&v2m0>;
520 pcie1: pcie@1f2c0000 {
523 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
524 #interrupt-cells = <1>;
526 #address-cells = <3>;
527 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
528 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
529 reg-names = "csr", "cfg";
530 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
531 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
532 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
533 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
534 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
535 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
536 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
537 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
538 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
539 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
541 clocks = <&pcie1clk 0>;
542 msi-parent = <&v2m0>;
545 sata1: sata@1a000000 {
546 compatible = "apm,xgene-ahci-v2";
547 reg = <0x0 0x1a000000 0x0 0x1000>,
548 <0x0 0x1f200000 0x0 0x1000>,
549 <0x0 0x1f20d000 0x0 0x1000>,
550 <0x0 0x1f20e000 0x0 0x1000>;
551 interrupts = <0x0 0x5a 0x4>;
555 sata2: sata@1a200000 {
556 compatible = "apm,xgene-ahci-v2";
557 reg = <0x0 0x1a200000 0x0 0x1000>,
558 <0x0 0x1f210000 0x0 0x1000>,
559 <0x0 0x1f21d000 0x0 0x1000>,
560 <0x0 0x1f21e000 0x0 0x1000>;
561 interrupts = <0x0 0x5b 0x4>;
565 sata3: sata@1a400000 {
566 compatible = "apm,xgene-ahci-v2";
567 reg = <0x0 0x1a400000 0x0 0x1000>,
568 <0x0 0x1f220000 0x0 0x1000>,
569 <0x0 0x1f22d000 0x0 0x1000>,
570 <0x0 0x1f22e000 0x0 0x1000>;
571 interrupts = <0x0 0x5c 0x4>;
576 compatible = "arasan,sdhci-4.9a";
577 reg = <0x0 0x1c000000 0x0 0x100>;
578 interrupts = <0x0 0x49 0x4>;
581 clock-names = "clk_xin", "clk_ahb";
582 clocks = <&sdioclk 0>, <&ahbclk 0>;
585 gfcgpio: gpio@1f63c000 {
586 compatible = "apm,xgene-gpio";
587 reg = <0x0 0x1f63c000 0x0 0x40>;
592 dwgpio: gpio@1c024000 {
593 compatible = "snps,dw-apb-gpio";
594 reg = <0x0 0x1c024000 0x0 0x1000>;
596 #address-cells = <1>;
599 porta: gpio-controller@0 {
600 compatible = "snps,dw-apb-gpio-port";
602 snps,nr-gpios = <32>;
607 sbgpio: gpio@17001000{
608 compatible = "apm,xgene-gpio-sb";
609 reg = <0x0 0x17001000 0x0 0x400>;
612 interrupts = <0x0 0x28 0x1>,
620 interrupt-parent = <&gic>;
621 #interrupt-cells = <2>;
622 interrupt-controller;
628 mdio: mdio@1f610000 {
629 compatible = "apm,xgene-mdio-xfi";
630 #address-cells = <1>;
632 reg = <0x0 0x1f610000 0x0 0xd100>;
633 clocks = <&xge0clk 0>;
636 sgenet0: ethernet@1f610000 {
637 compatible = "apm,xgene2-sgenet";
639 reg = <0x0 0x1f610000 0x0 0xd100>,
640 <0x0 0x1f600000 0x0 0xd100>,
641 <0x0 0x20000000 0x0 0x20000>;
642 interrupts = <0 96 4>,
645 clocks = <&xge0clk 0>;
646 local-mac-address = [00 01 73 00 00 01];
647 phy-connection-type = "sgmii";
648 phy-handle = <&sgenet0phy>;
651 xgenet1: ethernet@1f620000 {
652 compatible = "apm,xgene2-xgenet";
654 reg = <0x0 0x1f620000 0x0 0x10000>,
655 <0x0 0x1f600000 0x0 0xd100>,
656 <0x0 0x20000000 0x0 0x220000>;
657 interrupts = <0 108 4>,
668 clocks = <&xge1clk 0>;
669 local-mac-address = [00 01 73 00 00 02];
670 phy-connection-type = "xgmii";
674 compatible = "apm,xgene-rng";
675 reg = <0x0 0x10520000 0x0 0x100>;
676 interrupts = <0x0 0x41 0x4>;
677 clocks = <&rngpkaclk 0>;
681 #address-cells = <1>;
683 compatible = "snps,designware-i2c";
684 reg = <0x0 0x10511000 0x0 0x1000>;
685 interrupts = <0 0x45 0x4>;
687 clocks = <&sbapbclk 0>;
692 #address-cells = <1>;
694 compatible = "snps,designware-i2c";
695 reg = <0x0 0x10640000 0x0 0x1000>;
696 interrupts = <0 0x3a 0x4>;
697 clocks = <&i2c4clk 0>;