2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
4 * Copyright (C) 2015, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
24 compatible = "apm,strega", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,strega", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,strega", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,strega", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,strega", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,strega", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,strega", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,strega", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78090000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
86 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
87 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
88 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
89 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
90 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
91 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
95 compatible = "arm,armv8-pmuv3";
96 interrupts = <1 12 0xff04>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
102 <1 13 0xff04>, /* Non-secure Phys IRQ */
103 <1 14 0xff04>, /* Virt IRQ */
104 <1 15 0xff04>; /* Hyp IRQ */
105 clock-frequency = <50000000>;
109 compatible = "simple-bus";
110 #address-cells = <2>;
115 #address-cells = <2>;
120 compatible = "fixed-clock";
122 clock-frequency = <100000000>;
123 clock-output-names = "refclk";
126 socpll: socpll@17000120 {
127 compatible = "apm,xgene-socpll-clock";
129 clocks = <&refclk 0>;
130 reg = <0x0 0x17000120 0x0 0x1000>;
131 clock-output-names = "socpll";
134 socplldiv2: socplldiv2 {
135 compatible = "fixed-factor-clock";
137 clocks = <&socpll 0>;
140 clock-output-names = "socplldiv2";
143 ahbclk: ahbclk@1f2ac000 {
144 compatible = "apm,xgene-device-clock";
146 clocks = <&socplldiv2 0>;
147 reg = <0x0 0x1f2ac000 0x0 0x1000
148 0x0 0x17000000 0x0 0x2000>;
149 reg-names = "csr-reg", "div-reg";
152 enable-offset = <0x8>;
154 divider-offset = <0x164>;
155 divider-width = <0x5>;
156 divider-shift = <0x0>;
157 clock-output-names = "ahbclk";
160 sdioclk: sdioclk@1f2ac000 {
161 compatible = "apm,xgene-device-clock";
163 clocks = <&socplldiv2 0>;
164 reg = <0x0 0x1f2ac000 0x0 0x1000
165 0x0 0x17000000 0x0 0x2000>;
166 reg-names = "csr-reg", "div-reg";
169 enable-offset = <0x8>;
171 divider-offset = <0x178>;
172 divider-width = <0x8>;
173 divider-shift = <0x0>;
174 clock-output-names = "sdioclk";
177 pcie0clk: pcie0clk@1f2bc000 {
178 compatible = "apm,xgene-device-clock";
180 clocks = <&socplldiv2 0>;
181 reg = <0x0 0x1f2bc000 0x0 0x1000>;
182 reg-names = "csr-reg";
183 clock-output-names = "pcie0clk";
186 xge0clk: xge0clk@1f61c000 {
187 compatible = "apm,xgene-device-clock";
189 clocks = <&socplldiv2 0>;
190 reg = <0x0 0x1f61c000 0x0 0x1000>;
191 reg-names = "csr-reg";
194 clock-output-names = "xge0clk";
197 xge1clk: xge1clk@1f62c000 {
198 compatible = "apm,xgene-device-clock";
200 clocks = <&socplldiv2 0>;
201 reg = <0x0 0x1f62c000 0x0 0x1000>;
202 reg-names = "csr-reg";
205 clock-output-names = "xge1clk";
209 scu: system-clk-controller@17000000 {
210 compatible = "apm,xgene-scu","syscon";
211 reg = <0x0 0x17000000 0x0 0x400>;
214 reboot: reboot@17000014 {
215 compatible = "syscon-reboot";
221 serial0: serial@10600000 {
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0 0x10600000 0x0 0x1000>;
226 clock-frequency = <10000000>;
227 interrupt-parent = <&gic>;
228 interrupts = <0x0 0x4c 0x4>;
231 sata1: sata@1a000000 {
232 compatible = "apm,xgene-ahci";
233 reg = <0x0 0x1a000000 0x0 0x1000>,
234 <0x0 0x1f200000 0x0 0x1000>,
235 <0x0 0x1f20d000 0x0 0x1000>,
236 <0x0 0x1f20e000 0x0 0x1000>;
237 interrupts = <0x0 0x5a 0x4>;
241 sata2: sata@1a200000 {
242 compatible = "apm,xgene-ahci";
243 reg = <0x0 0x1a200000 0x0 0x1000>,
244 <0x0 0x1f210000 0x0 0x1000>,
245 <0x0 0x1f21d000 0x0 0x1000>,
246 <0x0 0x1f21e000 0x0 0x1000>;
247 interrupts = <0x0 0x5b 0x4>;
251 sata3: sata@1a400000 {
252 compatible = "apm,xgene-ahci";
253 reg = <0x0 0x1a400000 0x0 0x1000>,
254 <0x0 0x1f220000 0x0 0x1000>,
255 <0x0 0x1f22d000 0x0 0x1000>,
256 <0x0 0x1f22e000 0x0 0x1000>;
257 interrupts = <0x0 0x5c 0x4>;
262 compatible = "arasan,sdhci-4.9a";
263 reg = <0x0 0x1c000000 0x0 0x100>;
264 interrupts = <0x0 0x49 0x4>;
267 clock-names = "clk_xin", "clk_ahb";
268 clocks = <&sdioclk 0>, <&ahbclk 0>;
271 sbgpio: sbgpio@17001000{
272 compatible = "apm,xgene-gpio-sb";
273 reg = <0x0 0x17001000 0x0 0x400>;
276 interrupts = <0x0 0x28 0x1>,
286 sgenet0: ethernet@1f610000 {
287 compatible = "apm,xgene2-sgenet";
289 reg = <0x0 0x1f610000 0x0 0x10000>,
290 <0x0 0x1f600000 0x0 0Xd100>,
291 <0x0 0x20000000 0x0 0X20000>;
292 interrupts = <0 96 4>,
295 clocks = <&xge0clk 0>;
296 local-mac-address = [00 01 73 00 00 01];
297 phy-connection-type = "sgmii";
300 xgenet1: ethernet@1f620000 {
301 compatible = "apm,xgene2-xgenet";
303 reg = <0x0 0x1f620000 0x0 0x10000>,
304 <0x0 0x1f600000 0x0 0Xd100>,
305 <0x0 0x20000000 0x0 0X220000>;
306 interrupts = <0 108 4>,
310 clocks = <&xge1clk 0>;
311 local-mac-address = [00 01 73 00 00 02];
312 phy-connection-type = "xgmii";