2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
72 compatible = "arm,cortex-a53";
74 clocks = <&clockgen 1 0>;
79 compatible = "arm,cortex-a53";
81 clocks = <&clockgen 1 0>;
86 compatible = "arm,cortex-a53";
88 clocks = <&clockgen 1 0>;
93 device_type = "memory";
94 reg = <0x0 0x80000000 0 0x80000000>;
95 /* DRAM space 1, size: 2GiB DRAM */
99 compatible = "fixed-clock";
101 clock-frequency = <100000000>;
102 clock-output-names = "sysclk";
106 compatible ="syscon-reboot";
113 compatible = "arm,armv8-timer";
114 interrupts = <1 13 0x1>, /* Physical Secure PPI */
115 <1 14 0x1>, /* Physical Non-Secure PPI */
116 <1 11 0x1>, /* Virtual PPI */
117 <1 10 0x1>; /* Hypervisor PPI */
121 compatible = "arm,armv8-pmuv3";
122 interrupts = <0 106 0x4>,
126 interrupt-affinity = <&cpu0>,
132 gic: interrupt-controller@1400000 {
133 compatible = "arm,gic-400";
134 #interrupt-cells = <3>;
135 interrupt-controller;
136 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
137 <0x0 0x1402000 0 0x2000>, /* GICC */
138 <0x0 0x1404000 0 0x2000>, /* GICH */
139 <0x0 0x1406000 0 0x2000>; /* GICV */
140 interrupts = <1 9 0xf08>;
144 compatible = "simple-bus";
145 #address-cells = <2>;
149 clockgen: clocking@1ee1000 {
150 compatible = "fsl,ls1043a-clockgen";
151 reg = <0x0 0x1ee1000 0x0 0x1000>;
157 compatible = "fsl,ls1043a-scfg", "syscon";
158 reg = <0x0 0x1570000 0x0 0x10000>;
163 compatible = "fsl,ls1043a-dcfg", "syscon";
164 reg = <0x0 0x1ee0000 0x0 0x10000>;
169 compatible = "fsl,ifc", "simple-bus";
170 reg = <0x0 0x1530000 0x0 0x10000>;
171 interrupts = <0 43 0x4>;
174 esdhc: esdhc@1560000 {
175 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
176 reg = <0x0 0x1560000 0x0 0x10000>;
177 interrupts = <0 62 0x4>;
178 clock-frequency = <0>;
179 voltage-ranges = <1800 1800 3300 3300>;
185 dspi0: dspi@2100000 {
186 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
187 #address-cells = <1>;
189 reg = <0x0 0x2100000 0x0 0x10000>;
190 interrupts = <0 64 0x4>;
191 clock-names = "dspi";
192 clocks = <&clockgen 4 0>;
193 spi-num-chipselects = <5>;
198 dspi1: dspi@2110000 {
199 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
200 #address-cells = <1>;
202 reg = <0x0 0x2110000 0x0 0x10000>;
203 interrupts = <0 65 0x4>;
204 clock-names = "dspi";
205 clocks = <&clockgen 4 0>;
206 spi-num-chipselects = <5>;
212 compatible = "fsl,vf610-i2c";
213 #address-cells = <1>;
215 reg = <0x0 0x2180000 0x0 0x10000>;
216 interrupts = <0 56 0x4>;
218 clocks = <&clockgen 4 0>;
219 dmas = <&edma0 1 39>,
221 dma-names = "tx", "rx";
226 compatible = "fsl,vf610-i2c";
227 #address-cells = <1>;
229 reg = <0x0 0x2190000 0x0 0x10000>;
230 interrupts = <0 57 0x4>;
232 clocks = <&clockgen 4 0>;
237 compatible = "fsl,vf610-i2c";
238 #address-cells = <1>;
240 reg = <0x0 0x21a0000 0x0 0x10000>;
241 interrupts = <0 58 0x4>;
243 clocks = <&clockgen 4 0>;
248 compatible = "fsl,vf610-i2c";
249 #address-cells = <1>;
251 reg = <0x0 0x21b0000 0x0 0x10000>;
252 interrupts = <0 59 0x4>;
254 clocks = <&clockgen 4 0>;
258 duart0: serial@21c0500 {
259 compatible = "fsl,ns16550", "ns16550a";
260 reg = <0x00 0x21c0500 0x0 0x100>;
261 interrupts = <0 54 0x4>;
262 clocks = <&clockgen 4 0>;
265 duart1: serial@21c0600 {
266 compatible = "fsl,ns16550", "ns16550a";
267 reg = <0x00 0x21c0600 0x0 0x100>;
268 interrupts = <0 54 0x4>;
269 clocks = <&clockgen 4 0>;
272 duart2: serial@21d0500 {
273 compatible = "fsl,ns16550", "ns16550a";
274 reg = <0x0 0x21d0500 0x0 0x100>;
275 interrupts = <0 55 0x4>;
276 clocks = <&clockgen 4 0>;
279 duart3: serial@21d0600 {
280 compatible = "fsl,ns16550", "ns16550a";
281 reg = <0x0 0x21d0600 0x0 0x100>;
282 interrupts = <0 55 0x4>;
283 clocks = <&clockgen 4 0>;
286 gpio1: gpio@2300000 {
287 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
288 reg = <0x0 0x2300000 0x0 0x10000>;
289 interrupts = <0 66 0x4>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
296 gpio2: gpio@2310000 {
297 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
298 reg = <0x0 0x2310000 0x0 0x10000>;
299 interrupts = <0 67 0x4>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
306 gpio3: gpio@2320000 {
307 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
308 reg = <0x0 0x2320000 0x0 0x10000>;
309 interrupts = <0 68 0x4>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
316 gpio4: gpio@2330000 {
317 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
318 reg = <0x0 0x2330000 0x0 0x10000>;
319 interrupts = <0 134 0x4>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
326 lpuart0: serial@2950000 {
327 compatible = "fsl,ls1021a-lpuart";
328 reg = <0x0 0x2950000 0x0 0x1000>;
329 interrupts = <0 48 0x4>;
330 clocks = <&clockgen 0 0>;
335 lpuart1: serial@2960000 {
336 compatible = "fsl,ls1021a-lpuart";
337 reg = <0x0 0x2960000 0x0 0x1000>;
338 interrupts = <0 49 0x4>;
339 clocks = <&clockgen 4 0>;
344 lpuart2: serial@2970000 {
345 compatible = "fsl,ls1021a-lpuart";
346 reg = <0x0 0x2970000 0x0 0x1000>;
347 interrupts = <0 50 0x4>;
348 clocks = <&clockgen 4 0>;
353 lpuart3: serial@2980000 {
354 compatible = "fsl,ls1021a-lpuart";
355 reg = <0x0 0x2980000 0x0 0x1000>;
356 interrupts = <0 51 0x4>;
357 clocks = <&clockgen 4 0>;
362 lpuart4: serial@2990000 {
363 compatible = "fsl,ls1021a-lpuart";
364 reg = <0x0 0x2990000 0x0 0x1000>;
365 interrupts = <0 52 0x4>;
366 clocks = <&clockgen 4 0>;
371 lpuart5: serial@29a0000 {
372 compatible = "fsl,ls1021a-lpuart";
373 reg = <0x0 0x29a0000 0x0 0x1000>;
374 interrupts = <0 53 0x4>;
375 clocks = <&clockgen 4 0>;
380 wdog0: wdog@2ad0000 {
381 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
382 reg = <0x0 0x2ad0000 0x0 0x10000>;
383 interrupts = <0 83 0x4>;
384 clocks = <&clockgen 4 0>;
385 clock-names = "wdog";
389 edma0: edma@2c00000 {
391 compatible = "fsl,vf610-edma";
392 reg = <0x0 0x2c00000 0x0 0x10000>,
393 <0x0 0x2c10000 0x0 0x10000>,
394 <0x0 0x2c20000 0x0 0x10000>;
395 interrupts = <0 103 0x4>,
397 interrupt-names = "edma-tx", "edma-err";
400 clock-names = "dmamux0", "dmamux1";
401 clocks = <&clockgen 4 0>,
406 compatible = "snps,dwc3";
407 reg = <0x0 0x2f00000 0x0 0x10000>;
408 interrupts = <0 60 0x4>;
410 snps,quirk-frame-length-adjustment = <0x20>;
414 compatible = "snps,dwc3";
415 reg = <0x0 0x3000000 0x0 0x10000>;
416 interrupts = <0 61 0x4>;
418 snps,quirk-frame-length-adjustment = <0x20>;
422 compatible = "snps,dwc3";
423 reg = <0x0 0x3100000 0x0 0x10000>;
424 interrupts = <0 63 0x4>;
426 snps,quirk-frame-length-adjustment = <0x20>;
430 compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
431 reg = <0x0 0x3200000 0x0 0x10000>;
432 interrupts = <0 69 0x4>;
433 clocks = <&clockgen 4 0>;
436 msi1: msi-controller1@1571000 {
437 compatible = "fsl,1s1043a-msi";
438 reg = <0x0 0x1571000 0x0 0x8>;
440 interrupts = <0 116 0x4>;
443 msi2: msi-controller2@1572000 {
444 compatible = "fsl,1s1043a-msi";
445 reg = <0x0 0x1572000 0x0 0x8>;
447 interrupts = <0 126 0x4>;
450 msi3: msi-controller3@1573000 {
451 compatible = "fsl,1s1043a-msi";
452 reg = <0x0 0x1573000 0x0 0x8>;
454 interrupts = <0 160 0x4>;
458 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
459 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
460 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
461 reg-names = "regs", "config";
462 interrupts = <0 118 0x4>, /* controller interrupt */
463 <0 117 0x4>; /* PME interrupt */
464 interrupt-names = "intr", "pme";
465 #address-cells = <3>;
469 bus-range = <0x0 0xff>;
470 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
471 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
472 msi-parent = <&msi1>;
473 #interrupt-cells = <1>;
474 interrupt-map-mask = <0 0 0 7>;
475 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
476 <0000 0 0 2 &gic 0 111 0x4>,
477 <0000 0 0 3 &gic 0 112 0x4>,
478 <0000 0 0 4 &gic 0 113 0x4>;
482 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
483 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
484 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
485 reg-names = "regs", "config";
486 interrupts = <0 128 0x4>,
488 interrupt-names = "intr", "pme";
489 #address-cells = <3>;
493 bus-range = <0x0 0xff>;
494 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
495 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
496 msi-parent = <&msi2>;
497 #interrupt-cells = <1>;
498 interrupt-map-mask = <0 0 0 7>;
499 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
500 <0000 0 0 2 &gic 0 121 0x4>,
501 <0000 0 0 3 &gic 0 122 0x4>,
502 <0000 0 0 4 &gic 0 123 0x4>;
506 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
507 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
508 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
509 reg-names = "regs", "config";
510 interrupts = <0 162 0x4>,
512 interrupt-names = "intr", "pme";
513 #address-cells = <3>;
517 bus-range = <0x0 0xff>;
518 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
519 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
520 msi-parent = <&msi3>;
521 #interrupt-cells = <1>;
522 interrupt-map-mask = <0 0 0 7>;
523 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
524 <0000 0 0 2 &gic 0 155 0x4>,
525 <0000 0 0 3 &gic 0 156 0x4>,
526 <0000 0 0 4 &gic 0 157 0x4>;