2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a53";
75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a53";
83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
89 compatible = "arm,cortex-a53";
91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
101 device_type = "memory";
102 reg = <0x0 0x80000000 0 0x80000000>;
103 /* DRAM space 1, size: 2GiB DRAM */
107 compatible = "fixed-clock";
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
114 compatible ="syscon-reboot";
121 compatible = "arm,armv8-timer";
122 interrupts = <1 13 0x1>, /* Physical Secure PPI */
123 <1 14 0x1>, /* Physical Non-Secure PPI */
124 <1 11 0x1>, /* Virtual PPI */
125 <1 10 0x1>; /* Hypervisor PPI */
129 compatible = "arm,armv8-pmuv3";
130 interrupts = <0 106 0x4>,
134 interrupt-affinity = <&cpu0>,
140 gic: interrupt-controller@1400000 {
141 compatible = "arm,gic-400";
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
145 <0x0 0x1402000 0 0x2000>, /* GICC */
146 <0x0 0x1404000 0 0x2000>, /* GICH */
147 <0x0 0x1406000 0 0x2000>; /* GICV */
148 interrupts = <1 9 0xf08>;
152 compatible = "simple-bus";
153 #address-cells = <2>;
157 clockgen: clocking@1ee1000 {
158 compatible = "fsl,ls1043a-clockgen";
159 reg = <0x0 0x1ee1000 0x0 0x1000>;
165 compatible = "fsl,ls1043a-scfg", "syscon";
166 reg = <0x0 0x1570000 0x0 0x10000>;
170 crypto: crypto@1700000 {
171 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
174 #address-cells = <1>;
176 ranges = <0x0 0x00 0x1700000 0x100000>;
177 reg = <0x00 0x1700000 0x0 0x100000>;
178 interrupts = <0 75 0x4>;
181 compatible = "fsl,sec-v5.4-job-ring",
182 "fsl,sec-v5.0-job-ring",
183 "fsl,sec-v4.0-job-ring";
184 reg = <0x10000 0x10000>;
185 interrupts = <0 71 0x4>;
189 compatible = "fsl,sec-v5.4-job-ring",
190 "fsl,sec-v5.0-job-ring",
191 "fsl,sec-v4.0-job-ring";
192 reg = <0x20000 0x10000>;
193 interrupts = <0 72 0x4>;
197 compatible = "fsl,sec-v5.4-job-ring",
198 "fsl,sec-v5.0-job-ring",
199 "fsl,sec-v4.0-job-ring";
200 reg = <0x30000 0x10000>;
201 interrupts = <0 73 0x4>;
205 compatible = "fsl,sec-v5.4-job-ring",
206 "fsl,sec-v5.0-job-ring",
207 "fsl,sec-v4.0-job-ring";
208 reg = <0x40000 0x10000>;
209 interrupts = <0 74 0x4>;
214 compatible = "fsl,ls1043a-dcfg", "syscon";
215 reg = <0x0 0x1ee0000 0x0 0x10000>;
220 compatible = "fsl,ifc", "simple-bus";
221 reg = <0x0 0x1530000 0x0 0x10000>;
222 interrupts = <0 43 0x4>;
225 qspi: quadspi@1550000 {
226 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
227 #address-cells = <1>;
229 reg = <0x0 0x1550000 0x0 0x10000>,
230 <0x0 0x40000000 0x0 0x4000000>;
231 reg-names = "QuadSPI", "QuadSPI-memory";
232 interrupts = <0 99 0x4>;
233 clock-names = "qspi_en", "qspi";
234 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
239 esdhc: esdhc@1560000 {
240 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
241 reg = <0x0 0x1560000 0x0 0x10000>;
242 interrupts = <0 62 0x4>;
243 clock-frequency = <0>;
244 voltage-ranges = <1800 1800 3300 3300>;
250 dspi0: dspi@2100000 {
251 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
252 #address-cells = <1>;
254 reg = <0x0 0x2100000 0x0 0x10000>;
255 interrupts = <0 64 0x4>;
256 clock-names = "dspi";
257 clocks = <&clockgen 4 0>;
258 spi-num-chipselects = <5>;
263 dspi1: dspi@2110000 {
264 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
265 #address-cells = <1>;
267 reg = <0x0 0x2110000 0x0 0x10000>;
268 interrupts = <0 65 0x4>;
269 clock-names = "dspi";
270 clocks = <&clockgen 4 0>;
271 spi-num-chipselects = <5>;
277 compatible = "fsl,vf610-i2c";
278 #address-cells = <1>;
280 reg = <0x0 0x2180000 0x0 0x10000>;
281 interrupts = <0 56 0x4>;
283 clocks = <&clockgen 4 0>;
284 dmas = <&edma0 1 39>,
286 dma-names = "tx", "rx";
291 compatible = "fsl,vf610-i2c";
292 #address-cells = <1>;
294 reg = <0x0 0x2190000 0x0 0x10000>;
295 interrupts = <0 57 0x4>;
297 clocks = <&clockgen 4 0>;
302 compatible = "fsl,vf610-i2c";
303 #address-cells = <1>;
305 reg = <0x0 0x21a0000 0x0 0x10000>;
306 interrupts = <0 58 0x4>;
308 clocks = <&clockgen 4 0>;
313 compatible = "fsl,vf610-i2c";
314 #address-cells = <1>;
316 reg = <0x0 0x21b0000 0x0 0x10000>;
317 interrupts = <0 59 0x4>;
319 clocks = <&clockgen 4 0>;
323 duart0: serial@21c0500 {
324 compatible = "fsl,ns16550", "ns16550a";
325 reg = <0x00 0x21c0500 0x0 0x100>;
326 interrupts = <0 54 0x4>;
327 clocks = <&clockgen 4 0>;
330 duart1: serial@21c0600 {
331 compatible = "fsl,ns16550", "ns16550a";
332 reg = <0x00 0x21c0600 0x0 0x100>;
333 interrupts = <0 54 0x4>;
334 clocks = <&clockgen 4 0>;
337 duart2: serial@21d0500 {
338 compatible = "fsl,ns16550", "ns16550a";
339 reg = <0x0 0x21d0500 0x0 0x100>;
340 interrupts = <0 55 0x4>;
341 clocks = <&clockgen 4 0>;
344 duart3: serial@21d0600 {
345 compatible = "fsl,ns16550", "ns16550a";
346 reg = <0x0 0x21d0600 0x0 0x100>;
347 interrupts = <0 55 0x4>;
348 clocks = <&clockgen 4 0>;
351 gpio1: gpio@2300000 {
352 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
353 reg = <0x0 0x2300000 0x0 0x10000>;
354 interrupts = <0 66 0x4>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
361 gpio2: gpio@2310000 {
362 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
363 reg = <0x0 0x2310000 0x0 0x10000>;
364 interrupts = <0 67 0x4>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
371 gpio3: gpio@2320000 {
372 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
373 reg = <0x0 0x2320000 0x0 0x10000>;
374 interrupts = <0 68 0x4>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
381 gpio4: gpio@2330000 {
382 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
383 reg = <0x0 0x2330000 0x0 0x10000>;
384 interrupts = <0 134 0x4>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
391 lpuart0: serial@2950000 {
392 compatible = "fsl,ls1021a-lpuart";
393 reg = <0x0 0x2950000 0x0 0x1000>;
394 interrupts = <0 48 0x4>;
395 clocks = <&clockgen 0 0>;
400 lpuart1: serial@2960000 {
401 compatible = "fsl,ls1021a-lpuart";
402 reg = <0x0 0x2960000 0x0 0x1000>;
403 interrupts = <0 49 0x4>;
404 clocks = <&clockgen 4 0>;
409 lpuart2: serial@2970000 {
410 compatible = "fsl,ls1021a-lpuart";
411 reg = <0x0 0x2970000 0x0 0x1000>;
412 interrupts = <0 50 0x4>;
413 clocks = <&clockgen 4 0>;
418 lpuart3: serial@2980000 {
419 compatible = "fsl,ls1021a-lpuart";
420 reg = <0x0 0x2980000 0x0 0x1000>;
421 interrupts = <0 51 0x4>;
422 clocks = <&clockgen 4 0>;
427 lpuart4: serial@2990000 {
428 compatible = "fsl,ls1021a-lpuart";
429 reg = <0x0 0x2990000 0x0 0x1000>;
430 interrupts = <0 52 0x4>;
431 clocks = <&clockgen 4 0>;
436 lpuart5: serial@29a0000 {
437 compatible = "fsl,ls1021a-lpuart";
438 reg = <0x0 0x29a0000 0x0 0x1000>;
439 interrupts = <0 53 0x4>;
440 clocks = <&clockgen 4 0>;
445 wdog0: wdog@2ad0000 {
446 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
447 reg = <0x0 0x2ad0000 0x0 0x10000>;
448 interrupts = <0 83 0x4>;
449 clocks = <&clockgen 4 0>;
450 clock-names = "wdog";
454 edma0: edma@2c00000 {
456 compatible = "fsl,vf610-edma";
457 reg = <0x0 0x2c00000 0x0 0x10000>,
458 <0x0 0x2c10000 0x0 0x10000>,
459 <0x0 0x2c20000 0x0 0x10000>;
460 interrupts = <0 103 0x4>,
462 interrupt-names = "edma-tx", "edma-err";
465 clock-names = "dmamux0", "dmamux1";
466 clocks = <&clockgen 4 0>,
471 compatible = "snps,dwc3";
472 reg = <0x0 0x2f00000 0x0 0x10000>;
473 interrupts = <0 60 0x4>;
475 snps,quirk-frame-length-adjustment = <0x20>;
476 snps,dis_rxdet_inp3_quirk;
480 compatible = "snps,dwc3";
481 reg = <0x0 0x3000000 0x0 0x10000>;
482 interrupts = <0 61 0x4>;
484 snps,quirk-frame-length-adjustment = <0x20>;
485 snps,dis_rxdet_inp3_quirk;
489 compatible = "snps,dwc3";
490 reg = <0x0 0x3100000 0x0 0x10000>;
491 interrupts = <0 63 0x4>;
493 snps,quirk-frame-length-adjustment = <0x20>;
494 snps,dis_rxdet_inp3_quirk;
498 compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
499 reg = <0x0 0x3200000 0x0 0x10000>;
500 interrupts = <0 69 0x4>;
501 clocks = <&clockgen 4 0>;
504 msi1: msi-controller1@1571000 {
505 compatible = "fsl,1s1043a-msi";
506 reg = <0x0 0x1571000 0x0 0x8>;
508 interrupts = <0 116 0x4>;
511 msi2: msi-controller2@1572000 {
512 compatible = "fsl,1s1043a-msi";
513 reg = <0x0 0x1572000 0x0 0x8>;
515 interrupts = <0 126 0x4>;
518 msi3: msi-controller3@1573000 {
519 compatible = "fsl,1s1043a-msi";
520 reg = <0x0 0x1573000 0x0 0x8>;
522 interrupts = <0 160 0x4>;
526 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
527 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
528 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
529 reg-names = "regs", "config";
530 interrupts = <0 118 0x4>, /* controller interrupt */
531 <0 117 0x4>; /* PME interrupt */
532 interrupt-names = "intr", "pme";
533 #address-cells = <3>;
538 bus-range = <0x0 0xff>;
539 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
540 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
541 msi-parent = <&msi1>;
542 #interrupt-cells = <1>;
543 interrupt-map-mask = <0 0 0 7>;
544 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
545 <0000 0 0 2 &gic 0 111 0x4>,
546 <0000 0 0 3 &gic 0 112 0x4>,
547 <0000 0 0 4 &gic 0 113 0x4>;
551 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
552 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
553 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
554 reg-names = "regs", "config";
555 interrupts = <0 128 0x4>,
557 interrupt-names = "intr", "pme";
558 #address-cells = <3>;
563 bus-range = <0x0 0xff>;
564 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
565 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
566 msi-parent = <&msi2>;
567 #interrupt-cells = <1>;
568 interrupt-map-mask = <0 0 0 7>;
569 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
570 <0000 0 0 2 &gic 0 121 0x4>,
571 <0000 0 0 3 &gic 0 122 0x4>,
572 <0000 0 0 4 &gic 0 123 0x4>;
576 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
577 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
578 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
579 reg-names = "regs", "config";
580 interrupts = <0 162 0x4>,
582 interrupt-names = "intr", "pme";
583 #address-cells = <3>;
588 bus-range = <0x0 0xff>;
589 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
590 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
591 msi-parent = <&msi3>;
592 #interrupt-cells = <1>;
593 interrupt-map-mask = <0 0 0 7>;
594 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
595 <0000 0 0 2 &gic 0 155 0x4>,
596 <0000 0 0 3 &gic 0 156 0x4>,
597 <0000 0 0 4 &gic 0 157 0x4>;