2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
72 compatible = "arm,cortex-a53";
74 clocks = <&clockgen 1 0>;
79 compatible = "arm,cortex-a53";
81 clocks = <&clockgen 1 0>;
86 compatible = "arm,cortex-a53";
88 clocks = <&clockgen 1 0>;
93 device_type = "memory";
94 reg = <0x0 0x80000000 0 0x80000000>;
95 /* DRAM space 1, size: 2GiB DRAM */
99 compatible = "fixed-clock";
101 clock-frequency = <100000000>;
102 clock-output-names = "sysclk";
106 compatible ="syscon-reboot";
113 compatible = "arm,armv8-timer";
114 interrupts = <1 13 0x1>, /* Physical Secure PPI */
115 <1 14 0x1>, /* Physical Non-Secure PPI */
116 <1 11 0x1>, /* Virtual PPI */
117 <1 10 0x1>; /* Hypervisor PPI */
121 compatible = "arm,armv8-pmuv3";
122 interrupts = <0 106 0x4>,
126 interrupt-affinity = <&cpu0>,
132 gic: interrupt-controller@1400000 {
133 compatible = "arm,gic-400";
134 #interrupt-cells = <3>;
135 interrupt-controller;
136 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
137 <0x0 0x1402000 0 0x2000>, /* GICC */
138 <0x0 0x1404000 0 0x2000>, /* GICH */
139 <0x0 0x1406000 0 0x2000>; /* GICV */
140 interrupts = <1 9 0xf08>;
144 compatible = "simple-bus";
145 #address-cells = <2>;
149 clockgen: clocking@1ee1000 {
150 compatible = "fsl,ls1043a-clockgen";
151 reg = <0x0 0x1ee1000 0x0 0x1000>;
157 compatible = "fsl,ls1043a-scfg", "syscon";
158 reg = <0x0 0x1570000 0x0 0x10000>;
162 crypto: crypto@1700000 {
163 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
166 #address-cells = <1>;
168 ranges = <0x0 0x00 0x1700000 0x100000>;
169 reg = <0x00 0x1700000 0x0 0x100000>;
170 interrupts = <0 75 0x4>;
173 compatible = "fsl,sec-v5.4-job-ring",
174 "fsl,sec-v5.0-job-ring",
175 "fsl,sec-v4.0-job-ring";
176 reg = <0x10000 0x10000>;
177 interrupts = <0 71 0x4>;
181 compatible = "fsl,sec-v5.4-job-ring",
182 "fsl,sec-v5.0-job-ring",
183 "fsl,sec-v4.0-job-ring";
184 reg = <0x20000 0x10000>;
185 interrupts = <0 72 0x4>;
189 compatible = "fsl,sec-v5.4-job-ring",
190 "fsl,sec-v5.0-job-ring",
191 "fsl,sec-v4.0-job-ring";
192 reg = <0x30000 0x10000>;
193 interrupts = <0 73 0x4>;
197 compatible = "fsl,sec-v5.4-job-ring",
198 "fsl,sec-v5.0-job-ring",
199 "fsl,sec-v4.0-job-ring";
200 reg = <0x40000 0x10000>;
201 interrupts = <0 74 0x4>;
206 compatible = "fsl,ls1043a-dcfg", "syscon";
207 reg = <0x0 0x1ee0000 0x0 0x10000>;
212 compatible = "fsl,ifc", "simple-bus";
213 reg = <0x0 0x1530000 0x0 0x10000>;
214 interrupts = <0 43 0x4>;
217 qspi: quadspi@1550000 {
218 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
219 #address-cells = <1>;
221 reg = <0x0 0x1550000 0x0 0x10000>,
222 <0x0 0x40000000 0x0 0x4000000>;
223 reg-names = "QuadSPI", "QuadSPI-memory";
224 interrupts = <0 99 0x4>;
225 clock-names = "qspi_en", "qspi";
226 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
231 esdhc: esdhc@1560000 {
232 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
233 reg = <0x0 0x1560000 0x0 0x10000>;
234 interrupts = <0 62 0x4>;
235 clock-frequency = <0>;
236 voltage-ranges = <1800 1800 3300 3300>;
242 dspi0: dspi@2100000 {
243 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
244 #address-cells = <1>;
246 reg = <0x0 0x2100000 0x0 0x10000>;
247 interrupts = <0 64 0x4>;
248 clock-names = "dspi";
249 clocks = <&clockgen 4 0>;
250 spi-num-chipselects = <5>;
255 dspi1: dspi@2110000 {
256 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
257 #address-cells = <1>;
259 reg = <0x0 0x2110000 0x0 0x10000>;
260 interrupts = <0 65 0x4>;
261 clock-names = "dspi";
262 clocks = <&clockgen 4 0>;
263 spi-num-chipselects = <5>;
269 compatible = "fsl,vf610-i2c";
270 #address-cells = <1>;
272 reg = <0x0 0x2180000 0x0 0x10000>;
273 interrupts = <0 56 0x4>;
275 clocks = <&clockgen 4 0>;
276 dmas = <&edma0 1 39>,
278 dma-names = "tx", "rx";
283 compatible = "fsl,vf610-i2c";
284 #address-cells = <1>;
286 reg = <0x0 0x2190000 0x0 0x10000>;
287 interrupts = <0 57 0x4>;
289 clocks = <&clockgen 4 0>;
294 compatible = "fsl,vf610-i2c";
295 #address-cells = <1>;
297 reg = <0x0 0x21a0000 0x0 0x10000>;
298 interrupts = <0 58 0x4>;
300 clocks = <&clockgen 4 0>;
305 compatible = "fsl,vf610-i2c";
306 #address-cells = <1>;
308 reg = <0x0 0x21b0000 0x0 0x10000>;
309 interrupts = <0 59 0x4>;
311 clocks = <&clockgen 4 0>;
315 duart0: serial@21c0500 {
316 compatible = "fsl,ns16550", "ns16550a";
317 reg = <0x00 0x21c0500 0x0 0x100>;
318 interrupts = <0 54 0x4>;
319 clocks = <&clockgen 4 0>;
322 duart1: serial@21c0600 {
323 compatible = "fsl,ns16550", "ns16550a";
324 reg = <0x00 0x21c0600 0x0 0x100>;
325 interrupts = <0 54 0x4>;
326 clocks = <&clockgen 4 0>;
329 duart2: serial@21d0500 {
330 compatible = "fsl,ns16550", "ns16550a";
331 reg = <0x0 0x21d0500 0x0 0x100>;
332 interrupts = <0 55 0x4>;
333 clocks = <&clockgen 4 0>;
336 duart3: serial@21d0600 {
337 compatible = "fsl,ns16550", "ns16550a";
338 reg = <0x0 0x21d0600 0x0 0x100>;
339 interrupts = <0 55 0x4>;
340 clocks = <&clockgen 4 0>;
343 gpio1: gpio@2300000 {
344 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
345 reg = <0x0 0x2300000 0x0 0x10000>;
346 interrupts = <0 66 0x4>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
353 gpio2: gpio@2310000 {
354 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
355 reg = <0x0 0x2310000 0x0 0x10000>;
356 interrupts = <0 67 0x4>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
363 gpio3: gpio@2320000 {
364 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
365 reg = <0x0 0x2320000 0x0 0x10000>;
366 interrupts = <0 68 0x4>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
373 gpio4: gpio@2330000 {
374 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
375 reg = <0x0 0x2330000 0x0 0x10000>;
376 interrupts = <0 134 0x4>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
383 lpuart0: serial@2950000 {
384 compatible = "fsl,ls1021a-lpuart";
385 reg = <0x0 0x2950000 0x0 0x1000>;
386 interrupts = <0 48 0x4>;
387 clocks = <&clockgen 0 0>;
392 lpuart1: serial@2960000 {
393 compatible = "fsl,ls1021a-lpuart";
394 reg = <0x0 0x2960000 0x0 0x1000>;
395 interrupts = <0 49 0x4>;
396 clocks = <&clockgen 4 0>;
401 lpuart2: serial@2970000 {
402 compatible = "fsl,ls1021a-lpuart";
403 reg = <0x0 0x2970000 0x0 0x1000>;
404 interrupts = <0 50 0x4>;
405 clocks = <&clockgen 4 0>;
410 lpuart3: serial@2980000 {
411 compatible = "fsl,ls1021a-lpuart";
412 reg = <0x0 0x2980000 0x0 0x1000>;
413 interrupts = <0 51 0x4>;
414 clocks = <&clockgen 4 0>;
419 lpuart4: serial@2990000 {
420 compatible = "fsl,ls1021a-lpuart";
421 reg = <0x0 0x2990000 0x0 0x1000>;
422 interrupts = <0 52 0x4>;
423 clocks = <&clockgen 4 0>;
428 lpuart5: serial@29a0000 {
429 compatible = "fsl,ls1021a-lpuart";
430 reg = <0x0 0x29a0000 0x0 0x1000>;
431 interrupts = <0 53 0x4>;
432 clocks = <&clockgen 4 0>;
437 wdog0: wdog@2ad0000 {
438 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
439 reg = <0x0 0x2ad0000 0x0 0x10000>;
440 interrupts = <0 83 0x4>;
441 clocks = <&clockgen 4 0>;
442 clock-names = "wdog";
446 edma0: edma@2c00000 {
448 compatible = "fsl,vf610-edma";
449 reg = <0x0 0x2c00000 0x0 0x10000>,
450 <0x0 0x2c10000 0x0 0x10000>,
451 <0x0 0x2c20000 0x0 0x10000>;
452 interrupts = <0 103 0x4>,
454 interrupt-names = "edma-tx", "edma-err";
457 clock-names = "dmamux0", "dmamux1";
458 clocks = <&clockgen 4 0>,
463 compatible = "snps,dwc3";
464 reg = <0x0 0x2f00000 0x0 0x10000>;
465 interrupts = <0 60 0x4>;
467 snps,quirk-frame-length-adjustment = <0x20>;
471 compatible = "snps,dwc3";
472 reg = <0x0 0x3000000 0x0 0x10000>;
473 interrupts = <0 61 0x4>;
475 snps,quirk-frame-length-adjustment = <0x20>;
479 compatible = "snps,dwc3";
480 reg = <0x0 0x3100000 0x0 0x10000>;
481 interrupts = <0 63 0x4>;
483 snps,quirk-frame-length-adjustment = <0x20>;
487 compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
488 reg = <0x0 0x3200000 0x0 0x10000>;
489 interrupts = <0 69 0x4>;
490 clocks = <&clockgen 4 0>;
493 msi1: msi-controller1@1571000 {
494 compatible = "fsl,1s1043a-msi";
495 reg = <0x0 0x1571000 0x0 0x8>;
497 interrupts = <0 116 0x4>;
500 msi2: msi-controller2@1572000 {
501 compatible = "fsl,1s1043a-msi";
502 reg = <0x0 0x1572000 0x0 0x8>;
504 interrupts = <0 126 0x4>;
507 msi3: msi-controller3@1573000 {
508 compatible = "fsl,1s1043a-msi";
509 reg = <0x0 0x1573000 0x0 0x8>;
511 interrupts = <0 160 0x4>;
515 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
516 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
517 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
518 reg-names = "regs", "config";
519 interrupts = <0 118 0x4>, /* controller interrupt */
520 <0 117 0x4>; /* PME interrupt */
521 interrupt-names = "intr", "pme";
522 #address-cells = <3>;
526 bus-range = <0x0 0xff>;
527 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
528 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
529 msi-parent = <&msi1>;
530 #interrupt-cells = <1>;
531 interrupt-map-mask = <0 0 0 7>;
532 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
533 <0000 0 0 2 &gic 0 111 0x4>,
534 <0000 0 0 3 &gic 0 112 0x4>,
535 <0000 0 0 4 &gic 0 113 0x4>;
539 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
540 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
541 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
542 reg-names = "regs", "config";
543 interrupts = <0 128 0x4>,
545 interrupt-names = "intr", "pme";
546 #address-cells = <3>;
550 bus-range = <0x0 0xff>;
551 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
552 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
553 msi-parent = <&msi2>;
554 #interrupt-cells = <1>;
555 interrupt-map-mask = <0 0 0 7>;
556 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
557 <0000 0 0 2 &gic 0 121 0x4>,
558 <0000 0 0 3 &gic 0 122 0x4>,
559 <0000 0 0 4 &gic 0 123 0x4>;
563 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
564 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
565 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
566 reg-names = "regs", "config";
567 interrupts = <0 162 0x4>,
569 interrupt-names = "intr", "pme";
570 #address-cells = <3>;
574 bus-range = <0x0 0xff>;
575 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
576 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
577 msi-parent = <&msi3>;
578 #interrupt-cells = <1>;
579 interrupt-map-mask = <0 0 0 7>;
580 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
581 <0000 0 0 2 &gic 0 155 0x4>,
582 <0000 0 0 3 &gic 0 156 0x4>,
583 <0000 0 0 4 &gic 0 157 0x4>;