arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
   3  *
   4  * Copyright (C) 2014-2015, Freescale Semiconductor
   5  *
   6  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 / {
  48         compatible = "fsl,ls2080a";
  49         interrupt-parent = <&gic>;
  50         #address-cells = <2>;
  51         #size-cells = <2>;
  52
  53         cpus {
  54                 #address-cells = <2>;
  55                 #size-cells = <0>;
  56
  57                 /*
  58                  * We expect the enable-method for cpu's to be "psci", but this
  59                  * is dependent on the SoC FW, which will fill this in.
  60                  *
  61                  * Currently supported enable-method is psci v0.2
  62                  */
  63
  64                 /* We have 4 clusters having 2 Cortex-A57 cores each */
  65                 cpu@0 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a57";
  68                         reg = <0x0 0x0>;
  69                         clocks = <&clockgen 1 0>;
  70                 };
  71
  72                 cpu@1 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a57";
  75                         reg = <0x0 0x1>;
  76                         clocks = <&clockgen 1 0>;
  77                 };
  78
  79                 cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a57";
  82                         reg = <0x0 0x100>;
  83                         clocks = <&clockgen 1 1>;
  84                 };
  85
  86                 cpu@101 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a57";
  89                         reg = <0x0 0x101>;
  90                         clocks = <&clockgen 1 1>;
  91                 };
  92
  93                 cpu@200 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a57";
  96                         reg = <0x0 0x200>;
  97                         clocks = <&clockgen 1 2>;
  98                 };
  99
 100                 cpu@201 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a57";
 103                         reg = <0x0 0x201>;
 104                         clocks = <&clockgen 1 2>;
 105                 };
 106
 107                 cpu@300 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a57";
 110                         reg = <0x0 0x300>;
 111                         clocks = <&clockgen 1 3>;
 112                 };
 113
 114                 cpu@301 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a57";
 117                         reg = <0x0 0x301>;
 118                         clocks = <&clockgen 1 3>;
 119                 };
 120         };
 121
 122         memory@80000000 {
 123                 device_type = "memory";
 124                 reg = <0x00000000 0x80000000 0 0x80000000>;
 125                       /* DRAM space - 1, size : 2 GB DRAM */
 126         };
 127
 128         sysclk: sysclk {
 129                 compatible = "fixed-clock";
 130                 #clock-cells = <0>;
 131                 clock-frequency = <100000000>;
 132                 clock-output-names = "sysclk";
 133         };
 134
 135         gic: interrupt-controller@6000000 {
 136                 compatible = "arm,gic-v3";
 137                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 138                         <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
 139                         <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 140                         <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 141                         <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 142                 #interrupt-cells = <3>;
 143                 #address-cells = <2>;
 144                 #size-cells = <2>;
 145                 ranges;
 146                 interrupt-controller;
 147                 interrupts = <1 9 0x4>;
 148
 149                 its: gic-its@6020000 {
 150                         compatible = "arm,gic-v3-its";
 151                         msi-controller;
 152                         reg = <0x0 0x6020000 0 0x20000>;
 153                 };
 154         };
 155
 156         timer {
 157                 compatible = "arm,armv8-timer";
 158                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
 159                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
 160                              <1 11 0x8>, /* Virtual PPI, active-low */
 161                              <1 10 0x8>; /* Hypervisor PPI, active-low */
 162         };
 163
 164         pmu {
 165                 compatible = "arm,armv8-pmuv3";
 166                 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
 167         };
 168
 169         soc {
 170                 compatible = "simple-bus";
 171                 #address-cells = <2>;
 172                 #size-cells = <2>;
 173                 ranges;
 174
 175                 clockgen: clocking@1300000 {
 176                         compatible = "fsl,ls2080a-clockgen";
 177                         reg = <0 0x1300000 0 0xa0000>;
 178                         #clock-cells = <2>;
 179                         clocks = <&sysclk>;
 180                 };
 181
 182                 serial0: serial@21c0500 {
 183                         compatible = "fsl,ns16550", "ns16550a";
 184                         reg = <0x0 0x21c0500 0x0 0x100>;
 185                         clocks = <&clockgen 4 3>;
 186                         interrupts = <0 32 0x4>; /* Level high type */
 187                 };
 188
 189                 serial1: serial@21c0600 {
 190                         compatible = "fsl,ns16550", "ns16550a";
 191                         reg = <0x0 0x21c0600 0x0 0x100>;
 192                         clocks = <&clockgen 4 3>;
 193                         interrupts = <0 32 0x4>; /* Level high type */
 194                 };
 195
 196                 fsl_mc: fsl-mc@80c000000 {
 197                         compatible = "fsl,qoriq-mc";
 198                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 199                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 200                 };
 201
 202                 smmu: iommu@5000000 {
 203                         compatible = "arm,mmu-500";
 204                         reg = <0 0x5000000 0 0x800000>;
 205                         #global-interrupts = <12>;
 206                         interrupts = <0 13 4>, /* global secure fault */
 207                                      <0 14 4>, /* combined secure interrupt */
 208                                      <0 15 4>, /* global non-secure fault */
 209                                      <0 16 4>, /* combined non-secure interrupt */
 210                                 /* performance counter interrupts 0-7 */
 211                                      <0 211 4>, <0 212 4>,
 212                                      <0 213 4>, <0 214 4>,
 213                                      <0 215 4>, <0 216 4>,
 214                                      <0 217 4>, <0 218 4>,
 215                                 /* per context interrupt, 64 interrupts */
 216                                      <0 146 4>, <0 147 4>,
 217                                      <0 148 4>, <0 149 4>,
 218                                      <0 150 4>, <0 151 4>,
 219                                      <0 152 4>, <0 153 4>,
 220                                      <0 154 4>, <0 155 4>,
 221                                      <0 156 4>, <0 157 4>,
 222                                      <0 158 4>, <0 159 4>,
 223                                      <0 160 4>, <0 161 4>,
 224                                      <0 162 4>, <0 163 4>,
 225                                      <0 164 4>, <0 165 4>,
 226                                      <0 166 4>, <0 167 4>,
 227                                      <0 168 4>, <0 169 4>,
 228                                      <0 170 4>, <0 171 4>,
 229                                      <0 172 4>, <0 173 4>,
 230                                      <0 174 4>, <0 175 4>,
 231                                      <0 176 4>, <0 177 4>,
 232                                      <0 178 4>, <0 179 4>,
 233                                      <0 180 4>, <0 181 4>,
 234                                      <0 182 4>, <0 183 4>,
 235                                      <0 184 4>, <0 185 4>,
 236                                      <0 186 4>, <0 187 4>,
 237                                      <0 188 4>, <0 189 4>,
 238                                      <0 190 4>, <0 191 4>,
 239                                      <0 192 4>, <0 193 4>,
 240                                      <0 194 4>, <0 195 4>,
 241                                      <0 196 4>, <0 197 4>,
 242                                      <0 198 4>, <0 199 4>,
 243                                      <0 200 4>, <0 201 4>,
 244                                      <0 202 4>, <0 203 4>,
 245                                      <0 204 4>, <0 205 4>,
 246                                      <0 206 4>, <0 207 4>,
 247                                      <0 208 4>, <0 209 4>;
 248                         mmu-masters = <&fsl_mc 0x300 0>;
 249                 };
 250
 251                 dspi: dspi@2100000 {
 252                         status = "disabled";
 253                         compatible = "fsl,vf610-dspi";
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         reg = <0x0 0x2100000 0x0 0x10000>;
 257                         interrupts = <0 26 0x4>; /* Level high type */
 258                         clocks = <&clockgen 4 3>;
 259                         clock-names = "dspi";
 260                         spi-num-chipselects = <5>;
 261                         bus-num = <0>;
 262                 };
 263
 264                 esdhc: esdhc@2140000 {
 265                         status = "disabled";
 266                         compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
 267                         reg = <0x0 0x2140000 0x0 0x10000>;
 268                         interrupts = <0 28 0x4>; /* Level high type */
 269                         clock-frequency = <0>;  /* Updated by bootloader */
 270                         voltage-ranges = <1800 1800 3300 3300>;
 271                         sdhci,auto-cmd12;
 272                         little-endian;
 273                         bus-width = <4>;
 274                 };
 275
 276                 gpio0: gpio@2300000 {
 277                         compatible = "fsl,qoriq-gpio";
 278                         reg = <0x0 0x2300000 0x0 0x10000>;
 279                         interrupts = <0 36 0x4>; /* Level high type */
 280                         gpio-controller;
 281                         little-endian;
 282                         #gpio-cells = <2>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                 };
 286
 287                 gpio1: gpio@2310000 {
 288                         compatible = "fsl,qoriq-gpio";
 289                         reg = <0x0 0x2310000 0x0 0x10000>;
 290                         interrupts = <0 36 0x4>; /* Level high type */
 291                         gpio-controller;
 292                         little-endian;
 293                         #gpio-cells = <2>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <2>;
 296                 };
 297
 298                 gpio2: gpio@2320000 {
 299                         compatible = "fsl,qoriq-gpio";
 300                         reg = <0x0 0x2320000 0x0 0x10000>;
 301                         interrupts = <0 37 0x4>; /* Level high type */
 302                         gpio-controller;
 303                         little-endian;
 304                         #gpio-cells = <2>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 gpio3: gpio@2330000 {
 310                         compatible = "fsl,qoriq-gpio";
 311                         reg = <0x0 0x2330000 0x0 0x10000>;
 312                         interrupts = <0 37 0x4>; /* Level high type */
 313                         gpio-controller;
 314                         little-endian;
 315                         #gpio-cells = <2>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319
 320                 i2c0: i2c@2000000 {
 321                         status = "disabled";
 322                         compatible = "fsl,vf610-i2c";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         reg = <0x0 0x2000000 0x0 0x10000>;
 326                         interrupts = <0 34 0x4>; /* Level high type */
 327                         clock-names = "i2c";
 328                         clocks = <&clockgen 4 3>;
 329                 };
 330
 331                 i2c1: i2c@2010000 {
 332                         status = "disabled";
 333                         compatible = "fsl,vf610-i2c";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         reg = <0x0 0x2010000 0x0 0x10000>;
 337                         interrupts = <0 34 0x4>; /* Level high type */
 338                         clock-names = "i2c";
 339                         clocks = <&clockgen 4 3>;
 340                 };
 341
 342                 i2c2: i2c@2020000 {
 343                         status = "disabled";
 344                         compatible = "fsl,vf610-i2c";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         reg = <0x0 0x2020000 0x0 0x10000>;
 348                         interrupts = <0 35 0x4>; /* Level high type */
 349                         clock-names = "i2c";
 350                         clocks = <&clockgen 4 3>;
 351                 };
 352
 353                 i2c3: i2c@2030000 {
 354                         status = "disabled";
 355                         compatible = "fsl,vf610-i2c";
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         reg = <0x0 0x2030000 0x0 0x10000>;
 359                         interrupts = <0 35 0x4>; /* Level high type */
 360                         clock-names = "i2c";
 361                         clocks = <&clockgen 4 3>;
 362                 };
 363
 364                 ifc: ifc@2240000 {
 365                         compatible = "fsl,ifc", "simple-bus";
 366                         reg = <0x0 0x2240000 0x0 0x20000>;
 367                         interrupts = <0 21 0x4>; /* Level high type */
 368                         little-endian;
 369                         #address-cells = <2>;
 370                         #size-cells = <1>;
 371
 372                         ranges = <0 0 0x5 0x80000000 0x08000000
 373                                   2 0 0x5 0x30000000 0x00010000
 374                                   3 0 0x5 0x20000000 0x00010000>;
 375                 };
 376
 377                 qspi: quadspi@20c0000 {
 378                         status = "disabled";
 379                         compatible = "fsl,vf610-qspi";
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         reg = <0x0 0x20c0000 0x0 0x10000>,
 383                               <0x0 0x20000000 0x0 0x10000000>;
 384                         reg-names = "QuadSPI", "QuadSPI-memory";
 385                         interrupts = <0 25 0x4>; /* Level high type */
 386                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 387                         clock-names = "qspi_en", "qspi";
 388                 };
 389
 390                 pcie@3400000 {
 391                         compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
 392                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 393                                0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 394                         reg-names = "regs", "config";
 395                         interrupts = <0 108 0x4>; /* Level high type */
 396                         interrupt-names = "intr";
 397                         #address-cells = <3>;
 398                         #size-cells = <2>;
 399                         device_type = "pci";
 400                         num-lanes = <4>;
 401                         bus-range = <0x0 0xff>;
 402                         ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
 403                                   0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 404                         msi-parent = <&its>;
 405                         #interrupt-cells = <1>;
 406                         interrupt-map-mask = <0 0 0 7>;
 407                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
 408                                         <0000 0 0 2 &gic 0 0 0 110 4>,
 409                                         <0000 0 0 3 &gic 0 0 0 111 4>,
 410                                         <0000 0 0 4 &gic 0 0 0 112 4>;
 411                 };
 412
 413                 pcie@3500000 {
 414                         compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
 415                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 416                                0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 417                         reg-names = "regs", "config";
 418                         interrupts = <0 113 0x4>; /* Level high type */
 419                         interrupt-names = "intr";
 420                         #address-cells = <3>;
 421                         #size-cells = <2>;
 422                         device_type = "pci";
 423                         num-lanes = <4>;
 424                         bus-range = <0x0 0xff>;
 425                         ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
 426                                   0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 427                         msi-parent = <&its>;
 428                         #interrupt-cells = <1>;
 429                         interrupt-map-mask = <0 0 0 7>;
 430                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
 431                                         <0000 0 0 2 &gic 0 0 0 115 4>,
 432                                         <0000 0 0 3 &gic 0 0 0 116 4>,
 433                                         <0000 0 0 4 &gic 0 0 0 117 4>;
 434                 };
 435
 436                 pcie@3600000 {
 437                         compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
 438                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 439                                0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 440                         reg-names = "regs", "config";
 441                         interrupts = <0 118 0x4>; /* Level high type */
 442                         interrupt-names = "intr";
 443                         #address-cells = <3>;
 444                         #size-cells = <2>;
 445                         device_type = "pci";
 446                         num-lanes = <8>;
 447                         bus-range = <0x0 0xff>;
 448                         ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
 449                                   0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 450                         msi-parent = <&its>;
 451                         #interrupt-cells = <1>;
 452                         interrupt-map-mask = <0 0 0 7>;
 453                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
 454                                         <0000 0 0 2 &gic 0 0 0 120 4>,
 455                                         <0000 0 0 3 &gic 0 0 0 121 4>,
 456                                         <0000 0 0 4 &gic 0 0 0 122 4>;
 457                 };
 458
 459                 pcie@3700000 {
 460                         compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
 461                         reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 462                                0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 463                         reg-names = "regs", "config";
 464                         interrupts = <0 123 0x4>; /* Level high type */
 465                         interrupt-names = "intr";
 466                         #address-cells = <3>;
 467                         #size-cells = <2>;
 468                         device_type = "pci";
 469                         num-lanes = <4>;
 470                         bus-range = <0x0 0xff>;
 471                         ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
 472                                   0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 473                         msi-parent = <&its>;
 474                         #interrupt-cells = <1>;
 475                         interrupt-map-mask = <0 0 0 7>;
 476                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
 477                                         <0000 0 0 2 &gic 0 0 0 125 4>,
 478                                         <0000 0 0 3 &gic 0 0 0 126 4>,
 479                                         <0000 0 0 4 &gic 0 0 0 127 4>;
 480                 };
 481
 482                 sata0: sata@3200000 {
 483                         status = "disabled";
 484                         compatible = "fsl,ls2080a-ahci";
 485                         reg = <0x0 0x3200000 0x0 0x10000>;
 486                         interrupts = <0 133 0x4>; /* Level high type */
 487                         clocks = <&clockgen 4 3>;
 488                 };
 489
 490                 sata1: sata@3210000 {
 491                         status = "disabled";
 492                         compatible = "fsl,ls2080a-ahci";
 493                         reg = <0x0 0x3210000 0x0 0x10000>;
 494                         interrupts = <0 136 0x4>; /* Level high type */
 495                         clocks = <&clockgen 4 3>;
 496                 };
 497
 498                 usb0: usb3@3100000 {
 499                         status = "disabled";
 500                         compatible = "snps,dwc3";
 501                         reg = <0x0 0x3100000 0x0 0x10000>;
 502                         interrupts = <0 80 0x4>; /* Level high type */
 503                         dr_mode = "host";
 504                 };
 505
 506                 usb1: usb3@3110000 {
 507                         status = "disabled";
 508                         compatible = "snps,dwc3";
 509                         reg = <0x0 0x3110000 0x0 0x10000>;
 510                         interrupts = <0 81 0x4>; /* Level high type */
 511                         dr_mode = "host";
 512                 };
 513
 514                 ccn@4000000 {
 515                         compatible = "arm,ccn-504";
 516                         reg = <0x0 0x04000000 0x0 0x01000000>;
 517                         interrupts = <0 12 4>;
 518                 };
 519         };
 520 };