2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * Copyright (C) 2014-2015, Freescale Semiconductor
6 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls2080a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
64 /* We have 4 clusters having 2 Cortex-A57 cores each */
67 compatible = "arm,cortex-a57";
69 clocks = <&clockgen 1 0>;
74 compatible = "arm,cortex-a57";
76 clocks = <&clockgen 1 0>;
81 compatible = "arm,cortex-a57";
83 clocks = <&clockgen 1 1>;
88 compatible = "arm,cortex-a57";
90 clocks = <&clockgen 1 1>;
95 compatible = "arm,cortex-a57";
97 clocks = <&clockgen 1 2>;
102 compatible = "arm,cortex-a57";
104 clocks = <&clockgen 1 2>;
109 compatible = "arm,cortex-a57";
111 clocks = <&clockgen 1 3>;
116 compatible = "arm,cortex-a57";
118 clocks = <&clockgen 1 3>;
123 device_type = "memory";
124 reg = <0x00000000 0x80000000 0 0x80000000>;
125 /* DRAM space - 1, size : 2 GB DRAM */
129 compatible = "fixed-clock";
131 clock-frequency = <100000000>;
132 clock-output-names = "sysclk";
135 gic: interrupt-controller@6000000 {
136 compatible = "arm,gic-v3";
137 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
138 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
139 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
140 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
141 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
142 #interrupt-cells = <3>;
143 #address-cells = <2>;
146 interrupt-controller;
147 interrupts = <1 9 0x4>;
149 its: gic-its@6020000 {
150 compatible = "arm,gic-v3-its";
152 reg = <0x0 0x6020000 0 0x20000>;
156 rstcr: syscon@1e60000 {
157 compatible = "fsl,ls2080a-rstcr", "syscon";
158 reg = <0x0 0x1e60000 0x0 0x4>;
162 compatible ="syscon-reboot";
169 compatible = "arm,armv8-timer";
170 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
171 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
172 <1 11 0x8>, /* Virtual PPI, active-low */
173 <1 10 0x8>; /* Hypervisor PPI, active-low */
177 compatible = "arm,armv8-pmuv3";
178 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
182 compatible = "simple-bus";
183 #address-cells = <2>;
187 clockgen: clocking@1300000 {
188 compatible = "fsl,ls2080a-clockgen";
189 reg = <0 0x1300000 0 0xa0000>;
194 serial0: serial@21c0500 {
195 compatible = "fsl,ns16550", "ns16550a";
196 reg = <0x0 0x21c0500 0x0 0x100>;
197 clocks = <&clockgen 4 3>;
198 interrupts = <0 32 0x4>; /* Level high type */
201 serial1: serial@21c0600 {
202 compatible = "fsl,ns16550", "ns16550a";
203 reg = <0x0 0x21c0600 0x0 0x100>;
204 clocks = <&clockgen 4 3>;
205 interrupts = <0 32 0x4>; /* Level high type */
208 cluster1_core0_watchdog: wdt@c000000 {
209 compatible = "arm,sp805-wdt", "arm,primecell";
210 reg = <0x0 0xc000000 0x0 0x1000>;
211 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
212 clock-names = "apb_pclk", "wdog_clk";
215 cluster1_core1_watchdog: wdt@c010000 {
216 compatible = "arm,sp805-wdt", "arm,primecell";
217 reg = <0x0 0xc010000 0x0 0x1000>;
218 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
219 clock-names = "apb_pclk", "wdog_clk";
222 cluster2_core0_watchdog: wdt@c100000 {
223 compatible = "arm,sp805-wdt", "arm,primecell";
224 reg = <0x0 0xc100000 0x0 0x1000>;
225 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
226 clock-names = "apb_pclk", "wdog_clk";
229 cluster2_core1_watchdog: wdt@c110000 {
230 compatible = "arm,sp805-wdt", "arm,primecell";
231 reg = <0x0 0xc110000 0x0 0x1000>;
232 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
233 clock-names = "apb_pclk", "wdog_clk";
236 cluster3_core0_watchdog: wdt@c200000 {
237 compatible = "arm,sp805-wdt", "arm,primecell";
238 reg = <0x0 0xc200000 0x0 0x1000>;
239 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
240 clock-names = "apb_pclk", "wdog_clk";
243 cluster3_core1_watchdog: wdt@c210000 {
244 compatible = "arm,sp805-wdt", "arm,primecell";
245 reg = <0x0 0xc210000 0x0 0x1000>;
246 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
247 clock-names = "apb_pclk", "wdog_clk";
250 cluster4_core0_watchdog: wdt@c300000 {
251 compatible = "arm,sp805-wdt", "arm,primecell";
252 reg = <0x0 0xc300000 0x0 0x1000>;
253 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
254 clock-names = "apb_pclk", "wdog_clk";
257 cluster4_core1_watchdog: wdt@c310000 {
258 compatible = "arm,sp805-wdt", "arm,primecell";
259 reg = <0x0 0xc310000 0x0 0x1000>;
260 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
261 clock-names = "apb_pclk", "wdog_clk";
264 fsl_mc: fsl-mc@80c000000 {
265 compatible = "fsl,qoriq-mc";
266 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
267 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
269 #address-cells = <3>;
273 * Region type 0x0 - MC portals
274 * Region type 0x1 - QBMAN portals
276 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
277 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
280 * Define the maximum number of MACs present on the SoC.
283 #address-cells = <1>;
287 compatible = "fsl,qoriq-mc-dpmac";
292 compatible = "fsl,qoriq-mc-dpmac";
297 compatible = "fsl,qoriq-mc-dpmac";
302 compatible = "fsl,qoriq-mc-dpmac";
307 compatible = "fsl,qoriq-mc-dpmac";
312 compatible = "fsl,qoriq-mc-dpmac";
317 compatible = "fsl,qoriq-mc-dpmac";
322 compatible = "fsl,qoriq-mc-dpmac";
327 compatible = "fsl,qoriq-mc-dpmac";
332 compatible = "fsl,qoriq-mc-dpmac";
337 compatible = "fsl,qoriq-mc-dpmac";
342 compatible = "fsl,qoriq-mc-dpmac";
347 compatible = "fsl,qoriq-mc-dpmac";
352 compatible = "fsl,qoriq-mc-dpmac";
357 compatible = "fsl,qoriq-mc-dpmac";
362 compatible = "fsl,qoriq-mc-dpmac";
368 smmu: iommu@5000000 {
369 compatible = "arm,mmu-500";
370 reg = <0 0x5000000 0 0x800000>;
371 #global-interrupts = <12>;
372 interrupts = <0 13 4>, /* global secure fault */
373 <0 14 4>, /* combined secure interrupt */
374 <0 15 4>, /* global non-secure fault */
375 <0 16 4>, /* combined non-secure interrupt */
376 /* performance counter interrupts 0-7 */
377 <0 211 4>, <0 212 4>,
378 <0 213 4>, <0 214 4>,
379 <0 215 4>, <0 216 4>,
380 <0 217 4>, <0 218 4>,
381 /* per context interrupt, 64 interrupts */
382 <0 146 4>, <0 147 4>,
383 <0 148 4>, <0 149 4>,
384 <0 150 4>, <0 151 4>,
385 <0 152 4>, <0 153 4>,
386 <0 154 4>, <0 155 4>,
387 <0 156 4>, <0 157 4>,
388 <0 158 4>, <0 159 4>,
389 <0 160 4>, <0 161 4>,
390 <0 162 4>, <0 163 4>,
391 <0 164 4>, <0 165 4>,
392 <0 166 4>, <0 167 4>,
393 <0 168 4>, <0 169 4>,
394 <0 170 4>, <0 171 4>,
395 <0 172 4>, <0 173 4>,
396 <0 174 4>, <0 175 4>,
397 <0 176 4>, <0 177 4>,
398 <0 178 4>, <0 179 4>,
399 <0 180 4>, <0 181 4>,
400 <0 182 4>, <0 183 4>,
401 <0 184 4>, <0 185 4>,
402 <0 186 4>, <0 187 4>,
403 <0 188 4>, <0 189 4>,
404 <0 190 4>, <0 191 4>,
405 <0 192 4>, <0 193 4>,
406 <0 194 4>, <0 195 4>,
407 <0 196 4>, <0 197 4>,
408 <0 198 4>, <0 199 4>,
409 <0 200 4>, <0 201 4>,
410 <0 202 4>, <0 203 4>,
411 <0 204 4>, <0 205 4>,
412 <0 206 4>, <0 207 4>,
413 <0 208 4>, <0 209 4>;
414 mmu-masters = <&fsl_mc 0x300 0>;
419 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
420 #address-cells = <1>;
422 reg = <0x0 0x2100000 0x0 0x10000>;
423 interrupts = <0 26 0x4>; /* Level high type */
424 clocks = <&clockgen 4 3>;
425 clock-names = "dspi";
426 spi-num-chipselects = <5>;
430 esdhc: esdhc@2140000 {
432 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
433 reg = <0x0 0x2140000 0x0 0x10000>;
434 interrupts = <0 28 0x4>; /* Level high type */
435 clock-frequency = <0>; /* Updated by bootloader */
436 voltage-ranges = <1800 1800 3300 3300>;
442 gpio0: gpio@2300000 {
443 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
444 reg = <0x0 0x2300000 0x0 0x10000>;
445 interrupts = <0 36 0x4>; /* Level high type */
449 interrupt-controller;
450 #interrupt-cells = <2>;
453 gpio1: gpio@2310000 {
454 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
455 reg = <0x0 0x2310000 0x0 0x10000>;
456 interrupts = <0 36 0x4>; /* Level high type */
460 interrupt-controller;
461 #interrupt-cells = <2>;
464 gpio2: gpio@2320000 {
465 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
466 reg = <0x0 0x2320000 0x0 0x10000>;
467 interrupts = <0 37 0x4>; /* Level high type */
471 interrupt-controller;
472 #interrupt-cells = <2>;
475 gpio3: gpio@2330000 {
476 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
477 reg = <0x0 0x2330000 0x0 0x10000>;
478 interrupts = <0 37 0x4>; /* Level high type */
482 interrupt-controller;
483 #interrupt-cells = <2>;
488 compatible = "fsl,vf610-i2c";
489 #address-cells = <1>;
491 reg = <0x0 0x2000000 0x0 0x10000>;
492 interrupts = <0 34 0x4>; /* Level high type */
494 clocks = <&clockgen 4 3>;
499 compatible = "fsl,vf610-i2c";
500 #address-cells = <1>;
502 reg = <0x0 0x2010000 0x0 0x10000>;
503 interrupts = <0 34 0x4>; /* Level high type */
505 clocks = <&clockgen 4 3>;
510 compatible = "fsl,vf610-i2c";
511 #address-cells = <1>;
513 reg = <0x0 0x2020000 0x0 0x10000>;
514 interrupts = <0 35 0x4>; /* Level high type */
516 clocks = <&clockgen 4 3>;
521 compatible = "fsl,vf610-i2c";
522 #address-cells = <1>;
524 reg = <0x0 0x2030000 0x0 0x10000>;
525 interrupts = <0 35 0x4>; /* Level high type */
527 clocks = <&clockgen 4 3>;
531 compatible = "fsl,ifc", "simple-bus";
532 reg = <0x0 0x2240000 0x0 0x20000>;
533 interrupts = <0 21 0x4>; /* Level high type */
535 #address-cells = <2>;
538 ranges = <0 0 0x5 0x80000000 0x08000000
539 2 0 0x5 0x30000000 0x00010000
540 3 0 0x5 0x20000000 0x00010000>;
543 qspi: quadspi@20c0000 {
545 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
546 #address-cells = <1>;
548 reg = <0x0 0x20c0000 0x0 0x10000>,
549 <0x0 0x20000000 0x0 0x10000000>;
550 reg-names = "QuadSPI", "QuadSPI-memory";
551 interrupts = <0 25 0x4>; /* Level high type */
552 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
553 clock-names = "qspi_en", "qspi";
557 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
559 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
560 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
561 reg-names = "regs", "config";
562 interrupts = <0 108 0x4>; /* Level high type */
563 interrupt-names = "intr";
564 #address-cells = <3>;
568 bus-range = <0x0 0xff>;
569 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
570 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
572 #interrupt-cells = <1>;
573 interrupt-map-mask = <0 0 0 7>;
574 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
575 <0000 0 0 2 &gic 0 0 0 110 4>,
576 <0000 0 0 3 &gic 0 0 0 111 4>,
577 <0000 0 0 4 &gic 0 0 0 112 4>;
581 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
583 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
584 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
585 reg-names = "regs", "config";
586 interrupts = <0 113 0x4>; /* Level high type */
587 interrupt-names = "intr";
588 #address-cells = <3>;
592 bus-range = <0x0 0xff>;
593 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
594 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
596 #interrupt-cells = <1>;
597 interrupt-map-mask = <0 0 0 7>;
598 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
599 <0000 0 0 2 &gic 0 0 0 115 4>,
600 <0000 0 0 3 &gic 0 0 0 116 4>,
601 <0000 0 0 4 &gic 0 0 0 117 4>;
605 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
607 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
608 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
609 reg-names = "regs", "config";
610 interrupts = <0 118 0x4>; /* Level high type */
611 interrupt-names = "intr";
612 #address-cells = <3>;
616 bus-range = <0x0 0xff>;
617 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
618 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
620 #interrupt-cells = <1>;
621 interrupt-map-mask = <0 0 0 7>;
622 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
623 <0000 0 0 2 &gic 0 0 0 120 4>,
624 <0000 0 0 3 &gic 0 0 0 121 4>,
625 <0000 0 0 4 &gic 0 0 0 122 4>;
629 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
631 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
632 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
633 reg-names = "regs", "config";
634 interrupts = <0 123 0x4>; /* Level high type */
635 interrupt-names = "intr";
636 #address-cells = <3>;
640 bus-range = <0x0 0xff>;
641 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
642 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
644 #interrupt-cells = <1>;
645 interrupt-map-mask = <0 0 0 7>;
646 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
647 <0000 0 0 2 &gic 0 0 0 125 4>,
648 <0000 0 0 3 &gic 0 0 0 126 4>,
649 <0000 0 0 4 &gic 0 0 0 127 4>;
652 sata0: sata@3200000 {
654 compatible = "fsl,ls2080a-ahci";
655 reg = <0x0 0x3200000 0x0 0x10000>;
656 interrupts = <0 133 0x4>; /* Level high type */
657 clocks = <&clockgen 4 3>;
660 sata1: sata@3210000 {
662 compatible = "fsl,ls2080a-ahci";
663 reg = <0x0 0x3210000 0x0 0x10000>;
664 interrupts = <0 136 0x4>; /* Level high type */
665 clocks = <&clockgen 4 3>;
670 compatible = "snps,dwc3";
671 reg = <0x0 0x3100000 0x0 0x10000>;
672 interrupts = <0 80 0x4>; /* Level high type */
674 snps,quirk-frame-length-adjustment = <0x20>;
679 compatible = "snps,dwc3";
680 reg = <0x0 0x3110000 0x0 0x10000>;
681 interrupts = <0 81 0x4>; /* Level high type */
683 snps,quirk-frame-length-adjustment = <0x20>;
687 compatible = "arm,ccn-504";
688 reg = <0x0 0x04000000 0x0 0x01000000>;
689 interrupts = <0 12 4>;