2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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47 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "psci";
72 compatible = "arm,psci-0.2";
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13
79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
89 compatible = "simple-bus";
97 compatible = "simple-bus";
98 /* 32M internal register @ 0xd000_0000 */
99 ranges = <0x0 0x0 0xd0000000 0x2000000>;
101 uart0: serial@12000 {
102 compatible = "marvell,armada-3700-uart";
103 reg = <0x12000 0x400>;
104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
108 nb_perih_clk: nb-periph-clk@13000{
109 compatible = "marvell,armada-3700-periph-clock-nb";
110 reg = <0x13000 0x100>;
111 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
112 <&tbg 3>, <&xtalclk>;
116 sb_perih_clk: sb-periph-clk@18000{
117 compatible = "marvell,armada-3700-periph-clock-sb";
118 reg = <0x18000 0x100>;
119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
120 <&tbg 3>, <&xtalclk>;
125 compatible = "marvell,armada-3700-tbg-clock";
126 reg = <0x13200 0x100>;
132 compatible = "marvell,mvebu-gpio-3700",
133 "syscon", "simple-mfd";
134 reg = <0x13800 0x500>;
137 compatible = "marvell,armada-3700-xtal-clock";
138 clock-output-names = "xtal";
144 compatible = "marvell,armada3700-xhci",
146 reg = <0x58000 0x4000>;
147 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
152 compatible = "marvell,armada-3700-xor";
157 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
160 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
165 compatible = "marvell,armada-3700-ahci";
166 reg = <0xe0000 0x2000>;
167 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
171 gic: interrupt-controller@1d00000 {
172 compatible = "arm,gic-v3";
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 reg = <0x1d00000 0x10000>, /* GICD */
176 <0x1d40000 0x40000>; /* GICR */