2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
44 * Device Tree file for Marvell Armada AP806.
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 model = "Marvell Armada AP806";
53 compatible = "marvell,armada-ap806";
63 compatible = "arm,psci-0.2";
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
77 compatible = "simple-bus";
78 ranges = <0x0 0x0 0xf0000000 0x1000000>;
80 gic: interrupt-controller@210000 {
81 compatible = "arm,gic-400";
82 #interrupt-cells = <3>;
87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
88 reg = <0x210000 0x10000>,
93 gic_v2m0: v2m@280000 {
94 compatible = "arm,gic-v2m-frame";
96 reg = <0x280000 0x1000>;
97 arm,msi-base-spi = <160>;
98 arm,msi-num-spis = <32>;
100 gic_v2m1: v2m@290000 {
101 compatible = "arm,gic-v2m-frame";
103 reg = <0x290000 0x1000>;
104 arm,msi-base-spi = <192>;
105 arm,msi-num-spis = <32>;
107 gic_v2m2: v2m@2a0000 {
108 compatible = "arm,gic-v2m-frame";
110 reg = <0x2a0000 0x1000>;
111 arm,msi-base-spi = <224>;
112 arm,msi-num-spis = <32>;
114 gic_v2m3: v2m@2b0000 {
115 compatible = "arm,gic-v2m-frame";
117 reg = <0x2b0000 0x1000>;
118 arm,msi-base-spi = <256>;
119 arm,msi-num-spis = <32>;
124 compatible = "arm,armv8-timer";
125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
132 compatible = "arm,cortex-a72-pmu";
133 interrupt-parent = <&pic>;
138 compatible = "marvell,odmi-controller";
139 interrupt-controller;
141 marvell,odmi-frames = <4>;
142 reg = <0x300000 0x4000>,
146 marvell,spi-base = <128>, <136>, <144>, <152>;
149 pic: interrupt-controller@3f0100 {
150 compatible = "marvell,armada-8k-pic";
151 reg = <0x3f0100 0x10>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
158 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
159 reg = <0x400000 0x1000>,
161 msi-parent = <&gic_v2m0>;
166 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
167 reg = <0x420000 0x1000>,
169 msi-parent = <&gic_v2m0>;
174 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
175 reg = <0x440000 0x1000>,
177 msi-parent = <&gic_v2m0>;
182 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
183 reg = <0x460000 0x1000>,
185 msi-parent = <&gic_v2m0>;
190 compatible = "marvell,armada-380-spi";
191 reg = <0x510600 0x50>;
192 #address-cells = <1>;
195 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ap_syscon 3>;
201 compatible = "marvell,mv78230-i2c";
202 reg = <0x511000 0x20>;
203 #address-cells = <1>;
205 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&ap_syscon 3>;
211 uart0: serial@512000 {
212 compatible = "snps,dw-apb-uart";
213 reg = <0x512000 0x100>;
215 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ap_syscon 3>;
221 uart1: serial@512100 {
222 compatible = "snps,dw-apb-uart";
223 reg = <0x512100 0x100>;
225 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ap_syscon 3>;
232 ap_syscon: system-controller@6f4000 {
233 compatible = "marvell,ap806-system-controller",
236 clock-output-names = "ap-cpu-cluster-0",
238 "ap-fixed", "ap-mss";
239 reg = <0x6f4000 0x1000>;