2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
51 compatible = "rockchip,rk3368";
52 interrupt-parent = <&gic>;
75 #address-cells = <0x2>;
111 entry-method = "psci";
113 cpu_sleep: cpu-sleep-0 {
114 compatible = "arm,idle-state";
115 arm,psci-suspend-param = <0x1010000>;
116 entry-latency-us = <0x3fffffff>;
117 exit-latency-us = <0x40000000>;
118 min-residency-us = <0xffffffff>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 cpu-idle-states = <&cpu_sleep>;
127 enable-method = "psci";
129 #cooling-cells = <2>; /* min followed by max */
134 compatible = "arm,cortex-a53", "arm,armv8";
136 cpu-idle-states = <&cpu_sleep>;
137 enable-method = "psci";
142 compatible = "arm,cortex-a53", "arm,armv8";
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
150 compatible = "arm,cortex-a53", "arm,armv8";
152 cpu-idle-states = <&cpu_sleep>;
153 enable-method = "psci";
158 compatible = "arm,cortex-a53", "arm,armv8";
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
163 #cooling-cells = <2>; /* min followed by max */
168 compatible = "arm,cortex-a53", "arm,armv8";
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
176 compatible = "arm,cortex-a53", "arm,armv8";
178 cpu-idle-states = <&cpu_sleep>;
179 enable-method = "psci";
184 compatible = "arm,cortex-a53", "arm,armv8";
186 cpu-idle-states = <&cpu_sleep>;
187 enable-method = "psci";
192 compatible = "arm,armv8-pmuv3";
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
203 <&cpu_b2>, <&cpu_b3>;
207 compatible = "arm,psci-0.2";
212 compatible = "arm,armv8-timer";
213 interrupts = <GIC_PPI 13
214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
224 compatible = "fixed-clock";
225 clock-frequency = <24000000>;
226 clock-output-names = "xin24m";
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
232 reg = <0x0 0xff0c0000 0x0 0x4000>;
233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x0 0xff0d0000 0x0 0x4000>;
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
254 emmc: dwmmc@ff0f0000 {
255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x0 0xff0f0000 0x0 0x4000>;
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
266 saradc: saradc@ff100000 {
267 compatible = "rockchip,saradc";
268 reg = <0x0 0xff100000 0x0 0x100>;
269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
270 #io-channel-cells = <1>;
271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
272 clock-names = "saradc", "apb_pclk";
273 resets = <&cru SRST_SARADC>;
274 reset-names = "saradc-apb";
279 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
280 reg = <0x0 0xff110000 0x0 0x1000>;
281 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
282 clock-names = "spiclk", "apb_pclk";
283 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
286 #address-cells = <1>;
292 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
293 reg = <0x0 0xff120000 0x0 0x1000>;
294 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
295 clock-names = "spiclk", "apb_pclk";
296 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
299 #address-cells = <1>;
305 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
306 reg = <0x0 0xff130000 0x0 0x1000>;
307 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
308 clock-names = "spiclk", "apb_pclk";
309 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
312 #address-cells = <1>;
318 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
319 reg = <0x0 0xff140000 0x0 0x1000>;
320 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
321 #address-cells = <1>;
324 clocks = <&cru PCLK_I2C1>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c1_xfer>;
331 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
332 reg = <0x0 0xff150000 0x0 0x1000>;
333 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
337 clocks = <&cru PCLK_I2C3>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c3_xfer>;
344 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
345 reg = <0x0 0xff160000 0x0 0x1000>;
346 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
350 clocks = <&cru PCLK_I2C4>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c4_xfer>;
357 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
358 reg = <0x0 0xff170000 0x0 0x1000>;
359 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
363 clocks = <&cru PCLK_I2C5>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c5_xfer>;
369 uart0: serial@ff180000 {
370 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
371 reg = <0x0 0xff180000 0x0 0x100>;
372 clock-frequency = <24000000>;
373 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
374 clock-names = "baudclk", "apb_pclk";
375 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
381 uart1: serial@ff190000 {
382 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
383 reg = <0x0 0xff190000 0x0 0x100>;
384 clock-frequency = <24000000>;
385 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
386 clock-names = "baudclk", "apb_pclk";
387 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
393 uart3: serial@ff1b0000 {
394 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
395 reg = <0x0 0xff1b0000 0x0 0x100>;
396 clock-frequency = <24000000>;
397 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
398 clock-names = "baudclk", "apb_pclk";
399 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
405 uart4: serial@ff1c0000 {
406 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
407 reg = <0x0 0xff1c0000 0x0 0x100>;
408 clock-frequency = <24000000>;
409 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
410 clock-names = "baudclk", "apb_pclk";
411 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
419 polling-delay-passive = <100>; /* milliseconds */
420 polling-delay = <5000>; /* milliseconds */
422 thermal-sensors = <&tsadc 0>;
425 cpu_alert0: cpu_alert0 {
426 temperature = <75000>; /* millicelsius */
427 hysteresis = <2000>; /* millicelsius */
430 cpu_alert1: cpu_alert1 {
431 temperature = <80000>; /* millicelsius */
432 hysteresis = <2000>; /* millicelsius */
436 temperature = <95000>; /* millicelsius */
437 hysteresis = <2000>; /* millicelsius */
444 trip = <&cpu_alert0>;
446 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
449 trip = <&cpu_alert1>;
451 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
457 polling-delay-passive = <100>; /* milliseconds */
458 polling-delay = <5000>; /* milliseconds */
460 thermal-sensors = <&tsadc 1>;
463 gpu_alert0: gpu_alert0 {
464 temperature = <80000>; /* millicelsius */
465 hysteresis = <2000>; /* millicelsius */
469 temperature = <115000>; /* millicelsius */
470 hysteresis = <2000>; /* millicelsius */
477 trip = <&gpu_alert0>;
479 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
485 tsadc: tsadc@ff280000 {
486 compatible = "rockchip,rk3368-tsadc";
487 reg = <0x0 0xff280000 0x0 0x100>;
488 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
490 clock-names = "tsadc", "apb_pclk";
491 resets = <&cru SRST_TSADC>;
492 reset-names = "tsadc-apb";
493 pinctrl-names = "init", "default", "sleep";
494 pinctrl-0 = <&otp_gpio>;
495 pinctrl-1 = <&otp_out>;
496 pinctrl-2 = <&otp_gpio>;
497 #thermal-sensor-cells = <1>;
498 rockchip,hw-tshut-temp = <95000>;
502 gmac: ethernet@ff290000 {
503 compatible = "rockchip,rk3368-gmac";
504 reg = <0x0 0xff290000 0x0 0x10000>;
505 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
506 interrupt-names = "macirq";
507 rockchip,grf = <&grf>;
508 clocks = <&cru SCLK_MAC>,
509 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
510 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
511 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
512 clock-names = "stmmaceth",
513 "mac_clk_rx", "mac_clk_tx",
514 "clk_mac_ref", "clk_mac_refout",
515 "aclk_mac", "pclk_mac";
519 usb_host0_ehci: usb@ff500000 {
520 compatible = "generic-ehci";
521 reg = <0x0 0xff500000 0x0 0x100>;
522 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cru HCLK_HOST0>;
524 clock-names = "usbhost";
528 usb_otg: usb@ff580000 {
529 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
531 reg = <0x0 0xff580000 0x0 0x40000>;
532 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru HCLK_OTG0>;
536 g-np-tx-fifo-size = <16>;
537 g-rx-fifo-size = <275>;
538 g-tx-fifo-size = <256 128 128 64 64 32>;
544 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
545 reg = <0x0 0xff650000 0x0 0x1000>;
546 clocks = <&cru PCLK_I2C0>;
548 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c0_xfer>;
551 #address-cells = <1>;
557 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
558 reg = <0x0 0xff660000 0x0 0x1000>;
559 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
563 clocks = <&cru PCLK_I2C2>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>;
570 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
571 reg = <0x0 0xff680000 0x0 0x10>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pwm0_pin>;
575 clocks = <&cru PCLK_PWM1>;
581 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
582 reg = <0x0 0xff680010 0x0 0x10>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pwm1_pin>;
586 clocks = <&cru PCLK_PWM1>;
592 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
593 reg = <0x0 0xff680020 0x0 0x10>;
595 clocks = <&cru PCLK_PWM1>;
601 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
602 reg = <0x0 0xff680030 0x0 0x10>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pwm3_pin>;
606 clocks = <&cru PCLK_PWM1>;
611 uart2: serial@ff690000 {
612 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
613 reg = <0x0 0xff690000 0x0 0x100>;
614 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
615 clock-names = "baudclk", "apb_pclk";
616 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart2_xfer>;
624 mbox: mbox@ff6b0000 {
625 compatible = "rockchip,rk3368-mailbox";
626 reg = <0x0 0xff6b0000 0x0 0x1000>;
627 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cru PCLK_MAILBOX>;
632 clock-names = "pclk_mailbox";
636 pmugrf: syscon@ff738000 {
637 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
638 reg = <0x0 0xff738000 0x0 0x1000>;
640 pmu_io_domains: io-domains {
641 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
646 cru: clock-controller@ff760000 {
647 compatible = "rockchip,rk3368-cru";
648 reg = <0x0 0xff760000 0x0 0x1000>;
649 rockchip,grf = <&grf>;
654 grf: syscon@ff770000 {
655 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
656 reg = <0x0 0xff770000 0x0 0x1000>;
658 io_domains: io-domains {
659 compatible = "rockchip,rk3368-io-voltage-domain";
664 wdt: watchdog@ff800000 {
665 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
666 reg = <0x0 0xff800000 0x0 0x100>;
667 clocks = <&cru PCLK_WDT>;
668 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
673 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
674 reg = <0x0 0xff810000 0x0 0x20>;
675 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
678 gic: interrupt-controller@ffb71000 {
679 compatible = "arm,gic-400";
680 interrupt-controller;
681 #interrupt-cells = <3>;
682 #address-cells = <0>;
684 reg = <0x0 0xffb71000 0x0 0x1000>,
685 <0x0 0xffb72000 0x0 0x2000>,
686 <0x0 0xffb74000 0x0 0x2000>,
687 <0x0 0xffb76000 0x0 0x2000>;
688 interrupts = <GIC_PPI 9
689 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
693 compatible = "rockchip,rk3368-pinctrl";
694 rockchip,grf = <&grf>;
695 rockchip,pmu = <&pmugrf>;
696 #address-cells = <0x2>;
700 gpio0: gpio0@ff750000 {
701 compatible = "rockchip,gpio-bank";
702 reg = <0x0 0xff750000 0x0 0x100>;
703 clocks = <&cru PCLK_GPIO0>;
704 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-controller;
710 #interrupt-cells = <0x2>;
713 gpio1: gpio1@ff780000 {
714 compatible = "rockchip,gpio-bank";
715 reg = <0x0 0xff780000 0x0 0x100>;
716 clocks = <&cru PCLK_GPIO1>;
717 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
722 interrupt-controller;
723 #interrupt-cells = <0x2>;
726 gpio2: gpio2@ff790000 {
727 compatible = "rockchip,gpio-bank";
728 reg = <0x0 0xff790000 0x0 0x100>;
729 clocks = <&cru PCLK_GPIO2>;
730 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
735 interrupt-controller;
736 #interrupt-cells = <0x2>;
739 gpio3: gpio3@ff7a0000 {
740 compatible = "rockchip,gpio-bank";
741 reg = <0x0 0xff7a0000 0x0 0x100>;
742 clocks = <&cru PCLK_GPIO3>;
743 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-controller;
749 #interrupt-cells = <0x2>;
752 pcfg_pull_up: pcfg-pull-up {
756 pcfg_pull_down: pcfg-pull-down {
760 pcfg_pull_none: pcfg-pull-none {
764 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
766 drive-strength = <12>;
771 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
775 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
779 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
782 emmc_bus1: emmc-bus1 {
783 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
786 emmc_bus4: emmc-bus4 {
787 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
788 <1 19 RK_FUNC_2 &pcfg_pull_up>,
789 <1 20 RK_FUNC_2 &pcfg_pull_up>,
790 <1 21 RK_FUNC_2 &pcfg_pull_up>;
793 emmc_bus8: emmc-bus8 {
794 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
795 <1 19 RK_FUNC_2 &pcfg_pull_up>,
796 <1 20 RK_FUNC_2 &pcfg_pull_up>,
797 <1 21 RK_FUNC_2 &pcfg_pull_up>,
798 <1 22 RK_FUNC_2 &pcfg_pull_up>,
799 <1 23 RK_FUNC_2 &pcfg_pull_up>,
800 <1 24 RK_FUNC_2 &pcfg_pull_up>,
801 <1 25 RK_FUNC_2 &pcfg_pull_up>;
806 rgmii_pins: rgmii-pins {
807 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
808 <3 24 RK_FUNC_1 &pcfg_pull_none>,
809 <3 19 RK_FUNC_1 &pcfg_pull_none>,
810 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
811 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
812 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
813 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
814 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
815 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
816 <3 15 RK_FUNC_1 &pcfg_pull_none>,
817 <3 16 RK_FUNC_1 &pcfg_pull_none>,
818 <3 17 RK_FUNC_1 &pcfg_pull_none>,
819 <3 18 RK_FUNC_1 &pcfg_pull_none>,
820 <3 25 RK_FUNC_1 &pcfg_pull_none>,
821 <3 20 RK_FUNC_1 &pcfg_pull_none>;
824 rmii_pins: rmii-pins {
825 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
826 <3 24 RK_FUNC_1 &pcfg_pull_none>,
827 <3 19 RK_FUNC_1 &pcfg_pull_none>,
828 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
829 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
830 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
831 <3 15 RK_FUNC_1 &pcfg_pull_none>,
832 <3 16 RK_FUNC_1 &pcfg_pull_none>,
833 <3 20 RK_FUNC_1 &pcfg_pull_none>,
834 <3 21 RK_FUNC_1 &pcfg_pull_none>;
839 i2c0_xfer: i2c0-xfer {
840 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
841 <0 7 RK_FUNC_1 &pcfg_pull_none>;
846 i2c1_xfer: i2c1-xfer {
847 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
848 <2 22 RK_FUNC_1 &pcfg_pull_none>;
853 i2c2_xfer: i2c2-xfer {
854 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
855 <3 31 RK_FUNC_2 &pcfg_pull_none>;
860 i2c3_xfer: i2c3-xfer {
861 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
862 <1 17 RK_FUNC_1 &pcfg_pull_none>;
867 i2c4_xfer: i2c4-xfer {
868 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
869 <3 25 RK_FUNC_2 &pcfg_pull_none>;
874 i2c5_xfer: i2c5-xfer {
875 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
876 <3 27 RK_FUNC_2 &pcfg_pull_none>;
882 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
888 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
894 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
899 sdio0_bus1: sdio0-bus1 {
900 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
903 sdio0_bus4: sdio0-bus4 {
904 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
905 <2 29 RK_FUNC_1 &pcfg_pull_up>,
906 <2 30 RK_FUNC_1 &pcfg_pull_up>,
907 <2 31 RK_FUNC_1 &pcfg_pull_up>;
910 sdio0_cmd: sdio0-cmd {
911 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
914 sdio0_clk: sdio0-clk {
915 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
919 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
923 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
926 sdio0_pwr: sdio0-pwr {
927 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
930 sdio0_bkpwr: sdio0-bkpwr {
931 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
934 sdio0_int: sdio0-int {
935 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
940 sdmmc_clk: sdmmc-clk {
941 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
944 sdmmc_cmd: sdmmc-cmd {
945 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
949 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
952 sdmmc_bus1: sdmmc-bus1 {
953 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
956 sdmmc_bus4: sdmmc-bus4 {
957 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
958 <2 6 RK_FUNC_1 &pcfg_pull_up>,
959 <2 7 RK_FUNC_1 &pcfg_pull_up>,
960 <2 8 RK_FUNC_1 &pcfg_pull_up>;
966 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
969 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
972 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
975 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
978 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
984 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
987 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
990 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
993 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
996 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1001 spi2_clk: spi2-clk {
1002 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1004 spi2_cs0: spi2-cs0 {
1005 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1008 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1011 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1016 otp_gpio: otp-gpio {
1017 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1021 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1026 uart0_xfer: uart0-xfer {
1027 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1028 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1031 uart0_cts: uart0-cts {
1032 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1035 uart0_rts: uart0-rts {
1036 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1041 uart1_xfer: uart1-xfer {
1042 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1043 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1046 uart1_cts: uart1-cts {
1047 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1050 uart1_rts: uart1-rts {
1051 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1056 uart2_xfer: uart2-xfer {
1057 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1058 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1060 /* no rts / cts for uart2 */
1064 uart3_xfer: uart3-xfer {
1065 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1066 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1069 uart3_cts: uart3-cts {
1070 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1073 uart3_rts: uart3-rts {
1074 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1079 uart4_xfer: uart4-xfer {
1080 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1081 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1084 uart4_cts: uart4-cts {
1085 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1088 uart4_rts: uart4-rts {
1089 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;