2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
76 #address-cells = <0x2>;
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
130 #cooling-cells = <2>; /* min followed by max */
135 compatible = "arm,cortex-a53", "arm,armv8";
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
143 compatible = "arm,cortex-a53", "arm,armv8";
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
159 compatible = "arm,cortex-a53", "arm,armv8";
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
169 compatible = "arm,cortex-a53", "arm,armv8";
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
185 compatible = "arm,cortex-a53", "arm,armv8";
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
193 compatible = "arm,armv8-pmuv3";
194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
204 <&cpu_b2>, <&cpu_b3>;
208 compatible = "arm,psci-0.2";
213 compatible = "arm,armv8-timer";
214 interrupts = <GIC_PPI 13
215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
233 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 clock-freq-min-max = <400000 150000000>;
235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
238 fifo-depth = <0x100>;
239 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x0 0xff0d0000 0x0 0x4000>;
246 clock-freq-min-max = <400000 150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x0 0xff0f0000 0x0 0x4000>;
258 clock-freq-min-max = <400000 150000000>;
259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
262 fifo-depth = <0x100>;
263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
267 saradc: saradc@ff100000 {
268 compatible = "rockchip,saradc";
269 reg = <0x0 0xff100000 0x0 0x100>;
270 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";
278 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
279 reg = <0x0 0xff110000 0x0 0x1000>;
280 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
281 clock-names = "spiclk", "apb_pclk";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 #address-cells = <1>;
291 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
292 reg = <0x0 0xff120000 0x0 0x1000>;
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
298 #address-cells = <1>;
304 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
305 reg = <0x0 0xff130000 0x0 0x1000>;
306 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
307 clock-names = "spiclk", "apb_pclk";
308 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
311 #address-cells = <1>;
317 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
318 reg = <0x0 0xff140000 0x0 0x1000>;
319 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
323 clocks = <&cru PCLK_I2C2>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_xfer>;
330 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
331 reg = <0x0 0xff150000 0x0 0x1000>;
332 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
336 clocks = <&cru PCLK_I2C3>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c3_xfer>;
343 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
344 reg = <0x0 0xff160000 0x0 0x1000>;
345 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
349 clocks = <&cru PCLK_I2C4>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c4_xfer>;
356 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
357 reg = <0x0 0xff170000 0x0 0x1000>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
362 clocks = <&cru PCLK_I2C5>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c5_xfer>;
368 uart0: serial@ff180000 {
369 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
370 reg = <0x0 0xff180000 0x0 0x100>;
371 clock-frequency = <24000000>;
372 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
373 clock-names = "baudclk", "apb_pclk";
374 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
380 uart1: serial@ff190000 {
381 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
382 reg = <0x0 0xff190000 0x0 0x100>;
383 clock-frequency = <24000000>;
384 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
385 clock-names = "baudclk", "apb_pclk";
386 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
392 uart3: serial@ff1b0000 {
393 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
394 reg = <0x0 0xff1b0000 0x0 0x100>;
395 clock-frequency = <24000000>;
396 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
397 clock-names = "baudclk", "apb_pclk";
398 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
404 uart4: serial@ff1c0000 {
405 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
406 reg = <0x0 0xff1c0000 0x0 0x100>;
407 clock-frequency = <24000000>;
408 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
409 clock-names = "baudclk", "apb_pclk";
410 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
418 polling-delay-passive = <100>; /* milliseconds */
419 polling-delay = <5000>; /* milliseconds */
421 thermal-sensors = <&tsadc 0>;
424 cpu_alert0: cpu_alert0 {
425 temperature = <75000>; /* millicelsius */
426 hysteresis = <2000>; /* millicelsius */
429 cpu_alert1: cpu_alert1 {
430 temperature = <80000>; /* millicelsius */
431 hysteresis = <2000>; /* millicelsius */
435 temperature = <95000>; /* millicelsius */
436 hysteresis = <2000>; /* millicelsius */
443 trip = <&cpu_alert0>;
445 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
448 trip = <&cpu_alert1>;
450 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
456 polling-delay-passive = <100>; /* milliseconds */
457 polling-delay = <5000>; /* milliseconds */
459 thermal-sensors = <&tsadc 1>;
462 gpu_alert0: gpu_alert0 {
463 temperature = <80000>; /* millicelsius */
464 hysteresis = <2000>; /* millicelsius */
468 temperature = <115000>; /* millicelsius */
469 hysteresis = <2000>; /* millicelsius */
476 trip = <&gpu_alert0>;
478 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
484 tsadc: tsadc@ff280000 {
485 compatible = "rockchip,rk3368-tsadc";
486 reg = <0x0 0xff280000 0x0 0x100>;
487 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
489 clock-names = "tsadc", "apb_pclk";
490 resets = <&cru SRST_TSADC>;
491 reset-names = "tsadc-apb";
492 pinctrl-names = "init", "default", "sleep";
493 pinctrl-0 = <&otp_gpio>;
494 pinctrl-1 = <&otp_out>;
495 pinctrl-2 = <&otp_gpio>;
496 #thermal-sensor-cells = <1>;
497 rockchip,hw-tshut-temp = <95000>;
501 gmac: ethernet@ff290000 {
502 compatible = "rockchip,rk3368-gmac";
503 reg = <0x0 0xff290000 0x0 0x10000>;
504 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "macirq";
506 rockchip,grf = <&grf>;
507 clocks = <&cru SCLK_MAC>,
508 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
509 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
510 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
511 clock-names = "stmmaceth",
512 "mac_clk_rx", "mac_clk_tx",
513 "clk_mac_ref", "clk_mac_refout",
514 "aclk_mac", "pclk_mac";
518 usb_host0_ehci: usb@ff500000 {
519 compatible = "generic-ehci";
520 reg = <0x0 0xff500000 0x0 0x100>;
521 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru HCLK_HOST0>;
523 clock-names = "usbhost";
527 usb_otg: usb@ff580000 {
528 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
530 reg = <0x0 0xff580000 0x0 0x40000>;
531 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cru HCLK_OTG0>;
535 g-np-tx-fifo-size = <16>;
536 g-rx-fifo-size = <275>;
537 g-tx-fifo-size = <256 128 128 64 64 32>;
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544 reg = <0x0 0xff650000 0x0 0x1000>;
545 clocks = <&cru PCLK_I2C0>;
547 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c0_xfer>;
550 #address-cells = <1>;
556 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
557 reg = <0x0 0xff660000 0x0 0x1000>;
558 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
562 clocks = <&cru PCLK_I2C1>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2c1_xfer>;
569 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680000 0x0 0x10>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pwm0_pin>;
574 clocks = <&cru PCLK_PWM1>;
580 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
581 reg = <0x0 0xff680010 0x0 0x10>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pwm1_pin>;
585 clocks = <&cru PCLK_PWM1>;
591 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
592 reg = <0x0 0xff680020 0x0 0x10>;
594 clocks = <&cru PCLK_PWM1>;
600 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
601 reg = <0x0 0xff680030 0x0 0x10>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pwm3_pin>;
605 clocks = <&cru PCLK_PWM1>;
610 uart2: serial@ff690000 {
611 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
612 reg = <0x0 0xff690000 0x0 0x100>;
613 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
614 clock-names = "baudclk", "apb_pclk";
615 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&uart2_xfer>;
623 mbox: mbox@ff6b0000 {
624 compatible = "rockchip,rk3368-mailbox";
625 reg = <0x0 0xff6b0000 0x0 0x1000>;
626 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru PCLK_MAILBOX>;
631 clock-names = "pclk_mailbox";
635 pmugrf: syscon@ff738000 {
636 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
637 reg = <0x0 0xff738000 0x0 0x1000>;
639 pmu_io_domains: io-domains {
640 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
645 compatible = "syscon-reboot-mode";
647 mode-normal = <BOOT_NORMAL>;
648 mode-recovery = <BOOT_RECOVERY>;
649 mode-bootloader = <BOOT_FASTBOOT>;
650 mode-loader = <BOOT_BL_DOWNLOAD>;
654 cru: clock-controller@ff760000 {
655 compatible = "rockchip,rk3368-cru";
656 reg = <0x0 0xff760000 0x0 0x1000>;
657 rockchip,grf = <&grf>;
662 grf: syscon@ff770000 {
663 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
664 reg = <0x0 0xff770000 0x0 0x1000>;
666 io_domains: io-domains {
667 compatible = "rockchip,rk3368-io-voltage-domain";
672 wdt: watchdog@ff800000 {
673 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
674 reg = <0x0 0xff800000 0x0 0x100>;
675 clocks = <&cru PCLK_WDT>;
676 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
681 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
682 reg = <0x0 0xff810000 0x0 0x20>;
683 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
686 gic: interrupt-controller@ffb71000 {
687 compatible = "arm,gic-400";
688 interrupt-controller;
689 #interrupt-cells = <3>;
690 #address-cells = <0>;
692 reg = <0x0 0xffb71000 0x0 0x1000>,
693 <0x0 0xffb72000 0x0 0x2000>,
694 <0x0 0xffb74000 0x0 0x2000>,
695 <0x0 0xffb76000 0x0 0x2000>;
696 interrupts = <GIC_PPI 9
697 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
701 compatible = "rockchip,rk3368-pinctrl";
702 rockchip,grf = <&grf>;
703 rockchip,pmu = <&pmugrf>;
704 #address-cells = <0x2>;
708 gpio0: gpio0@ff750000 {
709 compatible = "rockchip,gpio-bank";
710 reg = <0x0 0xff750000 0x0 0x100>;
711 clocks = <&cru PCLK_GPIO0>;
712 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
717 interrupt-controller;
718 #interrupt-cells = <0x2>;
721 gpio1: gpio1@ff780000 {
722 compatible = "rockchip,gpio-bank";
723 reg = <0x0 0xff780000 0x0 0x100>;
724 clocks = <&cru PCLK_GPIO1>;
725 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-controller;
731 #interrupt-cells = <0x2>;
734 gpio2: gpio2@ff790000 {
735 compatible = "rockchip,gpio-bank";
736 reg = <0x0 0xff790000 0x0 0x100>;
737 clocks = <&cru PCLK_GPIO2>;
738 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
743 interrupt-controller;
744 #interrupt-cells = <0x2>;
747 gpio3: gpio3@ff7a0000 {
748 compatible = "rockchip,gpio-bank";
749 reg = <0x0 0xff7a0000 0x0 0x100>;
750 clocks = <&cru PCLK_GPIO3>;
751 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
756 interrupt-controller;
757 #interrupt-cells = <0x2>;
760 pcfg_pull_up: pcfg-pull-up {
764 pcfg_pull_down: pcfg-pull-down {
768 pcfg_pull_none: pcfg-pull-none {
772 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
774 drive-strength = <12>;
779 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
783 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
787 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
790 emmc_bus1: emmc-bus1 {
791 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
794 emmc_bus4: emmc-bus4 {
795 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
796 <1 19 RK_FUNC_2 &pcfg_pull_up>,
797 <1 20 RK_FUNC_2 &pcfg_pull_up>,
798 <1 21 RK_FUNC_2 &pcfg_pull_up>;
801 emmc_bus8: emmc-bus8 {
802 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
803 <1 19 RK_FUNC_2 &pcfg_pull_up>,
804 <1 20 RK_FUNC_2 &pcfg_pull_up>,
805 <1 21 RK_FUNC_2 &pcfg_pull_up>,
806 <1 22 RK_FUNC_2 &pcfg_pull_up>,
807 <1 23 RK_FUNC_2 &pcfg_pull_up>,
808 <1 24 RK_FUNC_2 &pcfg_pull_up>,
809 <1 25 RK_FUNC_2 &pcfg_pull_up>;
814 rgmii_pins: rgmii-pins {
815 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
816 <3 24 RK_FUNC_1 &pcfg_pull_none>,
817 <3 19 RK_FUNC_1 &pcfg_pull_none>,
818 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
819 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
820 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
821 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
822 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
823 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
824 <3 15 RK_FUNC_1 &pcfg_pull_none>,
825 <3 16 RK_FUNC_1 &pcfg_pull_none>,
826 <3 17 RK_FUNC_1 &pcfg_pull_none>,
827 <3 18 RK_FUNC_1 &pcfg_pull_none>,
828 <3 25 RK_FUNC_1 &pcfg_pull_none>,
829 <3 20 RK_FUNC_1 &pcfg_pull_none>;
832 rmii_pins: rmii-pins {
833 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
834 <3 24 RK_FUNC_1 &pcfg_pull_none>,
835 <3 19 RK_FUNC_1 &pcfg_pull_none>,
836 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
837 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
838 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
839 <3 15 RK_FUNC_1 &pcfg_pull_none>,
840 <3 16 RK_FUNC_1 &pcfg_pull_none>,
841 <3 20 RK_FUNC_1 &pcfg_pull_none>,
842 <3 21 RK_FUNC_1 &pcfg_pull_none>;
847 i2c0_xfer: i2c0-xfer {
848 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
849 <0 7 RK_FUNC_1 &pcfg_pull_none>;
854 i2c1_xfer: i2c1-xfer {
855 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
856 <2 22 RK_FUNC_1 &pcfg_pull_none>;
861 i2c2_xfer: i2c2-xfer {
862 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
863 <3 31 RK_FUNC_2 &pcfg_pull_none>;
868 i2c3_xfer: i2c3-xfer {
869 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
870 <1 17 RK_FUNC_1 &pcfg_pull_none>;
875 i2c4_xfer: i2c4-xfer {
876 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
877 <3 25 RK_FUNC_2 &pcfg_pull_none>;
882 i2c5_xfer: i2c5-xfer {
883 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
884 <3 27 RK_FUNC_2 &pcfg_pull_none>;
890 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
896 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
902 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
907 sdio0_bus1: sdio0-bus1 {
908 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
911 sdio0_bus4: sdio0-bus4 {
912 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
913 <2 29 RK_FUNC_1 &pcfg_pull_up>,
914 <2 30 RK_FUNC_1 &pcfg_pull_up>,
915 <2 31 RK_FUNC_1 &pcfg_pull_up>;
918 sdio0_cmd: sdio0-cmd {
919 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
922 sdio0_clk: sdio0-clk {
923 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
927 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
931 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
934 sdio0_pwr: sdio0-pwr {
935 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
938 sdio0_bkpwr: sdio0-bkpwr {
939 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
942 sdio0_int: sdio0-int {
943 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
948 sdmmc_clk: sdmmc-clk {
949 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
952 sdmmc_cmd: sdmmc-cmd {
953 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
957 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
960 sdmmc_bus1: sdmmc-bus1 {
961 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
964 sdmmc_bus4: sdmmc-bus4 {
965 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
966 <2 6 RK_FUNC_1 &pcfg_pull_up>,
967 <2 7 RK_FUNC_1 &pcfg_pull_up>,
968 <2 8 RK_FUNC_1 &pcfg_pull_up>;
974 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
977 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
980 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
983 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
986 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
992 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
995 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
998 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1001 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1004 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1009 spi2_clk: spi2-clk {
1010 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1012 spi2_cs0: spi2-cs0 {
1013 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1016 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1019 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1024 otp_gpio: otp-gpio {
1025 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1029 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1034 uart0_xfer: uart0-xfer {
1035 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1036 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1039 uart0_cts: uart0-cts {
1040 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1043 uart0_rts: uart0-rts {
1044 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1049 uart1_xfer: uart1-xfer {
1050 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1051 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1054 uart1_cts: uart1-cts {
1055 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1058 uart1_rts: uart1-rts {
1059 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1064 uart2_xfer: uart2-xfer {
1065 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1066 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1068 /* no rts / cts for uart2 */
1072 uart3_xfer: uart3-xfer {
1073 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1074 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1077 uart3_cts: uart3-cts {
1078 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1081 uart3_rts: uart3-rts {
1082 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1087 uart4_xfer: uart4-xfer {
1088 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1089 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1092 uart4_cts: uart4-cts {
1093 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1096 uart4_rts: uart4-rts {
1097 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;