arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi

   1 /*
   2  * ARM Ltd. Fast Models
   3  *
   4  * Versatile Express (VE) system model
   5  * Motherboard component
   6  *
   7  * VEMotherBoard.lisa
   8  */
   9
  10         motherboard {
  11                 arm,v2m-memory-map = "rs1";
  12                 compatible = "arm,vexpress,v2m-p1", "simple-bus";
  13                 #address-cells = <2>; /* SMB chipselect number and offset */
  14                 #size-cells = <1>;
  15                 #interrupt-cells = <1>;
  16                 ranges;
  17
  18                 flash@0,00000000 {
  19                         compatible = "arm,vexpress-flash", "cfi-flash";
  20                         reg = <0 0x00000000 0x04000000>,
  21                               <4 0x00000000 0x04000000>;
  22                         bank-width = <4>;
  23                 };
  24
  25                 vram@2,00000000 {
  26                         compatible = "arm,vexpress-vram";
  27                         reg = <2 0x00000000 0x00800000>;
  28                 };
  29
  30                 ethernet@2,02000000 {
  31                         compatible = "smsc,lan91c111";
  32                         reg = <2 0x02000000 0x10000>;
  33                         interrupts = <15>;
  34                 };
  35
  36                 v2m_clk24mhz: clk24mhz {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <24000000>;
  40                         clock-output-names = "v2m:clk24mhz";
  41                 };
  42
  43                 v2m_refclk1mhz: refclk1mhz {
  44                         compatible = "fixed-clock";
  45                         #clock-cells = <0>;
  46                         clock-frequency = <1000000>;
  47                         clock-output-names = "v2m:refclk1mhz";
  48                 };
  49
  50                 v2m_refclk32khz: refclk32khz {
  51                         compatible = "fixed-clock";
  52                         #clock-cells = <0>;
  53                         clock-frequency = <32768>;
  54                         clock-output-names = "v2m:refclk32khz";
  55                 };
  56
  57                 iofpga@3,00000000 {
  58                         compatible = "arm,amba-bus", "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges = <0 3 0 0x200000>;
  62
  63                         v2m_sysreg: sysreg@010000 {
  64                                 compatible = "arm,vexpress-sysreg";
  65                                 reg = <0x010000 0x1000>;
  66                                 gpio-controller;
  67                                 #gpio-cells = <2>;
  68                         };
  69
  70                         v2m_sysctl: sysctl@020000 {
  71                                 compatible = "arm,sp810", "arm,primecell";
  72                                 reg = <0x020000 0x1000>;
  73                                 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
  74                                 clock-names = "refclk", "timclk", "apb_pclk";
  75                                 #clock-cells = <1>;
  76                                 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  77                         };
  78
  79                         aaci@040000 {
  80                                 compatible = "arm,pl041", "arm,primecell";
  81                                 reg = <0x040000 0x1000>;
  82                                 interrupts = <11>;
  83                                 clocks = <&v2m_clk24mhz>;
  84                                 clock-names = "apb_pclk";
  85                         };
  86
  87                         mmci@050000 {
  88                                 compatible = "arm,pl180", "arm,primecell";
  89                                 reg = <0x050000 0x1000>;
  90                                 interrupts = <9 10>;
  91                                 cd-gpios = <&v2m_sysreg 0 0>;
  92                                 wp-gpios = <&v2m_sysreg 1 0>;
  93                                 max-frequency = <12000000>;
  94                                 vmmc-supply = <&v2m_fixed_3v3>;
  95                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
  96                                 clock-names = "mclk", "apb_pclk";
  97                         };
  98
  99                         kmi@060000 {
 100                                 compatible = "arm,pl050", "arm,primecell";
 101                                 reg = <0x060000 0x1000>;
 102                                 interrupts = <12>;
 103                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 104                                 clock-names = "KMIREFCLK", "apb_pclk";
 105                         };
 106
 107                         kmi@070000 {
 108                                 compatible = "arm,pl050", "arm,primecell";
 109                                 reg = <0x070000 0x1000>;
 110                                 interrupts = <13>;
 111                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 112                                 clock-names = "KMIREFCLK", "apb_pclk";
 113                         };
 114
 115                         v2m_serial0: uart@090000 {
 116                                 compatible = "arm,pl011", "arm,primecell";
 117                                 reg = <0x090000 0x1000>;
 118                                 interrupts = <5>;
 119                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 120                                 clock-names = "uartclk", "apb_pclk";
 121                         };
 122
 123                         v2m_serial1: uart@0a0000 {
 124                                 compatible = "arm,pl011", "arm,primecell";
 125                                 reg = <0x0a0000 0x1000>;
 126                                 interrupts = <6>;
 127                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 128                                 clock-names = "uartclk", "apb_pclk";
 129                         };
 130
 131                         v2m_serial2: uart@0b0000 {
 132                                 compatible = "arm,pl011", "arm,primecell";
 133                                 reg = <0x0b0000 0x1000>;
 134                                 interrupts = <7>;
 135                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 136                                 clock-names = "uartclk", "apb_pclk";
 137                         };
 138
 139                         v2m_serial3: uart@0c0000 {
 140                                 compatible = "arm,pl011", "arm,primecell";
 141                                 reg = <0x0c0000 0x1000>;
 142                                 interrupts = <8>;
 143                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 144                                 clock-names = "uartclk", "apb_pclk";
 145                         };
 146
 147                         wdt@0f0000 {
 148                                 compatible = "arm,sp805", "arm,primecell";
 149                                 reg = <0x0f0000 0x1000>;
 150                                 interrupts = <0>;
 151                                 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
 152                                 clock-names = "wdogclk", "apb_pclk";
 153                         };
 154
 155                         v2m_timer01: timer@110000 {
 156                                 compatible = "arm,sp804", "arm,primecell";
 157                                 reg = <0x110000 0x1000>;
 158                                 interrupts = <2>;
 159                                 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
 160                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 161                         };
 162
 163                         v2m_timer23: timer@120000 {
 164                                 compatible = "arm,sp804", "arm,primecell";
 165                                 reg = <0x120000 0x1000>;
 166                                 interrupts = <3>;
 167                                 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
 168                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 169                         };
 170
 171                         rtc@170000 {
 172                                 compatible = "arm,pl031", "arm,primecell";
 173                                 reg = <0x170000 0x1000>;
 174                                 interrupts = <4>;
 175                                 clocks = <&v2m_clk24mhz>;
 176                                 clock-names = "apb_pclk";
 177                         };
 178
 179                         clcd@1f0000 {
 180                                 compatible = "arm,pl111", "arm,primecell";
 181                                 reg = <0x1f0000 0x1000>;
 182                                 interrupts = <14>;
 183                                 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
 184                                 clock-names = "clcdclk", "apb_pclk";
 185                         };
 186
 187                         virtio_block@0130000 {
 188                                 compatible = "virtio,mmio";
 189                                 reg = <0x130000 0x200>;
 190                                 interrupts = <42>;
 191                         };
 192                 };
 193
 194                 v2m_fixed_3v3: fixedregulator@0 {
 195                         compatible = "regulator-fixed";
 196                         regulator-name = "3V3";
 197                         regulator-min-microvolt = <3300000>;
 198                         regulator-max-microvolt = <3300000>;
 199                         regulator-always-on;
 200                 };
 201
 202                 mcc {
 203                         compatible = "arm,vexpress,config-bus", "simple-bus";
 204                         arm,vexpress,config-bridge = <&v2m_sysreg>;
 205
 206                         v2m_oscclk1: osc@1 {
 207                                 /* CLCD clock */
 208                                 compatible = "arm,vexpress-osc";
 209                                 arm,vexpress-sysreg,func = <1 1>;
 210                                 freq-range = <23750000 63500000>;
 211                                 #clock-cells = <0>;
 212                                 clock-output-names = "v2m:oscclk1";
 213                         };
 214
 215                         reset@0 {
 216                                 compatible = "arm,vexpress-reset";
 217                                 arm,vexpress-sysreg,func = <5 0>;
 218                         };
 219
 220                         muxfpga@0 {
 221                                 compatible = "arm,vexpress-muxfpga";
 222                                 arm,vexpress-sysreg,func = <7 0>;
 223                         };
 224
 225                         shutdown@0 {
 226                                 compatible = "arm,vexpress-shutdown";
 227                                 arm,vexpress-sysreg,func = <8 0>;
 228                         };
 229
 230                         reboot@0 {
 231                                 compatible = "arm,vexpress-reboot";
 232                                 arm,vexpress-sysreg,func = <9 0>;
 233                         };
 234
 235                         dvimode@0 {
 236                                 compatible = "arm,vexpress-dvimode";
 237                                 arm,vexpress-sysreg,func = <11 0>;
 238                         };
 239                 };
 240         };