2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 compatible = "socionext,ph1-ld20";
49 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a72", "arm,armv8";
79 enable-method = "spin-table";
80 cpu-release-addr = <0 0x80000100>;
85 compatible = "arm,cortex-a72", "arm,armv8";
87 enable-method = "spin-table";
88 cpu-release-addr = <0 0x80000100>;
93 compatible = "arm,cortex-a53", "arm,armv8";
95 enable-method = "spin-table";
96 cpu-release-addr = <0 0x80000100>;
101 compatible = "arm,cortex-a53", "arm,armv8";
103 enable-method = "spin-table";
104 cpu-release-addr = <0 0x80000100>;
110 compatible = "fixed-clock";
112 clock-frequency = <25000000>;
117 compatible = "fixed-clock";
118 clock-frequency = <58820000>;
123 compatible = "fixed-clock";
124 clock-frequency = <50000000>;
129 compatible = "arm,armv8-timer";
130 interrupts = <1 13 0xf01>,
137 compatible = "simple-bus";
138 #address-cells = <1>;
140 ranges = <0 0 0 0xffffffff>;
142 serial0: serial@54006800 {
143 compatible = "socionext,uniphier-uart";
145 reg = <0x54006800 0x40>;
146 interrupts = <0 33 4>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart0>;
149 clocks = <&uart_clk>;
152 serial1: serial@54006900 {
153 compatible = "socionext,uniphier-uart";
155 reg = <0x54006900 0x40>;
156 interrupts = <0 35 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
159 clocks = <&uart_clk>;
162 serial2: serial@54006a00 {
163 compatible = "socionext,uniphier-uart";
165 reg = <0x54006a00 0x40>;
166 interrupts = <0 37 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_uart2>;
169 clocks = <&uart_clk>;
172 serial3: serial@54006b00 {
173 compatible = "socionext,uniphier-uart";
175 reg = <0x54006b00 0x40>;
176 interrupts = <0 177 4>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart3>;
179 clocks = <&uart_clk>;
183 compatible = "socionext,uniphier-fi2c";
185 reg = <0x58780000 0x80>;
186 #address-cells = <1>;
188 interrupts = <0 41 4>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c0>;
192 clock-frequency = <100000>;
196 compatible = "socionext,uniphier-fi2c";
198 reg = <0x58781000 0x80>;
199 #address-cells = <1>;
201 interrupts = <0 42 4>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c1>;
205 clock-frequency = <100000>;
209 compatible = "socionext,uniphier-fi2c";
210 reg = <0x58782000 0x80>;
211 #address-cells = <1>;
213 interrupts = <0 43 4>;
215 clock-frequency = <400000>;
219 compatible = "socionext,uniphier-fi2c";
221 reg = <0x58783000 0x80>;
222 #address-cells = <1>;
224 interrupts = <0 44 4>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_i2c3>;
228 clock-frequency = <100000>;
232 compatible = "socionext,uniphier-fi2c";
234 reg = <0x58784000 0x80>;
235 #address-cells = <1>;
237 interrupts = <0 45 4>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c4>;
241 clock-frequency = <100000>;
245 compatible = "socionext,uniphier-fi2c";
246 reg = <0x58785000 0x80>;
247 #address-cells = <1>;
249 interrupts = <0 25 4>;
251 clock-frequency = <400000>;
254 system_bus: system-bus@58c00000 {
255 compatible = "socionext,uniphier-system-bus";
257 reg = <0x58c00000 0x400>;
258 #address-cells = <2>;
263 compatible = "socionext,uniphier-smpctrl";
264 reg = <0x59801000 0x400>;
267 pinctrl: pinctrl@5f801000 {
268 compatible = "socionext,ph1-ld20-pinctrl", "syscon";
269 reg = <0x5f801000 0xe00>;
272 gic: interrupt-controller@5fe00000 {
273 compatible = "arm,gic-v3";
274 reg = <0x5fe00000 0x10000>, /* GICD */
275 <0x5fe80000 0x80000>; /* GICR */
276 interrupt-controller;
277 #interrupt-cells = <3>;
278 interrupts = <1 9 4>;
283 /include/ "uniphier-pinctrl.dtsi"