2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 compatible = "socionext,ph1-ld20";
49 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a72", "arm,armv8";
79 enable-method = "spin-table";
80 cpu-release-addr = <0 0x80000100>;
85 compatible = "arm,cortex-a72", "arm,armv8";
87 enable-method = "spin-table";
88 cpu-release-addr = <0 0x80000100>;
93 compatible = "arm,cortex-a53", "arm,armv8";
95 enable-method = "spin-table";
96 cpu-release-addr = <0 0x80000100>;
101 compatible = "arm,cortex-a53", "arm,armv8";
103 enable-method = "spin-table";
104 cpu-release-addr = <0 0x80000100>;
111 compatible = "fixed-clock";
112 clock-frequency = <58820000>;
117 compatible = "fixed-clock";
118 clock-frequency = <50000000>;
123 compatible = "arm,armv8-timer";
124 interrupts = <1 13 0xf01>,
131 compatible = "simple-bus";
132 #address-cells = <1>;
134 ranges = <0 0 0 0xffffffff>;
136 serial0: serial@54006800 {
137 compatible = "socionext,uniphier-uart";
139 reg = <0x54006800 0x40>;
140 interrupts = <0 33 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart0>;
143 clocks = <&uart_clk>;
146 serial1: serial@54006900 {
147 compatible = "socionext,uniphier-uart";
149 reg = <0x54006900 0x40>;
150 interrupts = <0 35 4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart1>;
153 clocks = <&uart_clk>;
156 serial2: serial@54006a00 {
157 compatible = "socionext,uniphier-uart";
159 reg = <0x54006a00 0x40>;
160 interrupts = <0 37 4>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart2>;
163 clocks = <&uart_clk>;
166 serial3: serial@54006b00 {
167 compatible = "socionext,uniphier-uart";
169 reg = <0x54006b00 0x40>;
170 interrupts = <0 177 4>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_uart3>;
173 clocks = <&uart_clk>;
177 compatible = "socionext,uniphier-fi2c";
179 reg = <0x58780000 0x80>;
180 #address-cells = <1>;
182 interrupts = <0 41 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c0>;
186 clock-frequency = <100000>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58781000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 42 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c1>;
199 clock-frequency = <100000>;
203 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58782000 0x80>;
206 #address-cells = <1>;
208 interrupts = <0 43 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c2>;
212 clock-frequency = <100000>;
216 compatible = "socionext,uniphier-fi2c";
218 reg = <0x58783000 0x80>;
219 #address-cells = <1>;
221 interrupts = <0 44 4>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c3>;
225 clock-frequency = <100000>;
229 compatible = "socionext,uniphier-fi2c";
230 reg = <0x58784000 0x80>;
231 #address-cells = <1>;
233 interrupts = <0 45 4>;
235 clock-frequency = <400000>;
239 compatible = "socionext,uniphier-fi2c";
240 reg = <0x58785000 0x80>;
241 #address-cells = <1>;
243 interrupts = <0 25 4>;
245 clock-frequency = <400000>;
249 compatible = "socionext,uniphier-fi2c";
250 reg = <0x58786000 0x80>;
251 #address-cells = <1>;
253 interrupts = <0 26 4>;
255 clock-frequency = <400000>;
258 system_bus: system-bus@58c00000 {
259 compatible = "socionext,uniphier-system-bus";
261 reg = <0x58c00000 0x400>;
262 #address-cells = <2>;
267 compatible = "socionext,uniphier-smpctrl";
268 reg = <0x59801000 0x400>;
271 pinctrl: pinctrl@5f801000 {
272 compatible = "socionext,ph1-ld20-pinctrl", "syscon";
273 reg = <0x5f801000 0xe00>;
276 gic: interrupt-controller@5fe00000 {
277 compatible = "arm,gic-v3";
278 reg = <0x5fe00000 0x10000>, /* GICD */
279 <0x5fe80000 0x80000>; /* GICR */
280 interrupt-controller;
281 #interrupt-cells = <3>;
282 interrupts = <1 9 4>;
287 /include/ "uniphier-pinctrl.dtsi"